Dead-time minimisation using active voltage control gate drive for high-power IGBT converters

High-power converters usually need longer dead-times than their lower-power counterparts and a lower switching frequency. Also due to the complicated assembly layout and severe variations in parasitics, in practice the conventional dead-time specific adjustment or compensation for high-power converters is less effective, and usually this process is time-consuming and bespoke. For general applications, minimising or eliminating dead-time in the gate drive technology is a desirable solution. With the growing acceptance of power electronics building blocks (PEBB) and intelligent power modules (IPM), gate drives with intelligent functions are in demand. Smart functions including dead time elimination/minimisation can improve modularity, flexibility and reliability. In this paper, a dead-time minimisation using Active Voltage Control (AVC) gate drive is presented. © 2012 IEEE.

Evaluation and modeling of lanthanum diffusion in TiN/La 2O 3/HfSiON/SiO 2/Si high-k stacks

In this study, TiN/La 2O 3/HfSiON/SiO 2/Si gate stacks with thick high-k (HK) and thick pedestal oxide were used. Samples were annealed at different temperatures and times in order to characterize in detail the interaction mechanisms between La and the gate stack layers. Time-of-flight secondary ion mass spectrometry (ToF-SIMS) measurements performed on these samples show a time diffusion saturation of La in the high-k insulator, indicating an La front immobilization due to LaSiO formation at the high-k/interfacial layer. Based on the SIMS data, a technology computer aided design (TCAD) diffusion model including La time diffusion saturation effect was developed. © 2012 American Institute of Physics.

Precursor flow rate manipulation for the controlled fabrication of twin-free GaAs nanowires on silicon substrates

Vertically oriented GaAs nanowires (NWs) are grown on Si(111) substrates using metal-organic chemical vapor deposition. Controlled epitaxial growth along the 111 direction is demonstrated following the deposition of thin GaAs buffer layers and the elimination of structural defects, such as twin defects and stacking faults, is found for high growth rates. By systematically manipulating the AsH 3 (group-V) and TMGa (group-III) precursor flow rates, it is found that the TMGa flow rate has the most significant effect on the nanowire quality. After capping the minimal tapering and twin-free GaAs NWs with an AlGaAs shell, long exciton lifetimes (over 700ps) are obtained for high TMGa flow rate samples. It is observed that the Ga adatom concentration significantly affects the growth of GaAs NWs, with a high concentration and rapid growth leading to desirable characteristics for optoelectronic nanowire device applications including improved morphology, crystal structure and optical performance. © 2012 IOP Publishing Ltd.

Designing folding rings using polynomial continuation

© 2014 by ASME. Two types of foldable rings are designed using polynomial continuation. The first type of ring, when deployed, forms regular polygons with an even number of sides and is designed by specifying a sequence of orientations which each bar must attain at various stages throughout deployment. A design criterion is that these foldable rings must fold with all bars parallel in the stowed position. At first, all three Euler angles are used to specify bar orientations, but elimination is also used to reduce the number of specified Euler angles to two, allowing greater freedom in the design process. The second type of ring, when deployed, forms doubly plane-symmetric (irregular) polygons. The doubly symmetric rings are designed using polynomial continuation, but in this example a series of bar end locations (in the stowed position) is used as the design criterion with focus restricted to those rings possessing eight bars.

Top down scale-up of semiconducting nanostructures for large area electronics

In this paper, we present a study on electrical and optical characteristics of n-type tin-oxide nanowires integrated based on top-down scale-up strategy. Through a combination of contact printing and plasma based back-channel passivation, we have achieved stable electrical characteristics with standard deviation in mobility and threshold voltage of 9.1% and 25%, respectively, for a large area of 1× 1 cm2 area. Through use of contact printing, high alignment of nanowires was achieved thus minimizing the number of nanowire-nanowire junctions, which serve to limit carrier transport in the channel. In addition, persistent photoconductivity has been observed, which we attribute to oxygen vacancy ionization and subsequent elimination using a gate pulse driving scheme. © 2014 IEEE.

Lean product development in practice: Insights from 4 companies

This paper aims to elucidate practitioners' understanding and implementation of Lean in Product Development (LPD). We report on a workshop held in the UK during 2012. Managers and engineers from four organizations discussed their understanding of LPD and their ideas and practice regarding management and assessment of value and waste. The study resulted in a set of insights into current practice and lean thinking from the industry perspective. Building on this, the paper introduces a balanced value and waste model that can be used by practitioners as a checklist to identify issues that need to be considered when applying LPD. The main results indicate that organizations tend to focus on waste elimination rather than value enhancement in LPD. Moreover, the lean metrics that were discussed by the workshop participants do not link the strategic level with the operational one, and poorly reflect the value and waste generated in the process. Future directions for research are explored, and include the importance of a balanced approach considering both value and waste when applying LPD, and the need to link lean metrics with value and waste levels.