GaN-based LEDs grown on 6-inch diameter Si (111) substrates by MOVPE

The issues and challenges of growing GaN-based structures on large area Si substrates have been studied. These include Si slip resulting from large temperature non-uniformities and cracking due to differential thermal expansion. Using an A1N nucleation layer in conjunction with an AlGaN buffer layer for stress management, and together with the interactive use of real time in-situ optical monitoring it was possible to realise flat, crack-free and uniform GaN and LED structures on 6-inch Si (111) substrates. The EL performance of processed LED devices was also studied on-wafer, giving good EL characteristics including a forward bias voltage of ∼3.5 V at 20 mA from a 500 μm × 500 μm device. © 2009 SPIE.

InGaN/GaN LEDs grown on Si(111): Dependence of device performance on threading dislocation density and emission wavelength

We demonstrate the growth of crack-free blue and greenemitting LED structures grown on 2-inch and 6-inch Si(111) substrates by metalorganic vapour phase epitaxy (MOVPE), using AlN nucleation layers and AlGaN buffer layers for stress management. LED device performance and its dependence on threading dislocation (TD) density and emission wavelength were studied. Despite the inherently low light extraction efficiency, an output power of 1.2 mW at 50 mA was measured from a 500 μm square planar device, emitting at 455 nm. The light output decreases dramatically as the emission wavelength increases from 455 nm to 510 nm. For LED devices emitting at similar wavelength, the light output was more than doubled when the TD density was reduced from 5×1 09 cm-2 to 2×109 cm-2. Our results clearly show that high TD density is detrimental to the overall light output, highlighting the need for further TD reduction for structures grown on Si. © 2010 Wiley-VCH Verlag GmbH & Co. KGaA.

Efficiency measurement of GaN-based quantum well and light-emitting diode structures grown on silicon substrates

The optical efficiency of GaN-based multiple quantum well (MQW) and light emitting diode (LED) structures grown on Si(111) substrates by metal-organic vapor phase epitaxy was measured and compared with equivalent structures on sapphire. The crystalline quality of the LED structures was comprehensively characterized using x-ray diffraction, atomic force microscopy, and plan-view transmission electron microscopy. A room temperature photoluminescence (PL) internal quantum efficiency (IQE) as high as 58% has been achieved in an InGaN/GaN MQW on Si, emitting at 460 nm. This is the highest reported PL-IQE of a c-plane GaN-based MQW on Si, and the radiative efficiency of this sample compares well with similar structures grown on sapphire. Processed LED devices on Si also show good electroluminescence (EL) performance, including a forward bias voltage of ∼3.5 V at 20 mA and a light output power of 1 mW at 45 mA from a 500 ×500 μm2 planar device without the use of any additional techniques to enhance the output coupling. The extraction efficiency of the LED devices was calculated, and the EL-IQE was then estimated to have a maximum value of 33% at a current density of 4 A cm-2, dropping to 30% at a current density of 40 A cm-2 for a planar LED device on Si emitting at 455 nm. The EL-IQE was clearly observed to increase as the structural quality of the material increased for devices on both sapphire and Si substrates. © 2011 American Institute of Physics.

Post-CMOS wafer level growth of carbon nanotubes for low-cost microsensors--a proof of concept.

Here we demonstrate a novel technique to grow carbon nanotubes (CNTs) on addressable localized areas, at wafer level, on a fully processed CMOS substrate. The CNTs were grown using tungsten micro-heaters (local growth technique) at elevated temperature on wafer scale by connecting adjacent micro-heaters through metal tracks in the scribe lane. The electrical and optical characterization show that the CNTs are identical and reproducible. We believe this wafer level integration of CNTs with CMOS circuitry enables the low-cost mass production of CNT sensors, such as chemical sensors.

Materials and devices toward three-dimensional integration

It has been shown that the apparent benefits of a two-layer stacked SOI system, i.e. packing density and speed improvements, are less than could be expected in the context of a VLSI requirement [1]. In this project the stacked SOI system has been identified as having major application in the realization of integrated, mixed technology systems. Zone-melting-recrystallization (ZMR) with lasers and electron beams have been used to produce device quality SOI material and a small test-bed circuit has been designed as a demonstration of the feasibility of this approach. © 1988.

Analytic model for turn off in the silicon-on-insulator LIGBT

Lateral insulated gate bipolar transistors (LIGBTs) in silicon-on-insulator (SOI) show a unique turn off characteristic when compared to junction-isolated RESURF LIGBTs or vertical IGBTs. The turn off characteristic shows an extended `terrace' where, after the initial fast transient characteristic of IGBTs due to the loss of the electron current, the current stays almost at the same value for an extended period of time, before suddenly dropping to zero. In this paper, we show that this terrace arises because there is a value of LIGBT current during switch off where the rate of expansion of the depletion region with respect to the anode current is infinite. Once this level of anode current is approached, the depletion region starts to expand very rapidly, and is only stopped when it reaches the n-type buffer layer surrounding the anode. Once this happens, the current rapidly drops to zero. A quasi-static analytic model is derived to explain this behaviour. The analytically modelled turn off characteristic agrees well with that found by numerical simulation.

Numerical modelling of lubricated foil rolling

A model of lubricated cold strip rolling (1, 2) is extended to the thin foil regime. The model considers the evolution of asperity geometry and lubricant pressure through the bite, treating the strip using a conventional slab model. The elastic deflections of the rolls are coupled into the problem using an elastic finite element model. Friction between the roll and the asperities on the strip is modelled using the Coulomb and Tresca friction factor approaches. The shear stress in the Coulomb friction model is limited to the shear yield stress of the strip. A novel modification to these standard friction laws is used to mimic slipping friction in the reduction regions and sticking friction in a central neutral zone. The model is able to reproduce the sticking and slipping zones predicted by Fleck et al. (3). The variation of rolling load, lubricant film thickness and asperity contact area with rolling speed is examined, for conditions typical of rolling aluminium foil from a thickness of 50 to 25 μm. T he contact area and hence friction rises as the speed drops, leading to a large increase in rolling load. This increase is considerably more marked using Coulomb friction as compared with the friction factor approach. Forward slip increases markedly as the speed falls and a significant sticking region develops.

Ink-jet printing for patterning engineering surfaces

This work explored the use of industrial drop-on-demand inkjet printing for masking steel surfaces on engineering components, followed by chemical etching, to produce patterned surfaces. A solvent-based ink was printed on to mild steel samples and the influences of substrate topography and substrate temperature were investigated. Contact angle measurements were used to assess wettability. Regular patterns of circular spots (∼60 /on diameter) and more complex mask patterns were printed. Variation of the substrate temperature had negligible effect on the final size of the printed drops or on the resolution achieved. Colored optical interference fringes were observed on the dried ink deposits and correlated with film thickness measurements by whitelight interferometry.

Unsteady ejectors: The effect of driver jet mark-space ratio

mark Unsteady ejectors can be driven by a wide range of driver jets. These vary from pulse detonation engines, which typically have a long gap between each slug of fluid exiting the detonation tube (mark-space ratios in the range 0.1-0.2) to the exit of a pulsejet where the mean mass flow rate leads to a much shorter gap between slugs (mark-space ratios in the range 2-3). The aim of this paper is to investigate the effect of mark-space ratio on the thrust augmentation of an unsteady ejector. Experimental testing was undertaken using a driver jet with a sinusoidal exit velocity profile. The mean value, amplitude and frequency of the velocity profile could be changed allowing the length to diameter ratio of the fluid slugs L/D and the mark-space ratio (the ratio of slug length to the spacing between slugs) L/S to be varied. The setup allowed L/S of the jet to vary from 0.8 to 2.3, while the L/D ratio of the slugs could take any values between 3.5 and 7.5. This paper shows that as the mark-space ratio of the driver jet is increased the thrust augmentation drops. Across the range of mark-space ratios tested, there is shown to be a drop in thrust augmentation of 0.1. The physical cause of this reduction in thrust augmentation is shown to be a decrease in the percentage time over which the ejector entrains ambient fluid. This is the direct result ofthe space between consecutive slugs in the driver jet decreasing. The one dimensional model reported in Heffer et al. [1] is extended to include the effect of varying L/S and is shown to accurately capture the experimentally measured behavior ofthe ejector. Copyright © 2010 by the American Institute of Aeronautics and Astronautics, Inc.