Performance of CMOS Devices in Silicon-on-Sapphire Films After Solid-Phase Epitaxial Growth With Rapid Electron-Beam Heating

The crystal quality of 0.3-μm-thick as-grown epitaxial silicon-on-sapphire (SOS) was improved using solid-phase epitaxy (SPE) by implantation with silicon to 1015 ions/cm2 at 175 keV and rapid annealing using electron-beam heating, n-channel and p-channel transistormobilities increased by 31 and 19 percent, respectively, and a reduction in ring-oscillator stage delay confirmed that crystal defects near the upper silicon surface had been removed. Leakage in n-channel transistors was not significantly affected by the regrowth process but for p-channel transistors back-channel leakage was considerably greater than for the control devices. This is attributed to aluminum released by damage to the sapphire during silicon implantation. © 1985 IEEE

Balanced parametrizations and canonical forms for system identification

This paper contains a review of recent results concerning the parametrization of asymptotically stable linear systems using balanced realizations. Particular emphasis is given on the application of these results to system identification. This work is part of a continuing programme aimed at elucidating the role of balanced realization in system identification.

200-V lateral superjunction LIGBT on partial SOI

This letter presents a novel lateral superjunction lateral insulated-gate bipolar transistor (LIGBT) in partial silicon-on-insulator (SOI) technology in 0.18-μm partial-SOI (PSOI) high-voltage (HV) process. For an n-type superjunction LIGBT, the p-layer in the superjunction drift region not only helps in achieving uniform electric field distribution but also contributes to the on-state current. The superjunction LIGBT successfully achieves a breakdown voltage (BV) of 210 V with an R dson of 765 mΩ ̇ mm 2. It exhibits half the value of specific on-state resistance R dson and three times higher saturation current (I dsat) for the same BV, compared to a comparable lateral superjunction laterally diffused metal-oxide-semiconductor fabricated in the same technology. It also performs well in higher temperature dc operation with 38.8% increase in R dson at 175°C, compared to the room temperature without any degradation in latch-up performance. To realize this device, it only requires one additional mask layer into X-FAB 0.18-μm PSOI HV process. © 2012 IEEE.

Superjunction IGBT filling the gap between SJ MOSFET and ultrafast IGBT

In this letter, we report E off-versus-V ce tradeoff curves for vertical superjunction insulated-gate bipolar transistors (SJ IGBTs), exhibiting unusual inverse slopes dE off/dV ce > 0 in a transition region between purely unipolar and strongly bipolar device behaviors. This effect is due to the action of p-pillar hole current when depleting the drift layer of SJ IGBTs during turnoff and the impact of current gain on the transconductance. Such SJ IGBTs surpass by a very significant margin their superjunction MOSFET counterparts in terms of power-handling capability and on-state and turnoff losses, all at the same time. © 2012 IEEE.

Analytical field-effect method for extraction of subgap states in thin-film transistors

We present an analytical field-effect method to extract the density of subgap states (subgap DOS) in amorphous semiconductor thin-film transistors (TFTs), using a closed-form relationship between surface potential and gate voltage. By accounting the interface states in the subthreshold characteristics, the subgap DOS is retrieved, leading to a reasonably accurate description of field-effect mobility and its gate voltage dependence. The method proposed here is very useful not only in extracting device performance but also in physically based compact TFT modeling for circuit simulation. © 2012 IEEE.

Gate commutated thyristor with voltage independent maximum controllable current

In this letter, we use a novel 3-D model, earlier calibrated with experimental results on standard gate commutated thyristors (GCTs), with the aim to explain the physics behind the high-power technology (HPT) GCT, to investigate what impact this design would have on 24 mm diameter GCTs, and to clarify the mechanisms that limit safe switching at different dc-link voltages. The 3-D simulation results show that the HPT design can increase the maximum controllable current in 24 mm diameter devices beyond the realm of GCT switching, known as the hard-drive limit. It is proposed that the maximum controllable current becomes independent of the dc-link voltage for the complete range of operating voltage. © 1980-2012 IEEE.

Improved switching uniformity and low-voltage operation in TaO x-based RRAM using Ge reactive layer

Significant improvements in the spatial and temporal uniformities of device switching parameters are successfully demonstrated in Ge/TaOx bilayer-based resistive switching devices, as compared with non-Ge devices. In addition, the reported Ge/TaOx devices also show significant reductions in the operation voltages. Influence of the Ge layer on the resistive switching of TaOx-based resistive random access memory is investigated by X-ray spectroscopy and the theory of Gibbs free energy. Higher uniformity is attributed to the confinement of the filamentary switching process. The presence of a larger number of interface traps, which will create a beneficial electric field to facilitate the drift of oxygen vacancies, is believed to be responsible for the lower operation voltages in the Ge/TaO x devices. © 1980-2012 IEEE.