Transient crosstalk in LCOS based WSS and a method to suppress the crosstalk levels

The origin of the transient crosstalk (TC) in a phase-only LCOS based WSS using a Fourier transform setup was investigated and identified. Two methods were proposed to reduce the TC by at least 5dB without the need to modify the optics or electronics in use. © 2013 OSA.

Transient Crosstalk in LCOS Based WSS and a Method to Suppress the Crosstalk Levels

The origin of the transient crosstalk (TC) in a phase-only LCOS based WSS using a Fourier transform setup was investigated and identified. Two methods were proposed to reduce the TC by at least 5dB without the need to modify the optics or electronics in use. © 2013 OSA.

Origin of transient crosstalk and its reduction in phase-only LCOS wavelength selective switches

The transient crosstalk in a phase-only liquid crystal on silicon (LCOS) based wavelength selective switch using a Fourier transform setup was investigated. Its origin was identified using an in situ test procedure and found to be related to the transient phase patterns displayed by the LCOS device during the switching. Two different methods were proposed to reduce the transient crosstalk without the need to modify the optics or electronics in use. Experimental results show both methods are able to reduce the worst-case transient crosstalk by at least 5 dB. © 1983-2013 IEEE.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

LES of heat transfer in electronics

Numerical methods based on the Reynolds Averaged Navier-Stokes (RANS) and Large Eddy Simulation (LES) equations are applied to the thermal prediction of flows representative of those found in and around electronics systems and components. Low Reynolds number flows through a heated ribbed channel, around a heated cube and within a complex electronics system case are investigated using linear and nonlinear LES models, hybrid RANS-LES and RANS-Numerical-LES (RANS-NLES) methods. Flow and heat transfer predictions using these techniques are in good agreement with each other and experimental data for a range of grid resolutions. Using second order central differences, the RANS-NLES method performs well for all simulations. © 2011 Elsevier Inc.

Strategies for modeling turbulent flows in electronics

Hybrid methods based on the Reynolds Averaged Navier Stokes (RANS) equations and the Large Eddy Simulation (LES) formulation are investigated to try and improve the accuracy of heat transfer and surface temperature predictions for electronics systems and components. Two relatively low Reynolds number flows are studied using hybrid RANS-LES, RANS-Implicit-LES (RANS-ILES) and non-linear LES models. Predictions using these methods are in good agreement with each other, even using different grid resolutions. © 2008 IEEE.

Review of computational aeroacoustics for application in electronics cooler noise

A review of computational aeroacoustics (CCA) was made for application in electronics cooler noise. Computational aeroacoustics encompasses all numerical methods where the purposes is to predict the noise emissions from a simulated flow. Numerical simulation of the flow inside and around heat sinks and fans can lead to a prediction of the emitted noise while they are still in the design phase. Direct CCA is theoretically the best way to predict flow-based acoustic phenomena numerically. It is typically used only for low-frequency sound prediction. The boundary element method offers low computational cost and does not use a computational grid, but instead use vortex-surface calculations to determine tonal noise. Axial fans are commonly used to increase the airflow and thus the heat transfer over the heat sinks within the computer cases. Very detailed source simulations in the fan and heat sink region coupled with the use of analogy methods could result in excellent simulation results with a reasonable computational effort.

Progresses in organic field effect transistors and molecular electronics

In the past years, organic materials have been extensively investigated as an electronic material for organic field effect transistors (OFETs). In this paper, we briefly summarize the current status of organic field effect transistors including materials design, device physics, molecular electronics and the application of carbon nanotubes in molecular electronics. Future prospects and investigations required to improve the OFET performance are also involved.