Computation of high-stability DC balancing scheme for ferroelectric liquid crystal on silicon holograms using graphics processing units.

Spatial light modulators based around liquid crystal on silicon have found use in a variety of telecommunications applications, including the optimization of multimode fibers, free-space communications, and wavelength selective switching. Ferroelectric liquid crystals are attractive in these areas due to their fast switching times and high phase stability, but the necessity for the liquid crystal to spend equal time in each of its two possible states is an issue of practical concern. Using the highly parallel nature of a graphics processing unit architecture, it is possible to calculate DC balancing schemes of exceptional quality and stability.

Advanced DC link capacitor technology application for a stiff voltage-source inverter

Problem of DC link size in a stiff voltage-source inverter for electric drive is described in the paper. Advantages of advanced film capacitor technology over conventional one for DC link application are reviewed. Conventional DC link capacitor selection methods are questioned in view of advanced capacitor technology utilization in stiff voltage-source inverter. For capacitor selection maximum ripple rms current point is shown. DC link ripple current spectrum analysis under modern PWM techniques is presented. Some capacitor selection recommendations are given. The analysis has been aided greatly by computer modeling in PSpice. ©2005 IEEE.

A fully integrated 660 MHz low-swing energy-recycling DC-DC converter

A fully integrated 0.18 μm DC-DC buck converter using a low-swing "stacked driver" configuration is reported in this paper. A high switching frequency of 660 MHz reduces filter components to fit on chip, but this suffers from high switching losses. These losses are reduced using: 1) low-swing drivers; 2) supply stacking; and 3) introducing a charge transfer path to deliver excess charge from the positive metal-oxide semiconductor drive chain to the load, thereby recycling the charge. The working prototype circuit converts 2.2 to 0.75-1.0 V at 40-55 mA. Design and simulation of an improved circuit is also included that further improves the efficiency by enhancing the charge recycling path, providing automated zero voltage switching (ZVS) operation, and synchronizing the half-swing gating signals. © 2009 IEEE.

Wave energy emulator and AC/DC rectifiers for direct drive wave energy converters

This paper describes a solid state electrical emulator devised for laboratory testing of power conditioning electronics for direct drive linear wave energy converters (DDLWEC). Two rectification strategies are considered; a uni-directional boost topology, and an H-bridge which may be controlled in either uni- or bidirectional modes.

The Ic behavior of 2G YBCO tapes under DC/AC magnetic fields at various temperatures

In order to design a High Temperature Superconducting (HTS) machine that is able to operate safely and reliably, studies on the characterization of Second Generation (2G) HTS tapes are of paramount importance. This paper presents an experimental setup to measure critical current of 2G HTS tapes in high DC magnetic fields (up to 5 Tesla) with an AC current ripple superimposed, as well as various temperatures ranging from 25 K to 77 K. The 2G tape measured is the SGS12050 coated conductor made by SuperPower. The critical current is measured by a flux vector with reference to the widest sample face from 0 to 90 degrees in 10 degree steps. Smaller steps are required close to 0 . A Variable Temperature Insert (VTI) is utilized to control temperature change. © 2010 IEEE.

Angular dependence of domain wall resistivity in artificial magnetic domain structures.

We exploit the ability to precisely control the magnetic domain structure of perpendicularly magnetized Pt/Co/Pt trilayers to fabricate artificial domain wall arrays and study their transport properties. The scaling behavior of this model system confirms the intrinsic domain wall origin of the magnetoresistance, and systematic studies using domains patterned at various angles to the current flow are excellently described by an angular-dependent resistivity tensor containing perpendicular and parallel domain wall resistivities. We find that the latter are fully consistent with Levy-Zhang theory, which allows us to estimate the ratio of minority to majority spin carrier resistivities, rho downward arrow/rho upward arrow approximately 5.5, in good agreement with thin film band structure calculations.

SoC energy savings = reduce+reuse+recycle: A case study using a 660MHz DC-DC converter with integrated output filter

This paper advocates 'reduce, reuse, recycle' as a complete energy savings strategy. While reduction has been common to date, there is growing need to emphasize reuse and recycling as well. We design a DC-DC buck converter to demonstrate the 3 techniques: reduce with low-swing and zero voltage switching (ZVS), reuse with supply stacking, and recycle with regulated delivery of excess energy to the output load. The efficiency gained from these 3 techniques helps offset the loss of operating drivers at very high switching frequencies which are needed to move the output filter completely on-chip. A prototype was fabricated in 0.18μm CMOS, operates at 660MHz, and converts 2.2V to 0.75-1.0V at ∼50mA.1 © 2008 IEEE.

Energy recovery from high-frequency clocks using DC-DC converters

Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large capacitor is wasted. Instead, the energy can be recovered using an on-chip DC-DC converter. This paper investigates the integration of two DC-DC converter topologies, boost and buck-boost, with a high-speed clock driver. The high operating frequency significantly shrinks the required size of the L and C components so they can be placed on-chip; typical converters place them off-chip. The clock driver and DC-DC converter are able to share the entire tapered buffer chain, including the widest drive transistors in the final stage. To achieve voltage regulation, the clock duty cycle must be modulated; implying only single-edge-triggered flops should be used. However, this minor drawback is eclipsed by the benefits: by recovering energy from the clock, the output power can actually exceed the additional power needed to operate the converter circuitry, resulting in an effective efficiency greater than 100%. Furthermore, the converter output can be used to operate additional power-saving features like low-voltage islands or body bias voltages. ©2008 IEEE.

A 660MHz ZVS DC-DC converter using gate-driver charge-recycling in 0.18μm CMOS with an integrated output filter

The design and manufacture of a prototype chip level power supply is described, with both simulated and experimental results. Of particular interest is the inclusion of a fully integrated on-chip LC filter. A high switching frequency of 660MHz and the design of a device drive circuit reduce losses by supply stacking, low-swing signaling and charge recycling. The paper demonstrates that a chip level converter operating at high frequency can be built and shows how this can be achieved, using zero voltage switching techniques similar to those commonly used in larger converters. Both simulations and experimental data from a fabricated circuit in 0.18μm CMOS are included. The circuit converts 2.2V to 0.75∼1.0V at ∼55mA. ©2008 IEEE.