40 Gbit/s optical communication system

The University of Bristol is studying the feasibility of deploying 40 Gbit/s optical time division multiplexed (OTDM) transmission networks to support new telecommunication services such the Internet and video-on-demand systems. Among the functional blocks being considered in the project are the optical pulse sources, signal multiplexers and demultiplexers, clock recovery subsystems, signal detection and dispersion accommodation methods.

10-Gbits/s all-optical 3R regeneration and format conversion using a gain-switched DFB laser

A strain-compensated multiple quantum well device is used as a DFB laser, this has been optimized for low jitter gain switched operation at 10 GHz. The signal is transmitted down 80 km of standard fiber then amplified, filtered and polarization controlled before being injected into a DFB laser. The purpose of this regeneration process is to gain switch the DFB with the extracted clock signal in order to retime the converted signal. This process also simultaneously converts the input NRZ format to an output RZ data to format and results in a signal whose optical power and extinction ratio are considerably improved by the regeneration process.

Investigating the relationships between user capabilities and product demands for older and disabled users

This paper presents the results of a study that specifically looks at the relationships between measured user capabilities and product demands in a sample of older and disabled users. An empirical study was conducted with 19 users performing tasks with four consumer products (a clock-radio, a mobile phone, a blender and a vacuum cleaner). The sensory, cognitive and motor capabilities of each user were measured using objective capability tests. The study yielded a rich dataset comprising capability measures, product demands, outcome measures (task times and errors), and subjective ratings of difficulty. Scatter plots were produced showing quantified product demands on user capabilities, together with subjective ratings of difficulty. The results are analysed in terms of the strength of correlations observed taking into account the limitations of the study sample. Directions for future research are also outlined. © 2011 Springer-Verlag.

Embedded Model Predictive Control (MPC) using a FPGA

Model Predictive Control (MPC) is increasingly being proposed for application to miniaturized devices, fast and/or embedded systems. A major obstacle to this is its computation time requirement. Continuing our previous studies of implementing constrained MPC on Field Programmable Gate Arrays (FPGA), this paper begins to exploit the possibilities of parallel computation, with the aim of speeding up the MPC implementation. Simulation studies on a realistic example show that it is possible to implement constrained MPC on an FPGA chip with a 25MHz clock and achieve MPC implementation rates comparable to those achievable on a Pentium 3.0 GHz PC. Copyright © 2007 International Federation of Automatic Control All Rights Reserved.

Energy recovery from high-frequency clocks using DC-DC converters

Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large capacitor is wasted. Instead, the energy can be recovered using an on-chip DC-DC converter. This paper investigates the integration of two DC-DC converter topologies, boost and buck-boost, with a high-speed clock driver. The high operating frequency significantly shrinks the required size of the L and C components so they can be placed on-chip; typical converters place them off-chip. The clock driver and DC-DC converter are able to share the entire tapered buffer chain, including the widest drive transistors in the final stage. To achieve voltage regulation, the clock duty cycle must be modulated; implying only single-edge-triggered flops should be used. However, this minor drawback is eclipsed by the benefits: by recovering energy from the clock, the output power can actually exceed the additional power needed to operate the converter circuitry, resulting in an effective efficiency greater than 100%. Furthermore, the converter output can be used to operate additional power-saving features like low-voltage islands or body bias voltages. ©2008 IEEE.

Energy recycling from multigigahertz clocks using fully integrated switching converters

Large digital chips use a significant amount of energy to broadcast a low-skew, multigigahertz clock to millions of latches located throughout the chip. Every clock cycle, the large aggregate capacitance of the clock network is charged from the supply and then discharged to ground. Instead of wasting this stored energy, it is possible to recycle the energy by controlling its delivery to another part of the chip using an on-chip dc-dc converter. The clock driver and switching converter circuits share many compatible characteristics that allow them to be merged into a single design and fully integrated on-chip. Our buck converter prototype, manufactured in 90-nm CMOS, provides a proof-of-concept that clock network energy can be recycled to other parts of the chip, thus lowering overall energy consumption. It also confirms that monolithic multigigahertz switching converters utilizing zero-voltage switching can be implemented in deep-submicrometer CMOS. With multigigahertz operation, fully integrated inductors and capacitors use a small amount of chip area with low losses. Combining the clock driver with the power converter can share the large MOSFET drivers necessary as well as being energy and space efficient. We present an analysis of the losses which we confirm by experimentally comparing the merged circuit with a conventional clock driver. © 2012 IEEE.

APSK coded modulation schemes for nonlinear satellite channels with high power and spectral efficiency

A new class of 16-ary Amplitude Phase Shift Keying (APSK) coded modulations deemed double-ring PSK modulations best suited for (satellite) nonlinear channels is proposed. Constellation parameters optimization has been based on geometric and information-theoretic considerations. Furthermore, pre- and post-compensation techniques to reduce the nonlinearity impact have been examined. Digital timing clock and carrier phase have been derived and analyzed for a Turbo coded version of the same new modulation scheme. Finally, the performance of state-of the art Turbo coded modulation for this new 16-ary digital modulation has been investigated and compared to the known TCM schemes. It is shown that for the same coding scheme, double-ring APSK modulation outperforms classical 16-QAM and 16-PSK over a typical satellite nonlinear channel due to its intrinsic robustness against the High Power Amplifier (HPA) nonlinear characteristics. The new modulation is shown to be power- and spectrally-efficient, with interesting applications to satellite communications. © 2002 by the American Institute of Aeronautics and Astronautics, Inc.