33 resultados para Borate buffer
Resumo:
Lateral insulated gate bipolar transistors (LIGBTs) in silicon-on-insulator (SOI) show a unique turn off characteristic when compared to junction-isolated RESURF LIGBTs or vertical IGBTs. The turn off characteristic shows an extended `terrace' where, after the initial fast transient characteristic of IGBTs due to the loss of the electron current, the current stays almost at the same value for an extended period of time, before suddenly dropping to zero. In this paper, we show that this terrace arises because there is a value of LIGBT current during switch off where the rate of expansion of the depletion region with respect to the anode current is infinite. Once this level of anode current is approached, the depletion region starts to expand very rapidly, and is only stopped when it reaches the n-type buffer layer surrounding the anode. Once this happens, the current rapidly drops to zero. A quasi-static analytic model is derived to explain this behaviour. The analytically modelled turn off characteristic agrees well with that found by numerical simulation.
Resumo:
This paper presents a practical destruction-free parameter extraction methodology for a new physics-based circuit simulator buffer-layer Integrated Gate Commutated Thyristor (IGCT) model. Most key parameters needed for this model can be extracted by one simple clamped inductive-load switching experiment. To validate this extraction method, a clamped inductive load switching experiment was performed, and corresponding simulations were carried out by employing the IGCT model with parameters extracted through the presented methodology. Good agreement has been obtained between the experimental data and simulation results.
Resumo:
The simulation of complex chemical systems often requires a multi-level description, in which a region of special interest is treated using a computationally expensive quantum mechanical (QM) model while its environment is described by a faster, simpler molecular mechanical (MM) model. Furthermore, studying dynamic effects in solvated systems or bio-molecules requires a variable definition of the two regions, so that atoms or molecules can be dynamically re-assigned between the QM and MM descriptions during the course of the simulation. Such reassignments pose a problem for traditional QM/MM schemes by exacerbating the errors that stem from switching the model at the boundary. Here we show that stable, long adaptive simulations can be carried out using density functional theory with the BLYP exchange-correlation functional for the QM model and a flexible TIP3P force field for the MM model without requiring adjustments of either. Using a primary benchmark system of pure water, we investigate the convergence of the liquid structure with the size of the QM region, and demonstrate that by using a sufficiently large QM region (with radius 6 Å) it is possible to obtain radial and angular distributions that, in the QM region, match the results of fully quantum mechanical calculations with periodic boundary conditions, and, after a smooth transition, also agree with fully MM calculations in the MM region. The key ingredient is the accurate evaluation of forces in the QM subsystem which we achieve by including an extended buffer region in the QM calculations. We also show that our buffered-force QM/MM scheme is transferable by simulating the solvated Cl(-) ion.
Resumo:
Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large capacitor is wasted. Instead, the energy can be recovered using an on-chip DC-DC converter. This paper investigates the integration of two DC-DC converter topologies, boost and buck-boost, with a high-speed clock driver. The high operating frequency significantly shrinks the required size of the L and C components so they can be placed on-chip; typical converters place them off-chip. The clock driver and DC-DC converter are able to share the entire tapered buffer chain, including the widest drive transistors in the final stage. To achieve voltage regulation, the clock duty cycle must be modulated; implying only single-edge-triggered flops should be used. However, this minor drawback is eclipsed by the benefits: by recovering energy from the clock, the output power can actually exceed the additional power needed to operate the converter circuitry, resulting in an effective efficiency greater than 100%. Furthermore, the converter output can be used to operate additional power-saving features like low-voltage islands or body bias voltages. ©2008 IEEE.
Resumo:
Embedded propulsion systems, such as for example used in advanced hybrid-wing body aircraft, can potentially offer major fuel burn and noise reduction benefits but introduce challenges in the aerodynamic and acoustic integration of the high-bypass ratio fan system. A novel approach is proposed to quantify the effects of non-uniform flow on the generation and propagation of multiple pure tone noise (MPTs). The new method is validated on a conventional inlet geometry first. The ultimate goal is to conduct a parametric study of S-duct inlets in order to quantify the effects of inlet design parameters on the acoustic signature. The key challenge is that the mechanism underlying the distortion transfer, noise source generation and propagation through the non-uniform flow field are inherently coupled such that a simultaneous computation of the aerodynamics and acoustics is required. The technical approach is based on a body force description of the fan blade row that is able to capture the distortion transfer and the MPT noise generation mechanisms while greatly reducing computational cost. A single, 3-D full-wheel unsteady CFD simulation, in which the Euler equations are solved to second-order spatial and temporal accuracy, simultaneously computes the MPT noise generation and its propagation in distorted mean flow. Several numerical tools were developed to enable the implementation of this new approach. Parametric studies were conducted to determine appropriate grid and time step sizes for the propagation of acoustic waves. The Ffowcs-Williams and Hawkings integral method is used to propagate the noise to far field receivers. Non-reflecting boundary conditions are implemented through the use of acoustic buffer zones. The body force modeling approach is validated and proof-of-concept studies demonstrate the generation of disturbances at both blade-passing and shaft-order frequencies using the perturbed body force method. The full methodology is currently being validated using NASA's Source Diagnostic Test (SDT) fan and inlet geometry. Copyright © 2009 by Jeff Defoe, Alex Narkaj & Zoltan Spakovszky.
Resumo:
We report on the preparation conditions of YBa2Cu3O7 polycrystalline superconducting tapes by a sol-gel deposition technique. We present some discussion on the compatibility between the nature of the substrate, the use of a buffer layer, and the conditions used to prepare appropriate superconducting YBa2Cu3O7 materials. We report also on the microstructural characterizations performed in order to evaluate the crystallites size, degree of orientation and connectivity. © 2002 Elsevier Science B.V. All rights reserved.
Resumo:
Vertically oriented GaAs nanowires (NWs) are grown on Si(111) substrates using metal-organic chemical vapor deposition. Controlled epitaxial growth along the 111 direction is demonstrated following the deposition of thin GaAs buffer layers and the elimination of structural defects, such as twin defects and stacking faults, is found for high growth rates. By systematically manipulating the AsH 3 (group-V) and TMGa (group-III) precursor flow rates, it is found that the TMGa flow rate has the most significant effect on the nanowire quality. After capping the minimal tapering and twin-free GaAs NWs with an AlGaAs shell, long exciton lifetimes (over 700ps) are obtained for high TMGa flow rate samples. It is observed that the Ga adatom concentration significantly affects the growth of GaAs NWs, with a high concentration and rapid growth leading to desirable characteristics for optoelectronic nanowire device applications including improved morphology, crystal structure and optical performance. © 2012 IOP Publishing Ltd.
Resumo:
Taper-free and vertically oriented Ge nanowires were grown on Si (111) substrates by chemical vapor deposition with Au nanoparticle catalysts. To achieve vertical nanowire growth on the highly lattice mismatched Si substrate, a thin Ge buffer layer was first deposited, and to achieve taper-free nanowire growth, a two-temperature process was employed. The two-temperature process consisted of a brief initial base growth step at high temperature followed by prolonged growth at lower temperature. Taper-free and defect-free Ge nanowires grew successfully even at 270 °C, which is 90 °C lower than the bulk eutectic temperature. The yield of vertical and taper-free nanowires is over 90%, comparable to that of vertical but tapered nanowires grown by the conventional one-temperature process. This method is of practical importance and can be reliably used to develop novel nanowire-based devices on relatively cheap Si substrates. Additionally, we observed that the activation energy of Ge nanowire growth by the two-temperature process is dependent on Au nanoparticle size. The low activation energy (∼5 kcal/mol) for 30 and 50 nm diameter Au nanoparticles suggests that the decomposition of gaseous species on the catalytic Au surface is a rate-limiting step. A higher activation energy (∼14 kcal/mol) was determined for 100 nm diameter Au nanoparticles which suggests that larger Au nanoparticles are partially solidified and that growth kinetics become the rate-limiting step. © 2011 American Chemical Society.
Resumo:
We report straight and vertically aligned defect-free GaAs nanowires grown on Si(111) substrates by metal-organic chemical vapor deposition. By deposition of thin GaAs buffer layers on Si substrates, these nanowires could be grown on the buffer layers with much less stringent conditions as otherwise imposed by epitaxy of III-V compounds on Si. Also, crystal-defect-free GaAs nanowires were grown by using either a two-temperature growth mode consisting of a short initial nucleation step under higher temperature followed by subsequent growth under lower temperature or a rapid growth rate mode with high source flow rate. These two growth modes not only eliminated planar crystallographic defects but also significantly reduced tapering. Core-shell GaAs-AlGaAs nanowires grown by the two-temperature growth mode showed improved optical properties with strong photoluminescence and long carrier life times. © 2011 American Chemical Society.
Resumo:
GaAs nanowires were grown on Si (111) substrates. By coating a thin GaAs buffer layer on Si surface and using a two-temperature growth, the morphology and crystal structure of GaAs nanowires were dramatically improved. The strained GaAs/GaP core-shell nanowires, based on the improved GaAs nanowires with a shell thickness of 25 nm, showed a significant shift in emission energy of 260 meV from the unstrained GaAs nanowires. © 2010 IEEE.
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Straight, vertically aligned GaAs nanowires were grown on Si(111) substrates coated with thin GaAs buffer layers. We find that the V/III precursor ratio and growth temperature are crucial factors influencing the morphology and quality of buffer layers. A double layer structure, consisting of a thin initial layer grown at low V/III ratio and low temperature followed by a layer grown at high V/III ratio and high temperature, is crucial for achieving straight, vertically aligned GaAs nanowires on Si(111) substrates. An in situ annealing step at high temperature after buffer layer growth improves the surface and structural properties of the buffer layer, which further improves the morphology of the GaAs nanowire growth. Through such optimizations we show that vertically aligned GaAs nanowires can be fabricated on Si(111) substrates and achieve the same structural and optical properties as GaAs nanowires grown directly on GaAs(111)B substrates.
Resumo:
We investigate vertical and defect-free growth of GaAs nanowires on Si (111) substrates via a vapor-liquid-solid (VLS) growth mechanism with Au catalysts by metal-organic chemical vapor deposition (MOCVD). By using annealed thin GaAs buffer layers on the surface of Si substrates, most nanowires are grown on the substrates straight, following (111) direction; by using two temperature growth, the nanowires were grown free from structural defects, such as twin defects and stacking faults. Systematic experiments about buffer layers indicate that V/III ratio of precursor and growth temperature can affect the morphology and quality of the buffer layers. Especially, heterostructural buffer layers grown with different V/III ratios and temperatures and in-situ post-annealing step are very helpful to grow well arranged, vertical GaAs nanowires on Si substrates. The initial nanowires having some structural defects can be defect-free by two-temperature growth mode with improved optical property, which shows us positive possibility for optoelectronic device application. ©2010 IEEE.
Resumo:
A critical element for the successful growth of GaN device layers on Si is accurate control of the AlGaN buffer layers used to manage strain. Here we present a method for measuring the composition of the AlGaN buffer layers in device structures which makes use of a one-dimensional x-ray detector to provide efficient measurement of a reciprocal space map which covers the full compositional range from AlN to GaN. Combining this with a suitable x-ray reflection with low strain sensitivity it is possible to accurately determine the Al fraction of the buffer layers independent of their relaxation state. © 2013 IOP Publishing Ltd.
Resumo:
The response of back-supported buffer plates comprising a solid face sheet and foam core backing impacted by a column of high velocity particles (sand slug) is investigated via a lumped parameter model and coupled discrete/continuum simulations. The buffer plate is either resting on (unattached) or attached to a rigid stationary foundation. The lumped parameter model is used to construct maps of the regimes of behaviour with axes of the ratio of the height of the sand slug to core thickness and the normalised core strength. Four regimes of behaviour are identified based on whether the core compression ends prior to the densification of the sand slug or vice versa. Coupled discrete/continuum simulations are also reported and compared with the lumped parameter model. While the model predicted regimes of behaviour are in excellent agreement with numerical simulations, the lumped parameter model is unable to predict the momentum transmitted to the supports as it neglects the role of elasticity in both the buffer plate and the sand slug. The numerical calculations show that the momentum transfer is minimised for intermediate values of the core strength when the so-called "soft-catch" mechanism is in play. In this regime the bounce-back of the sand slug is minimised which reduces the momentum transfer. However, in this regime, the impulse reduction is small (less than 10% of that transferred to a rigid structure). For high values of the core strength, the response of the buffer plate resembles a rigid plate with nearly no impulse mitigation while at low values of core strength, a slap event occurs when the face sheet impinges against the foundation due to full densification of the foam core. This slap event results in a significant enhancement of the momentum transfer to the foundation. The results demonstrate that appropriately designed buffer plates have potential as impulse mitigators in landmine loading situations. © 2013 Elsevier Ltd. All rights reserved.
Resumo:
A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ∼16.5 V, a high drain current on/off ratio of ∼105, a gate leakage current below ∼300 pA, and excellent retention characteristics for over 104 s. © 2014 AIP Publishing LLC.