Taper-free and vertically oriented Ge nanowires on Ge/Si substrates grown by a two-temperature process

Taper-free and vertically oriented Ge nanowires were grown on Si (111) substrates by chemical vapor deposition with Au nanoparticle catalysts. To achieve vertical nanowire growth on the highly lattice mismatched Si substrate, a thin Ge buffer layer was first deposited, and to achieve taper-free nanowire growth, a two-temperature process was employed. The two-temperature process consisted of a brief initial base growth step at high temperature followed by prolonged growth at lower temperature. Taper-free and defect-free Ge nanowires grew successfully even at 270 °C, which is 90 °C lower than the bulk eutectic temperature. The yield of vertical and taper-free nanowires is over 90%, comparable to that of vertical but tapered nanowires grown by the conventional one-temperature process. This method is of practical importance and can be reliably used to develop novel nanowire-based devices on relatively cheap Si substrates. Additionally, we observed that the activation energy of Ge nanowire growth by the two-temperature process is dependent on Au nanoparticle size. The low activation energy (∼5 kcal/mol) for 30 and 50 nm diameter Au nanoparticles suggests that the decomposition of gaseous species on the catalytic Au surface is a rate-limiting step. A higher activation energy (∼14 kcal/mol) was determined for 100 nm diameter Au nanoparticles which suggests that larger Au nanoparticles are partially solidified and that growth kinetics become the rate-limiting step. © 2011 American Chemical Society.

Vertically oriented epitaxial germanium nanowires on silicon substrates using thin germanium buffer layers.

We demonstrate a method to realize vertically oriented Ge nanowires on Si(111) substrates. Ge nanowires were grown by chemical vapor deposition using Au nanoparticles to seed nanowire growth via a vapor-liquid-solid growth mechanism. Rapid oxidation of Si during Au nanoparticle application inhibits the growth of vertically oriented Ge nanowires directly on Si. The present method employs thin Ge buffer layers grown at low temperature less than 600 degrees C to circumvent the oxidation problem. By using a thin Ge buffer layer with root-mean-square roughness of approximately 2 nm, the yield of vertically oriented Ge nanowires is as high as 96.3%. This yield is comparable to that of homoepitaxial Ge nanowires. Furthermore, branched Ge nanowires could be successfully grown on these vertically oriented Ge nanowires by a secondary seeding technique. Since the buffer layers are grown under moderate conditions without any high temperature processing steps, this method has a wide process window highly suitable for Si-based microelectronics.

Vertically standing Ge nanowires on GaAs(110) substrates.

The growth of epitaxial Ge nanowires is investigated on (100), (111) B and (110) GaAs substrates in the growth temperature range from 300 to 380 °C. Unlike epitaxial Ge nanowires on Ge or Si substrates, Ge nanowires on GaAs substrates grow predominantly along the [Formula: see text] direction. Using this unique property, vertical [Formula: see text] Ge nanowires epitaxially grown on GaAs(110) surface are realized. In addition, these Ge nanowires exhibit minimal tapering and uniform diameters, regardless of growth temperatures, which is an advantageous property for device applications. Ge nanowires growing along the [Formula: see text] directions are particularly attractive candidates for forming nanobridge devices on conventional (100) surfaces.

Improved switching uniformity and low-voltage operation in TaO x-based RRAM using Ge reactive layer

Significant improvements in the spatial and temporal uniformities of device switching parameters are successfully demonstrated in Ge/TaOx bilayer-based resistive switching devices, as compared with non-Ge devices. In addition, the reported Ge/TaOx devices also show significant reductions in the operation voltages. Influence of the Ge layer on the resistive switching of TaOx-based resistive random access memory is investigated by X-ray spectroscopy and the theory of Gibbs free energy. Higher uniformity is attributed to the confinement of the filamentary switching process. The presence of a larger number of interface traps, which will create a beneficial electric field to facilitate the drift of oxygen vacancies, is believed to be responsible for the lower operation voltages in the Ge/TaO x devices. © 1980-2012 IEEE.