262 resultados para gate resistance


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Copyright © 2014 John Wiley & Sons, Ltd. Copyright © 2014 John Wiley & Sons, Ltd. Summary A field programmable gate array (FPGA) based model predictive controller for two phases of spacecraft rendezvous is presented. Linear time-varying prediction models are used to accommodate elliptical orbits, and a variable prediction horizon is used to facilitate finite time completion of the longer range manoeuvres, whilst a fixed and receding prediction horizon is used for fine-grained tracking at close range. The resulting constrained optimisation problems are solved using a primal-dual interior point algorithm. The majority of the computational demand is in solving a system of simultaneous linear equations at each iteration of this algorithm. To accelerate these operations, a custom circuit is implemented, using a combination of Mathworks HDL Coder and Xilinx System Generator for DSP, and used as a peripheral to a MicroBlaze soft-core processor on the FPGA, on which the remainder of the system is implemented. Certain logic that can be hard-coded for fixed sized problems is implemented to be configurable online, in order to accommodate the varying problem sizes associated with the variable prediction horizon. The system is demonstrated in closed-loop by linking the FPGA with a simulation of the spacecraft dynamics running in Simulink on a PC, using Ethernet. Timing comparisons indicate that the custom implementation is substantially faster than pure embedded software-based interior point methods running on the same MicroBlaze and could be competitive with a pure custom hardware implementation.

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Aligned carbon nanotube (CNT) polymer composites are envisioned as the next-generation composite materials for a wide range of applications. In this work, we investigate the erosive wear behavior of epoxy matrix composites reinforced with both randomly dispersed and aligned carbon nanotube (CNT) arrays. The aligned CNT composites are prepared in two different configurations, where the sidewalls and ends of nanotubes are exposed to the composite surface. Results have shown that the composite with vertically aligned CNT-arrays exhibits superior erosive wear resistance compared to any of the other types of composites, and the erosion rate reaches a similar performance level to that of carbon steel at 20° impingement angle. The erosive wear mechanism of this type of composite, at various impingement angles, is studied by Scanning Electron Microscopy (SEM). We report that the erosive wear performance shows strong dependence on the alignment geometries of CNTs within the epoxy matrix under identical nanotube loading fractions. Correlations between the eroded surface roughness and the erosion rates of the CNT composites are studied by surface profilometry. This work demonstrates methods to fabricate CNT based polymer composites with high loading fractions of the filler, alignment control of nanotubes and optimized erosive wear properties. © 2014 Elsevier Ltd. All rights reserved.

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It has been previously observed that thin film transistors (TFTs) utilizing an amorphous indium gallium zinc oxide (a-IGZO) semiconducting channel suffer from a threshold voltage shift when subjected to a negative gate bias and light illumination simultaneously. In this work, a thermalization energy analysis has been applied to previously published data on negative bias under illumination stress (NBIS) in a-IGZO TFTs. A barrier to defect conversion of 0.65-0.75 eV is extracted, which is consistent with reported energies of oxygen vacancy migration. The attempt-to-escape frequency is extracted to be 10 6-107 s-1, which suggests a weak localization of carriers in band tail states over a 20-40 nm distance. Models for the NBIS mechanism based on charge trapping are reviewed and a defect pool model is proposed in which two distinct distributions of defect states exist in the a-IGZO band gap: these are associated with states that are formed as neutrally charged and 2+ charged oxygen vacancies at the time of film formation. In this model, threshold voltage shift is not due to a defect creation process, but to a change in the energy distribution of states in the band gap upon defect migration as this allows a state formed as a neutrally charged vacancy to be converted into one formed as a 2+ charged vacancy and vice versa. Carrier localization close to the defect migration site is necessary for the conversion process to take place, and such defect migration sites are associated with conduction and valence band tail states. Under negative gate bias stressing, the conduction band tail is depleted of carriers, but the bias is insufficient to accumulate holes in the valence band tail states, and so no threshold voltage shift results. It is only under illumination that the quasi Fermi level for holes is sufficiently lowered to allow occupation of valence band tail states. The resulting charge localization then allows a negative threshold voltage shift, but only under conditions of simultaneous negative gate bias and illumination, as observed experimentally as the NBIS effect. © 2014 AIP Publishing LLC.

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The spallation resistance of an air plasma sprayed (APS) thermal barrier coating (TBC) to cool-down/reheat is evaluated for a pre-existing delamination crack. The delamination emanates from a vertical crack through the coating and resides at the interface between coating and underlying thermally grown oxide layer (TGO). The coating progressively sinters during engine operation, and this leads to a depth-dependent increase in modulus. Following high temperature exposure, the coating is subjected to a cooling/reheating cycle representative of engine shut-down and start-up. The interfacial stress intensity factors are calculated for the delamination crack over this thermal cycle and are compared with the mode-dependent fracture toughness of the interface between sintered APS and TGO. The study reveals the role played by microstructural evolution during sintering in dictating the spallation life of the thermal barrier coating, and also describes a test method for the measurement of delamination toughness of a thin coating. © 2014 Elsevier Ltd.

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The model of interconnected numerical device segments can give a prediction on the dynamic performance of large area full wafer devices such as the Gate Commutated Thyristors (GCTs) and can be used as an optimisation tool for designing GCTs. In this study the authors evaluate the relative importance of the shallow p-base thickness, its peak concentration, the depth of the p-base and the buffer peak concentration. © The Institution of Engineering and Technology 2014.