Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

Application of electron beams in thermal processing of semiconductor materials and devices

Rapid and effective thermal processing methods using electron beams are described in this paper. Heating times ranging from a fraction of a second to several seconds and temperatures up to 1400°C are attainable. Applications such as the annealing of ion implanted material, both without significant dopant diffusion and with highly controlled diffusion of impurities, are described. The technique has been used successfully to activate source/drain regions for fine geometry NMOS transistors. It is shown that electron beams can produce localised heating of semiconductor substrates and a resolution of approximately 1 μm has been achieved. Electron beam heating has been applied to improving the crystalline quality of silicon-on sapphire used in CMOS device fabrication. Silicon layers with defect levels approaching bulk material have been obtained. Finally, the combination of isothermal and selective annealing is shown to have application in recrystallisation of polysilicon films on an insulating layer. The approach provides the opportunity of producing a silicon-on-insulator substrate with improved crystalline quality compared to silicon-on-sapphire at a potentially lower cost. It is suggested that rapid heating methods are expected to provide a real alternative to conventional furnace processing of semiconductor devices in the development of fabrication technology. © 1984 Benn electronics Publications Ltd, Luton.

Performance of CMOS Devices in Silicon-on-Sapphire Films After Solid-Phase Epitaxial Growth With Rapid Electron-Beam Heating

The crystal quality of 0.3-μm-thick as-grown epitaxial silicon-on-sapphire (SOS) was improved using solid-phase epitaxy (SPE) by implantation with silicon to 1015 ions/cm2 at 175 keV and rapid annealing using electron-beam heating, n-channel and p-channel transistormobilities increased by 31 and 19 percent, respectively, and a reduction in ring-oscillator stage delay confirmed that crystal defects near the upper silicon surface had been removed. Leakage in n-channel transistors was not significantly affected by the regrowth process but for p-channel transistors back-channel leakage was considerably greater than for the control devices. This is attributed to aluminum released by damage to the sapphire during silicon implantation. © 1985 IEEE

HYDROGENATED AMORPHOUS SILICON THIN-FILM DEPOSITION BY DIRECT PHOTO-ENHANCED DECOMPOSITION OF SILANE USING AN INTERNAL HYDROGEN DISCHARGE LAMP.

Hydrogenated amorphous silicon (a-Si:H) thin films have been deposited from silane using a novel photo-enhanced decomposition technique. The system comprises a hydrogen discharge lamp contained within the reaction vessel; this unified approach allows high energy photon excitation of the silane molecules without absorption by window materials or the need for mercury sensitisation. The film growth rates (exceeding 4 Angstrom/s) and material properties obtained are comparable to those of films produced by plasma-enhanced CVD techniques. The reduction of energetic charged particles in the film growth region should enable the fabrication of cleaner semiconductor/insulator interfaces in thin-film transistors.

Unified circuit model for the polysilicon TFT

This paper proposes two methods to improve the modelling of thin film transistors (TFTs). The first involves integrating Poissons equation numerically, given a density of trap states and other relevant material parameters including a constant mobility. Theresult is conductance as a numerical function of gate voltage. The second method recognizes that the data for areal conductance found by numerical integration, may easily be found by measurement without making assumptions about the density of trap states.

Influence of lattice temperature on SOI MOSFET's output characteristics

An explanation for the observed variations in the output behaviour of SOI transistors with different buried oxide thicknesses is presented. At low drain bias, the temperature effects are relatively insignificant while at high drain bias, the temperature effects dominate the nonlinear behaviour of the output characteristics.

Analytical model for the 3D-RESURF effect

This paper presents an analytical model for the determination of the basic breakdown properties of three-dimensional (3D)-RESURF/CoolMOS/super junction type structures. To account for the two-dimensional (2D) effect of the 3D-RESURF action, 2D models of the electric field distribution are developed. Based on these, expressions are derived for the breakdown voltage as a function of doping concentration and physical dimensions. In addition to cases where the drift regions are fully depleted, the model developed is also applicable to situations involving drift regions which are almost depleted. Accuracy of the analytical approach is verified by comparison with numerical results obtained from the MEDICI device simulator.

The use of C-V techniques to investigate instability mechanisms in M-I-S structures

In the field of flat panel displays, the current leading technology is the Active Matrix liquid Crystal Display; this uses a-Si:H based thin film transistors (TFTs) as the switching element in each pixel. However, under gate bias a-Si:H TFTs suffer from instability, as is evidenced by a shift in the gate threshold voltage. The shift in the gate threshold voltage is generally measured from the gate transfer characteristics, after subjecting the TFT to prolonged gate bias. However, a major drawback of this measurement method is that it cannot distinguish whether the shift is caused by the change in the midgap states in the a-Si:H channel or by charge trapping in the gate insulator. In view of this, we have developed a capacitance-voltage (C-V) method to measure the shift in threshold voltage. We employ Metal-Insulator-Semiconductor (MIS) structures to investigate the threshold voltage shift as they are simpler to fabricate than TFTs. We have investigated a large of number Metal/a-Si:H/Si3N4/Si+n structures using our C-V technique. From, the C-V data for the MIS structures, we have found that the relationship between the thermal energy and threshold voltage shift is similar to that reported by Wehrspohn et. al in a-Si:H TFTs (J Appl. Phys, 144, 87, 2000). The a-Si:H and Si3N4 layers were grown using the radio-frequency plasma-enhanced chemical vapour deposition technique.

Short-channel polymer field-effect-transistor fabrication using spin-coating-induced edge template and ink-jet printing

A method to fabricate polymer field-effect transistors with submicron channel lengths is described. A thin polymer film is spin coated on a prepatterned resist with a low resolution to create a thickness contrast in the overcoated polymer layer. After plasma and solvent etching, a submicron-sized line structure, which templates the contour of the prepattern, is obtained. A further lift-off process is applied to define source-drain electrodes of transistors. With a combination of ink-jet printing, transistors with channel length down to 400 nm have been fabricated by this method. We show that drive current density increases as expected, while the on/off current ratio 106 is achieved. © 2005 American Institute of Physics.

Millisecond processing beyond chip technology: From electronics to photonics

There is a clear and increasing interest in short time annealing processing far below one second, i.e. the lower limit of Rapid Thermal Processing (RTP) called spike annealing. This was driven by the need of suppressing the so-called Transient Enhanced Diffusion in advanced boronimplanted shallow pn-junctions in silicon technology. Meanwhile the interest in flash lamp annealing (FLA) in the millisecond range spread out into other fields related to silicon technology and beyond. This paper reports on recent experiments regarding shallow junction engineering in germanium, annealing of ITO layers on glass and plastic foil to form an conductive layer as well as investigations which we did during the last years in the field of wide band gap semiconductor materials (SiC, ZnO). A more common feature evolving from our work was related to the modeling of wafer stress during millisecond thermal processing with flash lamps. Finally recent achievements in the field of silicon-based light emission basing on Metal-Oxide-Semiconductor Light Emitting Devices will be reported. © 2007 IEEE.

Advanced thermal processing of semiconductor materials in the msec-range

This paper reviews the advances that flash lamp annealing brings to the processing of the most frequently used semiconductor materials, namely silicon and silicon carbide, thus enabling the fabrication of novel microelectronic structures and materials. The paper describes how such developments can translate into important practical applications leading to a wide range of technological benefits. Opportunities in ultra-shallow junction formation, heteroepitaxial growth of thin films of cubic silicon carbide on silicon, and crystallization of amorphous silicon films, along with the technical reasons for using flash lamp annealing are discussed in the context of state-of-the-art materials processing. © 2005 IEEE.