1-3 Piezocomposite design optimised for high frequency kerfless transducer arrays

Piezocomposites that can operate at frequencies above 30 MHz without spurious modes are required in order to develop sufficiently sensitive high frequency arrays for high resolution imaging. However, scaling down of conventional piezocomposite fabrication techniques becomes increasingly difficult as dimensions decrease with increasing frequency. The approach presented here is to use micro-moulded 1-3 piezocomposites and a distribution of piezoelectric segment size and separation. Innovative approaches to composite pattern design, based on a randomized spatial distribution, are presented. Micro-moulding techniques are shown to be suitable for fabricating composites with dimensions required for high frequency composites. Randomized piezocomposite patterns are modeled and are shown to suppress spurious modes.

Operation of a high frequency piezoelectric ultrasound array with an application specific integrated circuit

Integration of a piezoelectric high frequency ultrasound (HFUS) array with a microfabricated application specific integrated circuit (ASIC) performing a range of functions has several advantages for ultrasound imaging. The number of signal cables between the array/electronics and the data acquisition / imaging system can be reduced, cutting costs and increasing functionality. Electrical impedance matching is also simplified and the same approach can reduce overall system dimensions for applications such as endoscopic ultrasound. The work reported in this paper demonstrates early ASIC operation with a piezocomposite HFUS array operating at approximately 30 MHz. The array was tested in three different modes. Clear signals were seen in catch-mode, with an external transducer as a source of ultrasound, and in pitch-mode with the external transducer as a receiver. Pitch-catch mode was also tested successfully, using sequential excitation on three array elements, and viable signals were detected. However, these were relatively small and affected by interference from mixed-signal sources in the ASIC. Nevertheless, the functionality and compatibility of the two main components of an integrated HFUS - ASIC device have been demonstrated and the means of further optimization are evident.

Energy recovery from high-frequency clocks using DC-DC converters

Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large capacitor is wasted. Instead, the energy can be recovered using an on-chip DC-DC converter. This paper investigates the integration of two DC-DC converter topologies, boost and buck-boost, with a high-speed clock driver. The high operating frequency significantly shrinks the required size of the L and C components so they can be placed on-chip; typical converters place them off-chip. The clock driver and DC-DC converter are able to share the entire tapered buffer chain, including the widest drive transistors in the final stage. To achieve voltage regulation, the clock duty cycle must be modulated; implying only single-edge-triggered flops should be used. However, this minor drawback is eclipsed by the benefits: by recovering energy from the clock, the output power can actually exceed the additional power needed to operate the converter circuitry, resulting in an effective efficiency greater than 100%. Furthermore, the converter output can be used to operate additional power-saving features like low-voltage islands or body bias voltages. ©2008 IEEE.

Influence of voltage and frequency dimming on power losses in hf electronic ballasts for compact fluorescent lamps

Compact fluorescent lamps (CFLs) incorporating electronic ballasts are widely used in lighting. In many cases, the ability to dim the lamp is a requirement. Dimming can be achieved by varying the switching frequency of the inverter or by changing the voltage supplied to the inverter. The effect of dimming by both approaches on the power losses in the inverter is studied in this work. The lamp and associated inverter has been modeled in Pspice, using a behavioral model for the CFL. Predicted losses are in good agreement with experimental data obtained from calorimetry. After verification, the model was then used to determine the distribution of losses within the inverter, enabling a comparison of the effects of the two dimming methods to be made. © 2011 IEEE.