Destruction-free parameter extraction for a physics-based circuit simulator IGCT model

This paper presents a practical destruction-free parameter extraction methodology for a new physics-based circuit simulator buffer-layer Integrated Gate Commutated Thyristor (IGCT) model. Most key parameters needed for this model can be extracted by one simple clamped inductive-load switching experiment. To validate this extraction method, a clamped inductive load switching experiment was performed, and corresponding simulations were carried out by employing the IGCT model with parameters extracted through the presented methodology. Good agreement has been obtained between the experimental data and simulation results.

Characterization of defect removal in hydrogenated and deuterated amorphous silicon thin film transistors

Thin film transistors (TFTs) utilizing an hydrogenated amorphous silicon (a-Si:H) channel layer exhibit a shift in the threshold voltage with time under the application of a gate bias voltage due to the creation of metastable defects. These defects are removed by annealing the device with zero gate bias applied. The defect removal process can be characterized by a thermalization energy which is, in turn, dependent upon an attempt-to-escape frequency for defect removal. The threshold voltage of both hydrogenated and deuterated amorphous silicon (a-Si:D) TFTs has been measured as a function of annealing time and temperature. Using a molecular dynamics simulation of hydrogen and deuterium in a silicon network in the H2 * configuration, it is shown that the experimental results are consistent with an attempt-to-escape frequency of (4.4 ± 0.3) × 1013 Hz and (5.7 ± 0.3) × 1013 Hz for a-Si:H and a-Si:D respectively which is attributed to the oscillation of the Si-H and Si-D bonds. Using this approach, it becomes possible to describe defect removal in hydrogenated and deuterated material by the thermalization energies of (1.552 ± 0.003) eV and (1.559 ± 0.003) eV respectively. This correlates with the energy per atom of the Si-H and Si-D bonds. © 2006 Elsevier B.V. All rights reserved.

Switching aspects of hybrid semiconductor power devices

A hybrid semiconductor power device has been designed which combines IGBT switching and thyristor on-state characteristics. A single gate signal controls the switching and triggers the transitions between an IGBT and a thyristor mode of operation. This paper discusses aspects of the switching behaviour of this and of similar devices. Simulation results of an example structure are presented and conceivable developments in the switching characteristics of hybrid devices are discussed.

Single-gated multiple-mode power semiconductor devices

A new method has been used to design a power semiconductor device which combines IGBT switching and thyristor on-state characteristics. A single gate signal controls the switching and triggers the transitions between the IGBT and thyristor modes of operation. This paper discusses single-gated devices with multiple modes and aspects of their switching behaviour.

Switching aspects of hybrid semiconductor power devices

A hybrid semiconductor power device has been designed which combines IGBT switching and thyristor on-state characteristics. A single gate signal controls the switching and triggers the transitions between an IGBT and a thyristor mode of operation. This paper discusses aspects of the switching behaviour of this and of similar devices. Simulation results of an example structure are presented and conceivable developments in the switching characteristics of hybrid devices are discussed.

Spice modelling of the superjunction IGBT

This paper presents a SPICE model of the SuperJunction Insulated Gate Bipolar Transistor (SJIGBT) [1]. SPICE simulation results are in good agreement with the DESSIS simulation results under DC conditions. This model consists of an intrinsic MOSFET and a parallel combination of a wide and a narrow base pnp BJTs. A parasitic JFET is also included to account for the restricted current flow between two adjacent p-wells. In addition the JFET component also models the additional depletion region caused by the transverse junction at the upper side of the n-drift region where the current is mainly transported via majority carriers.

Active Voltage Control on series connection of IGBTs and diode recovery optimization

In this paper an Active Voltage Control (AVC) technique is presented, for series connection of insulated-gate-bipolar-transistors (IGBT) and control of diode recovery. The AVC technique can control the switching trajectory of an IGBT according to a pre-set reference signal. In series connections, every series connected IGBT follows the reference and so that the dynamic voltage sharing is achieved. Another key advantage for AVC is that by changing the reference signal at turn-on, the diode recovery can be optimised. © 2010 IEEE.

Self-aligned high-resolution printed polymer transistors

A process to fabricate solution-processable thin-film transistors (TFTs) with a one-step self-aligned definition of the dimensions in all functional layers is demonstrated. The TFT-channel, semiconductor materials, and effective gate dimention of different layers are determined by a one-step imprint process and the subsequent pattern transfer without the need for multiple patterning and mask alignment. The process is compatible with fabrication of large-scale circuits. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High mobility N-channel and P-channel nanocrystalline silicon thin-film transistors

We report high hole and electron mobilities in nanocrystalline silicon (nc-Si:H) top-gate staggered thin-film transistors (TFTs) fabricated by direct plasma-enhanced chemical vapor deposition (PECVD) at 260°C. The n-channel nc-Si:H TFT with n+ nc-Si:H ohmic contacts shows a field-effect electron mobility (μnFE) of 130 cm2/Vs, which increases to 150 cm2/Vs with Cr-silicide contacts, along with a field-effect hole mobility (μhFE) of 25 cm2/Vs. To the best of our knowledge, the hole and electron mobilities reported here are the highest achieved to date using direct PECVD. © 2005 IEEE.

Investigation into IGBT dV/dt during turn-off and its temperature dependence

In many power converter applications, particularly those with high variable loads, such as traction and wind power, condition monitoring of the power semiconductor devices in the converter is considered desirable. Monitoring the device junction temperature in such converters is an essential part of this process. In this paper, a method for measuring the insulated gate bipolar transistor (IGBT) junction temperature using the collector voltage dV/dt at turn-OFF is outlined. A theoretical closed-form expression for the dV/dt at turn-OFF is derived, closely agreeing with experimental measurements. The role of dV/dt in dynamic avalanche in high-voltage IGBTs is also discussed. Finally, the implications of the temperature dependence of the dV/dt are discussed, including implementation of such a temperature measurement technique. © 2006 IEEE.

How much do we spend to save? Calculating the embodied carbon costs of retrofit

The drive to reduce carbon emissions from domestic housing has led to a recent shift of focus from new-­‐build to retrofit. However there are two significant differences. Firstly more work is needed to retrofit existing housing to the same energy efficiency standards as new-­‐build. Secondly the remaining length of service life is potentially shorter. This implies that the capital expenditure – both financial and carbon -­‐ of retrofit may be disproportionate to the savings gained over the remaining life. However the Government’s definition of low and zero carbon continues to exclude the capital (embodied) carbon costs of construction, which has resulted in a lack of data for comparison. The paper addresses this gap by reporting the embodied carbon costs of retrofitting four individual pilot properties in Rampton Drift, part of an Eco-­‐Town Demonstrator Project in Cambridgeshire. Through collecting details of the materials used and their journeys from manufacturer to site, the paper conducts a ‘cradle-­‐to-­‐gate’ life cycle carbon assessment for each property. The embodied carbon figures are calculated using a software tool being developed by the Centre for Sustainable Development at the University of Cambridge. The key aims are to assess the real embodied carbon costs of retrofit of domestic properties, and to test the new tool; it is hoped that the methodology, the tool and the specific findings will be transferable to other projects. Initial changes in operational energy as a result of the retrofit works will be reported and compared with the embodied carbon costs when presenting this paper.

A Comparative Review of Existing Data and Methodologies for Calculating Embodied Energy and Carbon of Buildings

In the Climate Change Act of 2008 the UK Government pledged to reduce carbon emissions by 80% by 2050. As one step towards this, regulations are being introduced requiring all new buildings to be ‘zero carbon’ by 2019. These are defined as buildings which emit net zero carbon during their operational lifetime. However, in order to meet the 80% target it is necessary to reduce the carbon emitted during the whole life-cycle of buildings, including that emitted during the processes of construction. These elements make up the ‘embodied carbon’ of the building. While there are no regulations yet in place to restrict embodied carbon, a number of different approaches have been made. There are several existing databases of embodied carbon and embodied energy. Most provide data for the material extraction and manufacturing only, the ‘cradle to factory gate’ phase. In addition to the databases, various software tools have been developed to calculate embodied energy and carbon of individual buildings. A third source of data comes from the research literature, in which individual life cycle analyses of buildings are reported. This paper provides a comprehensive review, comparing and assessing data sources, boundaries and methodologies. The paper concludes that the wide variations in these aspects produce incomparable results. It highlights the areas where existing data is reliable, and where new data and more precise methods are needed. This comprehensive review will guide the future development of a consistent and transparent database and software tool to calculate the embodied energy and carbon of buildings.

Air stable complementary polymer circuits fabricated in ambient condition by inkjet printing

Air stable complementary polymer inverters were demonstrated by inkjet printing of both top-gate electrodes and the semiconductors in ambient conditions. The p-type and n-type polymer semiconductors were also thermally annealed in ambient conditions after printing. The good performance of circuits in ambient condition shows that the transistors are not only air-stable in term of ambient humidity and oxygen, but also inert to ion migration through dielectrics from the printed gate. The result obtained here has further confirmed the feasibility of fabrication of low-cost polymer complementary circuits in a practical environment. © 2011 Elsevier B.V. All rights reserved.

Electrical actuation and readout in a nanoelectromechanical resonator based on a laterally suspended zinc oxide nanowire.

In this paper, we present experimental results describing enhanced readout of the vibratory response of a doubly clamped zinc oxide (ZnO) nanowire employing a purely electrical actuation and detection scheme. The measured response suggests that the piezoelectric and semiconducting properties of ZnO effectively enhance the motional current for electromechanical transduction. For a doubly clamped ZnO nanowire resonator with radius ~10 nm and length ~1.91 µm, a resonant frequency around 21.4 MHz is observed with a quality factor (Q) of ~358 in vacuum. A comparison with the Q obtained in air (~242) shows that these nano-scale devices may be operated in fluid as viscous damping is less significant at these length scales. Additionally, the suspended nanowire bridges show field effect transistor (FET) characteristics when the underlying silicon substrate is used as a gate electrode or using a lithographically patterned in-plane gate electrode. Moreover, the Young's modulus of ZnO nanowires is extracted from a static bending test performed on a nanowire cantilever using an AFM and the value is compared to that obtained from resonant frequency measurements of electrically addressed clamped–clamped beam nanowire resonators.

Embedded Model Predictive Control (MPC) using a FPGA

Model Predictive Control (MPC) is increasingly being proposed for application to miniaturized devices, fast and/or embedded systems. A major obstacle to this is its computation time requirement. Continuing our previous studies of implementing constrained MPC on Field Programmable Gate Arrays (FPGA), this paper begins to exploit the possibilities of parallel computation, with the aim of speeding up the MPC implementation. Simulation studies on a realistic example show that it is possible to implement constrained MPC on an FPGA chip with a 25MHz clock and achieve MPC implementation rates comparable to those achievable on a Pentium 3.0 GHz PC. Copyright © 2007 International Federation of Automatic Control All Rights Reserved.