A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under simultaneous negative gate bias and illumination

It has been previously observed that thin film transistors (TFTs) utilizing an amorphous indium gallium zinc oxide (a-IGZO) semiconducting channel suffer from a threshold voltage shift when subjected to a negative gate bias and light illumination simultaneously. In this work, a thermalization energy analysis has been applied to previously published data on negative bias under illumination stress (NBIS) in a-IGZO TFTs. A barrier to defect conversion of 0.65-0.75 eV is extracted, which is consistent with reported energies of oxygen vacancy migration. The attempt-to-escape frequency is extracted to be 10 6-107 s-1, which suggests a weak localization of carriers in band tail states over a 20-40 nm distance. Models for the NBIS mechanism based on charge trapping are reviewed and a defect pool model is proposed in which two distinct distributions of defect states exist in the a-IGZO band gap: these are associated with states that are formed as neutrally charged and 2+ charged oxygen vacancies at the time of film formation. In this model, threshold voltage shift is not due to a defect creation process, but to a change in the energy distribution of states in the band gap upon defect migration as this allows a state formed as a neutrally charged vacancy to be converted into one formed as a 2+ charged vacancy and vice versa. Carrier localization close to the defect migration site is necessary for the conversion process to take place, and such defect migration sites are associated with conduction and valence band tail states. Under negative gate bias stressing, the conduction band tail is depleted of carriers, but the bias is insufficient to accumulate holes in the valence band tail states, and so no threshold voltage shift results. It is only under illumination that the quasi Fermi level for holes is sufficiently lowered to allow occupation of valence band tail states. The resulting charge localization then allows a negative threshold voltage shift, but only under conditions of simultaneous negative gate bias and illumination, as observed experimentally as the NBIS effect. © 2014 AIP Publishing LLC.

Fourier spectrum based extraction of an equivalent trap state density in indium gallium zinc oxide transistors

Segregating the dynamics of gate bias induced threshold voltage shift, and in particular, charge trapping in thin film transistors (TFTs) based on time constants provides insight into the different mechanisms underlying TFTs instability. In this Letter we develop a representation of the time constants and model the magnitude of charge trapped in the form of an equivalent density of created trap states. This representation is extracted from the Fourier spectrum of the dynamics of charge trapping. Using amorphous In-Ga-Zn-O TFTs as an example, the charge trapping was modeled within an energy range of ΔEt 0.3 eV and with a density of state distribution as Dt(Et-j)=Dt0exp(-ΔEt/ kT)with Dt0 = 5.02 × 1011 cm-2 eV-1. Such a model is useful for developing simulation tools for circuit design. © 2014 AIP Publishing LLC.

High performance transistors based on the controlled growth of triisopropylsilylethynyl-pentacene crystals via non-isotropic solvent evaporation

Triisopropylsilylethynyl-pentacene (TIPS-PEN) has proven to be one of the most promising small molecules in the field of molecular electronics, due to its unique features in terms of stability, performance and ease of processing. Among a wide variety of well-established techniques for the deposition of TIPS-PEN, blade-metered methods have recently gained great interest towards the formation of uniform crystalline films over a large area. Following this rationale, we herein designed a versatile approach based on blade-coating, which overcomes the problem of anisotropic crystal formation by manipulating the solvent evaporation behaviour, in a way that brings about a preferential degree of crystal orientation. The applicability of this method was evaluated by fabricating field-effect transistors on glass as well as on silicon dioxide/silicon (SiO2/Si) substrates. Interestingly, in an attempt to improve the rheological and wetting behaviour of the liquid films on the SiO2/Si substrates, we introduced a polymeric interlayer of polystyrene (PS) or polymethylmethacrylate (PMMA) which concurrently acts as passivation and crystallization assisting layer. In this case, the synergistic effects of the highly-ordered crystalline structure and the oxide surface modification were thoroughly investigated. The overall performance of the fabricated devices revealed excellent electrical characteristics, with high saturation mobilities up to 0.72 cm2 V-1 s-1 (on glass with polymeric dielectric), on/off current ratio >104 and low threshold voltage values (<-5 V). This journal is © the Partner Organisations 2014.

Zinc oxide nanowire networks for macroelectronic devices

Highly transparent zinc oxide (ZnO) nanowire networks have been used as the active material in thin film transistors (TFTs) and complementary inverter devices. A systematic study on a range of networks of variable density and TFT channel length was performed. ZnO nanowire networks provide a less lithographically intense alternative to individual nanowire devices, are always semiconducting, and yield significantly higher mobilites than those achieved from currently used amorphous Si and organic TFTs. These results suggest that ZnO nanowire networks could be ideal for inexpensive large area electronics. © 2009 American Institute of Physics.

A comparative study of plasma-enhanced chemical vapor gate dielectrics for solution-processed polymer thin-film transistor circuit integration

This paper considers plasma-enhanced chemical vapor deposited (PECVD) silicon nitride (SiNx) and silicon oxide (SiOx) as gate dielectrics for organic thin-film transistors (OTFTs), with solution-processed poly[5, 5′ -bis(3-dodecyl-2-thienyl)-2, 2′ -bithiophene] (PQT-12) as the active semiconductor layer. We examine transistors with SiNx films of varying composition deposited at 300 °C as well as 150 °C for plastic compatibility. The transistors show over 100% (two times) improvement in field-effect mobility as the silicon content in SiNx increases, with mobility (μFE) up to 0.14 cm2 /V s and on/off current ratio (ION / IOFF) of 108. With PECVD SiOx gate dielectric, preliminary devices exhibit a μFE of 0.4 cm2 /V s and ION / IOFF of 108. PQT-12 OTFTs with PECVD SiNx and SiOx gate dielectrics on flexible plastic substrates are also presented. These results demonstrate the viability of using PECVD SiN x and SiOx as gate dielectrics for OTFT circuit integration, where the low temperature and large area deposition capabilities of PECVD films are highly amenable to integration of OTFT circuits targeted for flexible and lightweight applications. © 2008 American Institute of Physics.

Local hydrogen reactions of H*2 in a-Si:H

Hydrogen rearrangements at the H*2 complex are used as a model of low energy, local transitions in the two-hydrogen density of states of hydrogenated amorphous silicon (a-Si:H). These are used to account for the low activation energy motion of H observed by nuclear magnetic resonance, the low energy defect annealing of defects formed by bias stress in thin film transistors, and the elimination of hydrogen from the growth zone during the low temperature plasma deposition of a-Si:H. © 1998 Elsevier Science B.V. All rights reserved.

Design and coupled-effect simulations of CMOS micro gas-sensors built on SOI thin membranes

This paper describes coupled-effect simulations of smart micro gas-sensors based on standard BiCMOS technology. The smart sensor features very low power consumption, high sensitivity and potential low fabrication cost achieved through full CMOS integration. For the first time the micro heaters are made of active CMOS elements (i.e. MOSFET transistors) and embedded in a thin SOI membrane consisting of Si and SiO2 thin layers. Micro gas-sensors such as chemoresistive, microcalorimeteric and Pd/polymer gate FET sensors can be made using this technology. Full numerical analyses including 3D electro-thermo-mechanical simulations, in particular stress and deflection studies on the SOI membranes are presented. The transducer circuit design and the post-CMOS fabrication process, which includes single sided back-etching, are also reported.

Semi-analytic slope delay model for CMOS switch-level timing verification

A novel slope delay model for CMOS switch-level timing verification is presented. It differs from conventional methods in being semianalytic in character. The model assumes that all input waveforms are trapezoidal in overall shape, but that they vary in their slope. This simplification is quite reasonable and does not seriously affect precision, but it facilitates rapid solution. The model divides the stages in a switch-level circuit into two types. One corresponds to the logic gates, and the other corresponds to logic gates with pass transistors connected to their outputs. Semianalytic modeling for both cases is discussed.

Carbon nanotube Schottky diode and directionally dependent field-effect transistor using asymmetrical contacts

We demonstrate the fabrication and operation of a carbon nanotube (CNT) based Schottky diode by using a Pd contact (high-work-function metal) and an Al contact (low-work-function metal) at the two ends of a single-wall CNT. We show that it is possible to tune the rectification current-voltage (I-V) characteristics of the CNT through the use of a back gate. In contrast to standard back gate field-effect transistors (FET) using same-metal source drain contacts, the asymmetrically contacted CNT operates as a directionally dependent CNT FET when gated. While measuring at source-drain reverse bias, the device displays semiconducting characteristics whereas at forward bias, the device is nonsemiconducting. © 2005 American Institute of Physics.