Voltage sensing buck converter-based technique for maximum photovoltaic solar energy delivery

A voltage sensing buck converter-based technique for maximum solar power delivery to a load is presented. While retaining the features and advantages of the incremental conductance algorithm, this technique is more desirable because of single sensor use. The technique operates by maximising power at the buck converter output instead of the input.

Influence of voltage and frequency dimming on power losses in hf electronic ballasts for compact fluorescent lamps

Compact fluorescent lamps (CFLs) incorporating electronic ballasts are widely used in lighting. In many cases, the ability to dim the lamp is a requirement. Dimming can be achieved by varying the switching frequency of the inverter or by changing the voltage supplied to the inverter. The effect of dimming by both approaches on the power losses in the inverter is studied in this work. The lamp and associated inverter has been modeled in Pspice, using a behavioral model for the CFL. Predicted losses are in good agreement with experimental data obtained from calorimetry. After verification, the model was then used to determine the distribution of losses within the inverter, enabling a comparison of the effects of the two dimming methods to be made. © 2011 IEEE.

Breakdown voltage for superjunction power devices with charge imbalance: An analytical model valid for both punch through and non punch through devices

An analytical model for the electric field and the breakdown voltage (BV) of an unbalanced superjunction (SJ) device is presented in this paper. The analytical technique uses a superposition approach treating the asymmetric charge in the pillars as an excess charge component superimposed on a balanced charge component. The proposed double-exponentialmodel is able to accurately predict the electric field and the BV for unbalanced SJ devices in both punch through and non punch through conditions. The model is also reasonably accurate at extremely high levels of charge imbalance when the devices behave similarly to a PiN diode or to a high-conductance layer. The analytical model is compared against numerical simulations of charge unbalanced SJ devices and against experimental results. © 2009 IEEE.

Symmetrical low voltage ride-through of the Brushless Doubly-Fed Induction Generator

The Brushless Doubly-Fed Induction Generator (BDFIG) shows commercial promise for wind power generation due to its lower cost and higher reliability compared to the Doubly-Fed Induction Generator (DFIG). For the purposes of commercialisation, the BDFIG must meet grid codes at all times. Nowadays, all new wind generators have to ride through certain grid faults, and the Low-Voltage Ride Through (LVRT) capability has become one of the most important points on which to assess the performance a generator. This paper, for the first time, proposes a control scheme to enable the the BDFIG to ride through symmetrical voltage dips. Simulation results and experimental results on a prototype BDFIG show that the proposed scheme gives the capability to ride through low voltage faults. © 2011 IEEE.

One step self-aligned multilayer patterning process for the fabrication of organic complementary circuits in combination with inkjet printing

Recent development of solution processable organic semiconductors delineates the emergence of a new generation of air-stable, high performance p- and n-type materials. This makes it indeed possible for printed organic complementary circuits (CMOS) to be used in real applications. The main technical bottleneck for organic CMOS to be adopted as the next generation organic integrated circuit is how to deposit and pattern both p- and n-type semiconductor materials with high resolutions at the same time. It represents a significant technical challenge, especially if it can be done for multiple layers without mask alignment. In this paper, we propose a one-step self-aligned fabrication process which allows the deposition and high resolution patterning of functional layers for both p- and n-channel thin film transistors (TFTs) simultaneously. All the dimensional information of the device components is featured on a single imprinting stamp, and the TFT-channel geometry, electrodes with different work functions, p- and n-type semiconductors and effective gate dimensions can all be accurately defined by one-step imprinting and the subsequent pattern transfer process. As an example, we have demonstrated an organic complementary inverter fabricated by 3D imprinting in combination with inkjet printing and the measured electrical characteristics have validated the feasibility of the novel technique. © 2012 Elsevier B.V. All rights reserved.

Compact three-dimensional silicon termination solutions for high voltage SOI SuperJunction

This paper demonstrates and discusses novel "three dimensional" silicon based junction isolation/termination solutions suitable for high density ultra-low-resistance Lateral Super-Junction structures. The proposed designs are both compact and effective in safely distributing the electrostatic potential away from the active device area. The designs are based on the utilization of existing layers in the device fabrication line, hence resulting in no extra complexity or cost increase. The study/demonstration is done through extensive experimental measurements and numerical simulations. © 2012 IEEE.

A fast 600-V Tandem PiN Schottky (TPS) rectifier with ultra-low on-state voltage

The Tandem PiN Schottky (TPS) rectifier features lowly-doped p-layers in both active and termination regions, and is applied in 600-V rating for the first time. In the active region, the Schottky contact is in series connection with a transparent p-layer, leading to a superior forward performance than the conventional diodes. In addition, due to the benefit of moderate hole injection from the p-layer, the TPS offers a better trade-off between the on-state voltage and the switching speed. The active p-layer also helps to stabilise the Schottky contact, and hence the electrical data distributions are more concentrated. Regarding the floating p-layer in the termination region, its purpose is to reduce the peak electric fields, and the TPS demonstrates a high breakdown voltage with a compact termination width, less than 70% of the state-of-the-art devices on the market. Experimental results have shown that the 600-V TPS rectifier has an ultra-low on-state voltage of 0.98 V at 250 A/cm 2, a fast turn-off time of 75 ns by the standard RG1 test (I F=0.5A, I R=1A, and I RR=0.25A) and a breakdown voltage over 720 V. It is noteworthy that the p-layers in the active and termination regions can be formed at no extra cost for the use of self-alignment process. © 2012 IEEE.

Increasing the open-circuit voltage of photoprotein-based photoelectrochemical cells by manipulation of the vacuum potential of the electrolytes.

The innately highly efficient light-powered separation of charge that underpins natural photosynthesis can be exploited for applications in photoelectrochemistry by coupling nanoscale protein photoreaction centers to man-made electrodes. Planar photoelectrochemical cells employing purple bacterial reaction centers have been constructed that produce a direct current under continuous illumination and an alternating current in response to discontinuous illumination. The present work explored the basis of the open-circuit voltage (V(OC)) produced by such cells with reaction center/antenna (RC-LH1) proteins as the photovoltaic component. It was established that an up to ~30-fold increase in V(OC) could be achieved by simple manipulation of the electrolyte connecting the protein to the counter electrode, with an approximately linear relationship being observed between the vacuum potential of the electrolyte and the resulting V(OC). We conclude that the V(OC) of such a cell is dependent on the potential difference between the electrolyte and the photo-oxidized bacteriochlorophylls in the reaction center. The steady-state short-circuit current (J(SC)) obtained under continuous illumination also varied with different electrolytes by a factor of ~6-fold. The findings demonstrate a simple way to boost the voltage output of such protein-based cells into the hundreds of millivolts range typical of dye-sensitized and polymer-blend solar cells, while maintaining or improving the J(SC). Possible strategies for further increasing the V(OC) of such protein-based photoelectrochemical cells through protein engineering are discussed.

NEMS based logic and memory circuits

Carbon nanotube (CNT) based nano electromechanical system (NEMS) were developed to apply to the logic and the memory circuit. The electrical 'on-off' behavior induced by the mechanical movements of CNTs can promise low power consumption in circuit with very low level leakage current. Additionally, the unique vertical structure of nanotubes allows high integration density for devices. © 2012 IEEE.

Symmetrical low voltage ride-through of a 250 kW Brushless DFIG

The Brushless Doubly-Fed Induction Generator (Brushless DFIG) shows commercial promise for wind power generation due to its lower cost and higher reliability when compared with the conventional Doubly-Fed Induction Generator (DFIG). In the most recent grid codes, wind generators are required to be able to ride through a low voltage fault and meet the reactive current demand from the grid. Hence, a Low-Voltage Ride-Through (LVRT) capability is important for wind generators which are integrated into the grid. In this paper the authors propose a control strategy enabling the Brushless DFIG to successfully ride through a symmetrical voltage dip. The control strategy has been implemented on a 250 kW Brushless DFIG and the experimental results indicate that LVRT is possible without a crowbar.

IGBT series connection under Active Voltage Control with temporary clamp

This paper presents the use of an Active Voltage Control (AVC) technique for balancing the voltages in a series connection of Insulated Gate Bipolar Transistors (IGBTs). The AVC technique can control the switching trajectory of an IGBT according to a pre-set reference signal. In series connections, every series connected IGBT follows the reference and so that the dynamic voltage sharing is achieved. For the static voltage balancing, a temporary clamp technique is introduced. The temporary clamp technique clamps the collector-emitter voltage of all the series connected IGBTs at the ideal voltage so that the IGBTs will share the voltage evenly. © 2012 IEEE.

Dead-time minimisation using active voltage control gate drive for high-power IGBT converters

High-power converters usually need longer dead-times than their lower-power counterparts and a lower switching frequency. Also due to the complicated assembly layout and severe variations in parasitics, in practice the conventional dead-time specific adjustment or compensation for high-power converters is less effective, and usually this process is time-consuming and bespoke. For general applications, minimising or eliminating dead-time in the gate drive technology is a desirable solution. With the growing acceptance of power electronics building blocks (PEBB) and intelligent power modules (IPM), gate drives with intelligent functions are in demand. Smart functions including dead time elimination/minimisation can improve modularity, flexibility and reliability. In this paper, a dead-time minimisation using Active Voltage Control (AVC) gate drive is presented. © 2012 IEEE.