Trench MOS-gated power devices

MOS gated power devices are now available for power switching applications with voltage blocking requirements up to 1 kV and current ratings up to 300A. This is due to the invention of the IGBT, a device in which MOS gate turn-on leads to minority carrier injection to modulate the high resistance drift region required for voltage blocking. The paper presents current technologies being developed in order to expand the applications of MOS gated power devices. Also explained is the available trench gate technology that can be used to fabricate power devices.

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An ingenious new CMOS-compatible process which promises to significantly improve the performance of power devices is discussed. A novel power device concept based on the use of high voltage regions suspended on thin semiconductor/dielectric membranes is reported. The membrane power devices are manufactured in a fully-CMOS compatible silicon-on-insulator (SOI) process followed by a bulk etching step and subsequent back-passivation. The concept is applicable to a class of high voltage devices such as LDMOSFETs, diodes, LIGBTs and superjunctions.

Optimum design of 1.4KV trench IGBTs - The next generation of high power switching devices

The Trench Insulated Gate Bipolar Transistor (IGBT) is the most promising structure for the next generation of power semiconductor devices with wide applications ranging from motor control (1-4 kV) to HVDC (6.5 kV). Here we present for the first time an optimum design of a 1.4kV Trench IGBT using a new, fully integrated optimisation system comprising process and device simulators and the RSM optimiser. The use of this new TCAD system has contributed largely to realizing devices with characteristics far superior to the previous DMOS generation of IGBTs. Full experimental results on 1.4kV Trench IGBTs which are in excellent agreement with the TCAD predictions are reported.

Synapses with short-term plasticity are optimal estimators of presynaptic membrane potentials.

The trajectory of the somatic membrane potential of a cortical neuron exactly reflects the computations performed on its afferent inputs. However, the spikes of such a neuron are a very low-dimensional and discrete projection of this continually evolving signal. We explored the possibility that the neuron's efferent synapses perform the critical computational step of estimating the membrane potential trajectory from the spikes. We found that short-term changes in synaptic efficacy can be interpreted as implementing an optimal estimator of this trajectory. Short-term depression arose when presynaptic spiking was sufficiently intense as to reduce the uncertainty associated with the estimate; short-term facilitation reflected structural features of the statistics of the presynaptic neuron such as up and down states. Our analysis provides a unifying account of a powerful, but puzzling, form of plasticity.

An extended computational model of the circulatory system for designing ventricular assist devices.

An extended computational model of the circulatory system has been developed to predict blood flow in the presence of ventricular assist devices (VADs). A novel VAD, placed in the descending aorta, intended to offload the left ventricle (LV) and augment renal perfusion is being studied. For this application, a better understanding of the global hemodynamic response of the VAD, in essence an electrically driven pump, and the cardiovascular system is necessary. To meet this need, a model has been established as a nonlinear, lumped-parameter electrical analog, and simulated results under different states [healthy, congestive heart failure (CHF), and postinsertion of VAD] are presented. The systemic circulation is separated into five compartments and the descending aorta is composed of three components to accurately yield the system response of each section before and after the insertion of the VAD. Delays in valve closing time and blood inertia in the aorta were introduced to deliver a more realistic model. Pump governing equations and optimization are based on fundamental theories of turbomachines and can serve as a practical initial design point for rotary blood pumps. The model's results closely mimic established parameters for the circulatory system and confirm the feasibility of the intra-aortic VAD concept. This computational model can be linked with models of the pump motor to provide a valuable tool for innovative VAD design.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.