Switching performance of epitaxially grown normally-off 4H-SiC JFET

Static and dynamic behavior of the epitaxially grown dual gate trench 4H-SiC junction field effect transistor (JFET) is investigated. Typical on-state resistance Ron was 6-10mΩcm2 at VGS = 2.5V and the breakdown voltage between the range of 1.5-1.8kV was realized at VGS = -5V for normally-off like JFETs. It was found that the turn-on energy delivers the biggest part of the switching losses. The dependence of switching losses from gate resistor is nearly linear, suggesting that changing the gate resistor, a way similar to Si-IGBT technology, can easily control di/dt and dv/dt. Turn-on losses at 200°C are lower compared to those at 25°C, which indicates the influence of the high internal p-type gate layer resistance. Inductive switching numerical analysis suggested the strong influence of channel doping conditions on the turn-on switching performance. The fast switching normally-off JFET devices require heavily doped narrow JFET channel design. © (2009) Trans Tech Publications, Switzerland.

Evidence of quantum lateral confinement in side-gated resonant tunnelling diodes formed by patterned substrate regrowth

MBE regrowth on patterned np-GaAs wafers has been used to fabricate GaAs/AlGaAs double barrier resonant tunnel diodes with a side-gate in the plane of the quantum well. The physical diameters vary from 1 to 20 μm. For a nominally 1 μm diameter diode the peak current is reduced by more than 95% at a side-gate voltage of -2 V at 1.5 K, which we estimate corresponds to an active tunnel region diameter of 75 nm ± 10 nm. At high gate biases additional structure appears in the conductance data. Differential I-V measurements show a linear dependence of the spacing of subsidiary peaks on gate bias indicating lateral quantum confinement. © 1996 American Institute of Physics.

Design and coupled-effect simulations of CMOS micro gas-sensors built on SOI thin membranes

This paper describes coupled-effect simulations of smart micro gas-sensors based on standard BiCMOS technology. The smart sensor features very low power consumption, high sensitivity and potential low fabrication cost achieved through full CMOS integration. For the first time the micro heaters are made of active CMOS elements (i.e. MOSFET transistors) and embedded in a thin SOI membrane consisting of Si and SiO2 thin layers. Micro gas-sensors such as chemoresistive, microcalorimeteric and Pd/polymer gate FET sensors can be made using this technology. Full numerical analyses including 3D electro-thermo-mechanical simulations, in particular stress and deflection studies on the SOI membranes are presented. The transducer circuit design and the post-CMOS fabrication process, which includes single sided back-etching, are also reported.

Switch-level timing verification for CMOS circuits. A semianalytic approach

The paper describes a semianalytic slope delay model for CMOS switch-level timing verification. It is characterised by classification of the effects of the input slope, internal size and load capacitance of a logic gate on delay time, and then the use of a series of carefully chosen analytic functions to estimate delay times under different circumstances. In the field of VLSI analysis, this model achieves improvements in speed and accuracy compared with conventional approaches to transistor-level and switch-level simulation.

High temperature direct double side cooled inverter module for hybrid electric vehicle application

In this paper a novel approach to the design and fabrication of a high temperature inverter module for hybrid electrical vehicles is presented. Firstly, SiC power electronic devices are considered in place of the conventional Si devices. Use of SiC raises the maximum practical operating junction temperature to well over 200°C, giving much greater thermal headroom between the chips and the coolant. In the first fabrication, a SiC Schottky barrier diode (SBD) replaces the Si pin diode and is paired with a Si-IGBT. Secondly, double-sided cooling is employed, in which the semiconductor chips are sandwiched between two substrate tiles. The tiles provide electrical connections to the top and the bottom of the chips, thus replacing the conventional wire bonded interconnect. Each tile assembly supports two IGBTs and two SBDs in a half-bridge configuration. Both sides of the assembly are cooled directly using a high-performance liquid impingement system. Specific features of the design ensure that thermo-mechanical stresses are controlled so as to achieve long thermal cycling life. A prototype 10 kW inverter module is described incorporating three half-bridge sandwich assemblies, gate drives, dc-link capacitance and two heat-exchangers. This achieves a volumetric power density of 30W/cm3.

Persistent photoconductivity in Hf-In-Zn-O thin film transistors

Passivated Hf-In-Zn-O (HIZO) thin film transistors suffer from a negative threshold voltage shift under visible light stress due to persistent photoconductivity (PPC). Ionization of oxygen vacancy sites is identified as the origin of the PPC following observations of its temperature- and wavelength-dependence. This is further corroborated by the photoluminescence spectrum of the HIZO. We also show that the gate voltage can control the decay of PPC in the dark, giving rise to a memory action. © 2010 American Institute of Physics.

Self-aligned electrodes for suspended carbon nanotube structures

We report on a study into electrode fabrication for the gate control of carbon nanotubes partially suspended above an oxidised silicon substrate. A fabrication technique has been developed that allows self-aligned side-gate electrodes to be placed with respect to an individual nanotube with a spacing of less than 10 nm. The suspended multi-walled carbon nanotube (MWCNT) is used as an evaporation mask during metal deposition. The metal forms an island on the nanotube, with increasing width as the metal is deposited, forming a wedge shape, so that even thick deposited layers yield islands that remain separated from the metal deposited on the substrate due to shadowing of the evaporation. The island can be removed during lift-off to leave a set of self-aligned electrodes on the substrate. Results show that Cr yields self-aligned side gates with around 90% effectiveness. © 2003 Elsevier Science B.V. All rights reserved.

Fabrication of self-aligned side gates to carbon nanotubes

We have fabricated self-aligned, side-gated suspended multi-walled carbon nanotubes (MWCNTs), with nanotube-to-gate spacing of less than 10 nm. Evaporated metal forms an island on a suspended MWCNT, the island and the nanotube act as a mask shielding the substrate, and lift-off then removes the metal island, leaving a set of self-aligned side gates. Al, Cr, Au, and Ti were investigated and the best results were obtained with Cr, at a yield of over 90%.

Carbon nanotube Schottky diode and directionally dependent field-effect transistor using asymmetrical contacts

We demonstrate the fabrication and operation of a carbon nanotube (CNT) based Schottky diode by using a Pd contact (high-work-function metal) and an Al contact (low-work-function metal) at the two ends of a single-wall CNT. We show that it is possible to tune the rectification current-voltage (I-V) characteristics of the CNT through the use of a back gate. In contrast to standard back gate field-effect transistors (FET) using same-metal source drain contacts, the asymmetrically contacted CNT operates as a directionally dependent CNT FET when gated. While measuring at source-drain reverse bias, the device displays semiconducting characteristics whereas at forward bias, the device is nonsemiconducting. © 2005 American Institute of Physics.

Self-aligned, gated arrays of individual nanotube and nanowire emitters

We demonstrate the production of integrated-gate nanocathodes which have a single carbon nanotube or silicon nanowire/whisker per gate aperture. The fabrication is based on a technologically scalable, self-alignment process in which a single lithographic step is used to define the gate, insulator, and emitter. The nanotube-based gated nanocathode array has a low turn-on voltage of 25 V and a peak current of 5 μA at 46 V, with a gate current of 10 nA (i.e., 99% transparency). These low operating voltage cathodes are potentially useful as electron sources for field emission displays or miniaturizing electron-based instrumentation.

Trench MOS-gated power devices

MOS gated power devices are now available for power switching applications with voltage blocking requirements up to 1 kV and current ratings up to 300A. This is due to the invention of the IGBT, a device in which MOS gate turn-on leads to minority carrier injection to modulate the high resistance drift region required for voltage blocking. The paper presents current technologies being developed in order to expand the applications of MOS gated power devices. Also explained is the available trench gate technology that can be used to fabricate power devices.

Analysis of SEB and SEGR in super-junction MOSFETs

The electric field distribution in the super junction power MOSFET is analyzed using analytical modeling and numerical simulations in this paper. The single-event burn-out (SEB) and single-event gate rupture (SEGR) phenomena in this device are studied in detail. It is demonstrated that the super junction device is much less sensitive to SEB and SEGR compared to the standard power MOSFET. The physical mechanism is explained.

p-MOS controlled lateral thyristor: A MOS controllable thyristor suitable for integration

A novel CMOS compatible lateral thyristor is proposed in this paper. Its thyristor conduction is fully controlled by a p-MOS gate. Loss of MOS control due to parasitic latch-up has been eliminated and triggering of the main thyristor at lower forward current achieved. The device operation has been verified by 2-D numerical simulations and experimental fabrication.

Compact double-side liquid-impingement-cooled integrated power electronic module

This paper presents a compact integrated power electronic module (IPEM) which seeks to overcome the volumetric power density limitations of conventional packaging technologies. A key innovation has been the development of a substrate sandwich structure which permits double side cooling of the embedded dies whilst controlling the mechanical stresses both within the module and at the heat exchanger interface. A 3-phase inverter module has been developed, integrating the sandwich structures with high efficiency impingement coolers, delink capacitance and gate drive units. Full details of the IPEM construction and electrical evaluation are given in the paper. © 2007 IEEE.

Optimum design of 1.4KV trench IGBTs - The next generation of high power switching devices

The Trench Insulated Gate Bipolar Transistor (IGBT) is the most promising structure for the next generation of power semiconductor devices with wide applications ranging from motor control (1-4 kV) to HVDC (6.5 kV). Here we present for the first time an optimum design of a 1.4kV Trench IGBT using a new, fully integrated optimisation system comprising process and device simulators and the RSM optimiser. The use of this new TCAD system has contributed largely to realizing devices with characteristics far superior to the previous DMOS generation of IGBTs. Full experimental results on 1.4kV Trench IGBTs which are in excellent agreement with the TCAD predictions are reported.