Contingency awareness in human aversive conditioning involves the middle frontal gyrus.

In contrast to the wealth of data describing the neural mechanisms underlying classical conditioning, we know remarkably little about the mechanisms involved in acquisition of explicit contingency awareness. Subjects variably acquire contingency awareness in classical conditioning paradigms, in which they are able to describe the temporal relationship between a conditioned cue and its outcome. Previous studies have implicated the hippocampus and prefrontal cortex in the acquisition of explicit knowledge, although their specific roles remain unclear. We used functional magnetic resonance imaging to track the trial-by-trial acquisition of explicit knowledge in a concurrent trace and delay conditioning paradigm. We show that activity in bilateral middle frontal gyrus and parahippocampal gyrus correlates with the accuracy of explicit contingency awareness on each trial. In contrast, amygdala activation correlates with conditioned responses indexed by skin conductance responses (SCRs). These results demonstrate that brain regions known to be involved in other aspects of learning and memory also play a specific role, reflecting on each trial the acquisition and representation of contingency awareness.

100 Gb/s uncooled WDM system using conventional WDM components and advanced receiver signal processing

We demonstrate an uncooled WDM system using standard WDM components and receiver signal processing, with a different number of receivers to transmitters, to allow wide temperature drift of the transmitter lasers. A 100 Gb/s 8-wavelength demonstrator has been developed, which proves the feasibility of the approach over 25 km of SMF. © 2012 OSA.

Thyristors

Thyristors are usually three-terminal devices that have four layers of alternating p-type and n-type material (i.e. three p-n junctions) comprising its main power handling section. In contrast to the linear relation which exists between load and control currents in a transistor, the thyristor is bistable. The control terminal of the thyristor, called the gate (G) electrode, may be connected to an integrated and complex structure as a part of the device. Thyristors are used to approximate ideal closed (no voltage drop between anode and cathode) or open (no anode current flow) switches for control of power flow in a circuit. This differs from low-level digital switching circuits that are designed to deliver two distinct small voltage levels while conducting small currents (ideally zero). Thyristor circuits must have the capability of delivering large currents and be able to withstand large externally applied voltages. All thyristor types are controllable in switching from a forward-lockingstate (positive potential applied to the anode with respect to the cathode, with correspondingly little anode current flow) into a forward-conduction state (large forward anode current flowing, with a small anode-cathode potential drop). Most thyristors have the characteristic that after switching from a forward-blocking state into the forward-conduction state, the gate signal can be removed and the thyristor will remain in its forward-conduction mode. This property is termed "latching" and is an important distinction between thyristors and other types of power electronic devices. © 2007 Elsevier Inc. All rights reserved.

Energy performance certification as a signal of workplace quality

Energy performance labelling and certification have been introduced widely to address market failures affecting the uptake of energy efficient technologies, by providing a signal to support decision making during contracting processes. The UK has recently introduced the Energy Performance Certificate (EPC) as a signal of building energy performance. The aims of this article are: to evaluate how valid EPC's are signals of occupier satisfaction with office facilities; and to understand whether occupant attitudes towards environmental issues have affected commercial office rental values. This was achieved by surveying occupant satisfaction with their workplaces holistically using a novel multi-item rating scale which gathered 204 responses. Responses to this satisfaction scale were matched with the corresponding EPC and rental value of occupier's workplaces. The satisfaction scale was found to be both a reliable and valid measure. The analysis found that EPC asset rating correlates significantly with occupant satisfaction with all facility attributes. Therefore, EPC ratings may be considered valid signals of overall facility satisfaction within the survey sample. Rental value was found to correlate significantly only with facility aesthetics. No evidence suggests rental value has been affected by occupants' perceptions towards the environmental impact of facilities. © 2013 The Authors.

Degenerate mode-group division multiplexing using MIMO digital signal processing

MIMO DSP is employed to improve the performance of degenerate mode-group division multiplexing in 8 km of conventional GI-MMF. Compensation of the mode coupling, induced by the launch and propagation, between and inside each degenerate mode-group is investigated in order to reduce the DSP complexity. © 2013 IEEE.

Integration of silicon plasmonic schottky photodetector for on chip signal tapping at telecom wavelengths

We experimentally demonstrate the use of an on-chip integrated Schottky plasmonic detector for testing, monitoring and tapping signals in plasmonic and photonic devices. Theoretical model and measurement of external and integrated devices will be presented. © OSA 2013.

Integration of silicon plasmonic schottky photodetector for on chip signal tapping at telecom wavelengths

We experimentally demonstrate the use of an on-chip integrated Schottky plasmonic detector for testing, monitoring and tapping signals in plasmonic and photonic devices. Theoretical model and measurement of external and integrated devices will be presented. © OSA 2013.

Integration of silicon plasmonic schottky photodetector for on chip signal tapping at telecom wavelengths

We experimentally demonstrate the use of an on-chip integrated Schottky plasmonic detector for testing, monitoring and tapping signals in plasmonic and photonic devices. Theoretical model and measurement of external and integrated devices will be presented. © OSA 2013.

100 Gb/s uncooled WDM system using conventional WDM components and advanced receiver signal processing

We demonstrate an uncooled WDM system using standard WDM components and receiver signal processing, with a different number of receivers to transmitters, to allow wide temperature drift of the transmitter lasers. A 100 Gb/s 8-wavelength demonstrator has been developed, which proves the feasibility of the approach over 25 km of SMF. © 2012 Optical Society of America.

Gigahertz multi-transistor graphene integrated circuits

We review the potential of graphene in ultra-high speed circuits. To date, most of high-frequency graphene circuits typically consist of a single transistor integrated with a few passive components. The development of multi-transistor graphene integrated circuits operating at GHz frequencies can pave the way for applications in which high operating speed is traded off against power consumption and circuit complexity. Novel vertical and planar devices based on a combination of graphene and layered materials could broaden the scope and performances of future devices. © 2013 IEEE.

A 40 Gb/s optical bus for optical backplane interconnections

Optical technologies have received large interest in recent years for use in board-level interconnects. Polymer multimode waveguides in particular, constitute a promising technology for high-capacity optical backplanes as they can be cost-effectively integrated onto conventional printed circuit boards (PCBs). This paper presents the first optical backplane demonstrator based on the use of PCB-integrated polymer multimode waveguides and a regenerative shared bus architecture. The backplane demonstrator is formed with commercially-available low-cost electronic and photonic components onto conventional FR4 substrates and comprises two opto-electronic (OE) bus modules interconnected via a prototype regenerator unit. The system enables interconnection between the connected cards over four optical channels, each operating at 10 Gb/s. Bus extension is achieved by cascading OE bus modules via 3R regenerator units, overcoming therefore the inherent limitation of optical bus topologies in the maximum number of cards that can be connected to the bus. Details of the design, fabrication, and assembly of the different parts of this optical bus backplane are presented and related optical and data transmission characterisation studies are reported. The optical layer of the OE bus modules comprises a four-channel three-card waveguide layout that is compatible with VCSEL/PD arrays and ribbon fibres. All on-board optical paths exhibit insertion losses below 13 dB and intra-channel crosstalk lower than -29 dB. The robustness of the signal distribution from the bus inputs to all respective bus output ports in the presence of input misalignment is demonstrated, while 1 dB input alignment tolerances of approximately ±10 μm are obtained. The electrical layer of the OE bus modules comprises the essential driving circuitry for 1×4 VCSEL and PD arrays and the corresponding control and power regulation circuits. The interface between the optical and electrical layers of the bus modules is achieved with simple OE connectors that enable end-fired optical coupling into and out of the on-board polymer waveguides. The backplane demonstrator achieves error-free (BER < 10-12) 10 Gb/s data transmission over each optical channel, enabling therefore, an aggregate interconnection capacity of 40 Gb/s between any connected cards. © 1983-2012 IEEE.