293 resultados para Multiwalled carbon nanotubes (MWCN)


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The best field emission properties from carbon nanotube cathodes were obtained when their heights, diameters and spacings were optimized. Field emission currents as high as 10 mA were obtained from 1 cm × 1 cm vertically aligned CNT cathode with optimized parameters grown using dc plasma CVD in situ. It was found that in order to obtain large emission current of >10 mA, space charge effects within the electron beam must be taken into account.

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The overall aim of this work is to produce arrays of field emitting microguns, based on carbon nanotubes, which can be utilised in the manufacture of large area field emitting displays, parallel e-beam lithography systems and electron sources for high frequency amplifiers. This paper will describe the work carried out to produce patterned arrays of aligned multiwall carbon nanotubes (MWCNTs) using a dc plasma technique and a Ni catalyst. We will discuss how the density of the carbon nanotube/fibres can be varied by reducing the deposition yield through nickel interaction with a diffusion layer or by direct lithographic patterning of the Ni catalyst to precisely define the position of each nanotube/fibre. Details of the field emission behaviour of the different arrays of MWCNTS will also be presented. © 2002 Published by Elsevier Science B.V.

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We synthesize Co nanorod filled inside multi-walled CNTs (MWCNTs) by microwave plasma enhanced chemical vapor deposition (MPECVD) and utilize off-axis electron holography to observe the remanent states of the filled metal nanorod inside MWCNTs at room. The MWCNTs grew up to 100-110 nm in diameter and 1.5-1.7 μm in length. The typical bright-field transmission electron microscope (TEM) images revealed both Co/Pd multisegment nanorod and Co nanorod filled inside MWCNTs on the same substrate. We have also performed energy-dispersive X-ray spectrometer (EDS) measurements to characterize the composition of metal filled inside MWCNTs. Based on high-resolution TEM measurements, we observed the face-centered-cubic (fcc) Co filled inside MWCNT. The component of magnetic induction was then measured to be 1.2±0.1 T, which is lower than the expected saturation magnetization of fcc Co of 1.7 T. The partial oxidation of the ferromagnetic metal during the process and the magnetization direction may play an important role in the determination of the quality of the remanent states. © 2008 IEEE.

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This paper presents direct growth of horizontally aligned carbon nanotubes (CNTs) between two predefined various inter-spacing up to tens of microns of electrodes (pads) and its use as CNT field-effect transistors (CNT-FETs). The catalytic metals were prepared, consisting of iron (Fe), aluminum (Al) and platinum (Pt) triple layers, on the thermal silicon oxide substrate (Pt/Al/Fe/SiO2). Scanning electron microscopy measurements of CNT-FETs from the as-grown samples showed that over 80% of the nanotubes are grown across the catalytic electrodes. Moreover, the number of CNTs across the catalytic electrodes is roughly controllable by adjusting the growth condition. The Al, as the upper layer on Fe electrode, not only plays a role as a barrier to prevent vertical growth but also serves as a porous medium that helps in forming smaller nano-sized Fe particles which would be necessary for lateral growth of CNTs. Back-gate field effect transistors were demonstrated with the laterally aligned CNTs. The on/off ratios in all the measured devices are lower than 100 due to the drain leakage current. ©2010 IEEE.

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Here we demonstrate a novel technique to grow carbon nanotubes (CNTs) on addressable localized areas, at wafer level, on a fully processed CMOS substrate. The CNTs were grown using tungsten micro-heaters (local growth technique) at elevated temperature on wafer scale by connecting adjacent micro-heaters through metal tracks in the scribe lane. The electrical and optical characterization show that the CNTs are identical and reproducible. We believe this wafer level integration of CNTs with CMOS circuitry enables the low-cost mass production of CNT sensors, such as chemical sensors.

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The direct deposition of carbon nanotubes on CMOS microhotplates is demonstrated in this paper. Tungsten microhotplates, fabricated on thin SOI membranes aside CMOS control circuitry, are used to locally grow carbon nanotubes by chemical vapour deposition. Unlike bulk heating of the entire chip, which could cause degradation to CMOS devices and interconnects due to high growth temperatures in excess of 500 °C, this novel technique allows carbon nanotubes to be grown on-chip in localized regions. The microfabricated heaters are thermally isolated from the rest of the CMOS chip as they are on the membranes. This allows carbon nanotubes to be grown alongside CMOS circuitry on the same wafer without any external heating, thus enabling new applications (e.g. smart gas sensing) where the integration of CMOS and carbon nanotubes is required.

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We present electro-optic characteristics of a transparent nanophotonic device fabricated on quartz substrate based on multiwall carbon nanotubes and nematic liquid crystals (LCs). The nanotube electrodes spawn a Gaussian electric field to three dimensionally address the LC molecules. The electro-optic characteristics of the device were investigated to optimize the device performance and it was found that lower driving voltages were suitable for microlens array and phase modulation applications, while higher driving voltages with a holding voltage can be used for display-related applications.

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This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.