A fast detailed-chemistry modelling approach for simulating the SI-HCCI transition

An established Stochastic Reactor Model (SRM) is used to simulate the transition from Spark Ignition (SI) to Homogeneous Charge Compression Ignition (HCCI) combustion mode in a four cylinder in-line four-stroke naturally aspirated direct injection SI engine with cam profile switching. The SRM is coupled with GT-Power, a one-dimensional engine simulation tool used for modelling engine breathing during the open valve portion of the engine cycle, enabling multi-cycle simulations. The mode change is achieved by switching the cam profiles and phasing, resulting in a Negative Valve Overlap (NVO), opening the throttle, advancing the spark timing and reducing the fuel mass as well as using a pilot injection. A proven technique for tabulating the model is used to create look-up tables in both SI and HCCI modes. In HCCI mode several tables are required, including tables for the first NVO, transient valve timing NVO, transient valve timing HCCI and steady valve timing HCCI and NVO. This results in the ability to simulate the transition with detailed chemistry in very short computation times. The tables are then used to optimise the transition with the goal of reducing NO x emissions and fluctuations in IMEP. Copyright © 2010 SAE International.

A detailed chemistry simulation of the SI-HCCI transition

A Stochastic Reactor Model (SRM) has been used to simulate the transition from Spark Ignition (SI) mode to Homogeneous Charge Compression Ignition (HCCI) mode in a four cylinder in-line four-stroke naturally aspirated direct injection SI engine with cam profile switching. The SRM is coupled with GT-Power, a one-dimensional engine simulation tool used for modelling engine breathing during the open valve portion of the engine cycle, enabling multi-cycle simulations. The model is initially calibrated in both modes using steady state data from SI and HCCI operation. The mode change is achieved by switching the cam profiles and phasing, resulting in a Negative Valve Overlap (NVO), opening the throttle, advancing the spark timing and reducing the fuel mass as well as utilising a pilot injection. Experimental data is presented along with the simulation results. The model is used to investigate key control parameters and their effects on parameters that are difficult to measure experimentally. The effect of the spark in the first HCCI cycles is found to have a major impact on the stability of the transition. Copyright © 2010 SAE International.

A numerical simulation of AFR switch of SI engines

A novel mechanical method of achieving a rapid switch between stoichiometric and lean conditions for SI engines is explored. Two and three throttle configurations, a switch strategy which employs a standard intake manifold and an assembly of pipes and throttle(s), are investigated numerically by using a one-dimensional engine simulation program based on the method of characteristics. The results indicate that it is possible to achieve rapid AFR switch without a torque jump, i.e. unperceptible to the driver. © 1998 Society of Automotive Engineers, Inc.

Taper-free and vertically oriented Ge nanowires on Ge/Si substrates grown by a two-temperature process

Taper-free and vertically oriented Ge nanowires were grown on Si (111) substrates by chemical vapor deposition with Au nanoparticle catalysts. To achieve vertical nanowire growth on the highly lattice mismatched Si substrate, a thin Ge buffer layer was first deposited, and to achieve taper-free nanowire growth, a two-temperature process was employed. The two-temperature process consisted of a brief initial base growth step at high temperature followed by prolonged growth at lower temperature. Taper-free and defect-free Ge nanowires grew successfully even at 270 °C, which is 90 °C lower than the bulk eutectic temperature. The yield of vertical and taper-free nanowires is over 90%, comparable to that of vertical but tapered nanowires grown by the conventional one-temperature process. This method is of practical importance and can be reliably used to develop novel nanowire-based devices on relatively cheap Si substrates. Additionally, we observed that the activation energy of Ge nanowire growth by the two-temperature process is dependent on Au nanoparticle size. The low activation energy (∼5 kcal/mol) for 30 and 50 nm diameter Au nanoparticles suggests that the decomposition of gaseous species on the catalytic Au surface is a rate-limiting step. A higher activation energy (∼14 kcal/mol) was determined for 100 nm diameter Au nanoparticles which suggests that larger Au nanoparticles are partially solidified and that growth kinetics become the rate-limiting step. © 2011 American Chemical Society.

Defect-free GaAs/AlGaAs Core-shell nanowires on Si substrates

We report straight and vertically aligned defect-free GaAs nanowires grown on Si(111) substrates by metal-organic chemical vapor deposition. By deposition of thin GaAs buffer layers on Si substrates, these nanowires could be grown on the buffer layers with much less stringent conditions as otherwise imposed by epitaxy of III-V compounds on Si. Also, crystal-defect-free GaAs nanowires were grown by using either a two-temperature growth mode consisting of a short initial nucleation step under higher temperature followed by subsequent growth under lower temperature or a rapid growth rate mode with high source flow rate. These two growth modes not only eliminated planar crystallographic defects but also significantly reduced tapering. Core-shell GaAs-AlGaAs nanowires grown by the two-temperature growth mode showed improved optical properties with strong photoluminescence and long carrier life times. © 2011 American Chemical Society.

Structural and optical characterization of vertical GaAs/GaP core-shell nanowires grown on Si substrates

GaAs nanowires were grown on Si (111) substrates. By coating a thin GaAs buffer layer on Si surface and using a two-temperature growth, the morphology and crystal structure of GaAs nanowires were dramatically improved. The strained GaAs/GaP core-shell nanowires, based on the improved GaAs nanowires with a shell thickness of 25 nm, showed a significant shift in emission energy of 260 meV from the unstrained GaAs nanowires. © 2010 IEEE.

Novel growth and properties of GaAs nanowires on Si substrates.

Straight, vertically aligned GaAs nanowires were grown on Si(111) substrates coated with thin GaAs buffer layers. We find that the V/III precursor ratio and growth temperature are crucial factors influencing the morphology and quality of buffer layers. A double layer structure, consisting of a thin initial layer grown at low V/III ratio and low temperature followed by a layer grown at high V/III ratio and high temperature, is crucial for achieving straight, vertically aligned GaAs nanowires on Si(111) substrates. An in situ annealing step at high temperature after buffer layer growth improves the surface and structural properties of the buffer layer, which further improves the morphology of the GaAs nanowire growth. Through such optimizations we show that vertically aligned GaAs nanowires can be fabricated on Si(111) substrates and achieve the same structural and optical properties as GaAs nanowires grown directly on GaAs(111)B substrates.

Improvement of morphology, structure, and optical properties of GaAs nanowires grown on Si substrates

We investigate vertical and defect-free growth of GaAs nanowires on Si (111) substrates via a vapor-liquid-solid (VLS) growth mechanism with Au catalysts by metal-organic chemical vapor deposition (MOCVD). By using annealed thin GaAs buffer layers on the surface of Si substrates, most nanowires are grown on the substrates straight, following (111) direction; by using two temperature growth, the nanowires were grown free from structural defects, such as twin defects and stacking faults. Systematic experiments about buffer layers indicate that V/III ratio of precursor and growth temperature can affect the morphology and quality of the buffer layers. Especially, heterostructural buffer layers grown with different V/III ratios and temperatures and in-situ post-annealing step are very helpful to grow well arranged, vertical GaAs nanowires on Si substrates. The initial nanowires having some structural defects can be defect-free by two-temperature growth mode with improved optical property, which shows us positive possibility for optoelectronic device application. ©2010 IEEE.

Vertical CNT-Si photodiode array.

A photodiode consisting of nanopillars of thin-film silicon p-i-n on an array of vertically aligned carbon nanotubes (CNTs) with a noncontinuous cathode electrode is demonstrated. The structure exploits the intrinsic enhancement of the CNTs' electric field, which leads to reduction in the photodiode's operating voltage and response time and enhancement of optical coupling due to better light trapping, as compared with the conventional planar photodiode. These improvements translate to higher resolution and higher frame rate flat-panel imaging systems for a broad range of applications, including computed tomography and particle detection.

Measuring the composition of AlGaN layers in GaN based structures grown on 150 mm Si substrates using (2 0 5) reciprocal space maps

A critical element for the successful growth of GaN device layers on Si is accurate control of the AlGaN buffer layers used to manage strain. Here we present a method for measuring the composition of the AlGaN buffer layers in device structures which makes use of a one-dimensional x-ray detector to provide efficient measurement of a reciprocal space map which covers the full compositional range from AlN to GaN. Combining this with a suitable x-ray reflection with low strain sensitivity it is possible to accurately determine the Al fraction of the buffer layers independent of their relaxation state. © 2013 IOP Publishing Ltd.

Prospects of III-nitride optoelectronics grown on Si.

The use of III-nitride-based light-emitting diodes (LEDs) is now widespread in applications such as indicator lamps, display panels, backlighting for liquid-crystal display TVs and computer screens, traffic lights, etc. To meet the huge market demand and lower the manufacturing cost, the LED industry is moving fast from 2 inch to 4 inch and recently to 6 inch wafer sizes. Although Al2O3 (sapphire) and SiC remain the dominant substrate materials for the epitaxy of nitride LEDs, the use of large Si substrates attracts great interest because Si wafers are readily available in large diameters at low cost. In addition, such wafers are compatible with existing processing lines for 6 inch and larger wafers commonly used in the electronics industry. During the last decade, much exciting progress has been achieved in improving the performance of GaN-on-Si devices. In this contribution, the status and prospects of III-nitride optoelectronics grown on Si substrates are reviewed. The issues involved in the growth of GaN-based LED structures on Si and possible solutions are outlined, together with a brief introduction to some novel in situ and ex situ monitoring/characterization tools, which are especially useful for the growth of GaN-on-Si structures.

Low-cost high-efficiency GaN LED on large-area si substrate

The use of large size Si substrates for epitaxy of nitride light emitting diode (LED) structures has attracted great interest because Si wafers are readily available in large diameter at low cost. In addition, such wafers are compatible with existing processing lines for the 6-inch and larger wafer sizes commonly used in the electronics industry. With the development of various methods to avoid wafer cracking and reduce the defect density, the performance of GaN-based LED and electronic devices has been greatly improved. In this paper, we review our methods of growing crack-free InGaN-GaN multiple quantum well (MQW) LED structures of high crystalline quality on Si(111) substrates. The performance of processed LED devices and its dependence on the threading dislocation density were studied. Full wafer-level LED processing using a conventional 6-inch III-V processing line is also presented, demonstrating the great advantage of using large-size Si substrates for mass production of GaN LED devices.

800V lateral IGBT in bulk Si for low power compact SMPS applications

An 800V rated lateral IGBT for high frequency, low-cost off-line applications has been developed. The LIGBT features a new method of adjusting the bipolar gain, based on a floating N+ stripe in front of the P+ anode/drain region. The floating N+ layer enhances the carrier recombination at the anode/drain side of the drift region resulting in a very significant decrease in the turn-off speed and substantially lower overall losses. Switching speeds as low as 140ns at 25oC and 300ns at 125oC have been achieved with corresponding equivalent Rdson at 125oC below 90mω.cm2. A fully operational AC-DC converter using a controller with an integrated LIGBT+depletion mode MOSFET chip has been designed and qualified in plastic SOP8 packages and used in 5W, 65kHz SMPS applications. The device is fabricated in 0.6μm bulk silicon CMOS technology without any additional masking steps. © 2013 IEEE.

Characteristics and applications of InGaN micro-light emitting diodes on Si substrates

InGaN micro-light emitting diodes on Si substrates have been fabricated and characterized. Their abilities for micro-display, high modulation bandwidth of 270 MHz and data transmission rate of up to 400 Mbit/s have been demonstrated. © 2013 IEEE.