One step self-aligned multilayer patterning process for the fabrication of organic complementary circuits in combination with inkjet printing

Recent development of solution processable organic semiconductors delineates the emergence of a new generation of air-stable, high performance p- and n-type materials. This makes it indeed possible for printed organic complementary circuits (CMOS) to be used in real applications. The main technical bottleneck for organic CMOS to be adopted as the next generation organic integrated circuit is how to deposit and pattern both p- and n-type semiconductor materials with high resolutions at the same time. It represents a significant technical challenge, especially if it can be done for multiple layers without mask alignment. In this paper, we propose a one-step self-aligned fabrication process which allows the deposition and high resolution patterning of functional layers for both p- and n-channel thin film transistors (TFTs) simultaneously. All the dimensional information of the device components is featured on a single imprinting stamp, and the TFT-channel geometry, electrodes with different work functions, p- and n-type semiconductors and effective gate dimensions can all be accurately defined by one-step imprinting and the subsequent pattern transfer process. As an example, we have demonstrated an organic complementary inverter fabricated by 3D imprinting in combination with inkjet printing and the measured electrical characteristics have validated the feasibility of the novel technique. © 2012 Elsevier B.V. All rights reserved.

Highly efficient spin transport in epitaxial graphene on SiC

Spin information processing is a possible new paradigm for post-CMOS (complementary metal-oxide semiconductor) electronics and efficient spin propagation over long distances is fundamental to this vision. However, despite several decades of intense research, a suitable platform is still wanting. We report here on highly efficient spin transport in two-terminal polarizer/analyser devices based on high-mobility epitaxial graphene grown on silicon carbide. Taking advantage of high-impedance injecting/detecting tunnel junctions, we show spin transport efficiencies up to 75%, spin signals in the mega-ohm range and spin diffusion lengths exceeding 100μm. This enables spintronics in complex structures: devices and network architectures relying on spin information processing, well beyond present spintronics applications, can now be foreseen. © 2012 Macmillan Publishers Limited. All rights reserved.

Energy recycling from multigigahertz clocks using fully integrated switching converters

Large digital chips use a significant amount of energy to broadcast a low-skew, multigigahertz clock to millions of latches located throughout the chip. Every clock cycle, the large aggregate capacitance of the clock network is charged from the supply and then discharged to ground. Instead of wasting this stored energy, it is possible to recycle the energy by controlling its delivery to another part of the chip using an on-chip dc-dc converter. The clock driver and switching converter circuits share many compatible characteristics that allow them to be merged into a single design and fully integrated on-chip. Our buck converter prototype, manufactured in 90-nm CMOS, provides a proof-of-concept that clock network energy can be recycled to other parts of the chip, thus lowering overall energy consumption. It also confirms that monolithic multigigahertz switching converters utilizing zero-voltage switching can be implemented in deep-submicrometer CMOS. With multigigahertz operation, fully integrated inductors and capacitors use a small amount of chip area with low losses. Combining the clock driver with the power converter can share the large MOSFET drivers necessary as well as being energy and space efficient. We present an analysis of the losses which we confirm by experimentally comparing the merged circuit with a conventional clock driver. © 2012 IEEE.

Enhanced infra-red emission from sub-millimeter microelectromechanical systems micro hotplates via inkjet deposited carbon nanoparticles and fullerenes

In this paper, we demonstrate a micro-inkjet printing technique as a reproducible post-process for the deposition of carbon nanoparticles and fullerene adlayers onto fully CMOS compatible micro-electro-mechanical silicon-on-insulator infrared (IR) light sources to enhance their infrared emission. We show experimentally a significant increase in the infrared emission efficiency of the coated emitters. We numerically validate these findings with models suggesting a dominant performance increase for wavelengths <5.5 μm. Here, the bimodal size distribution in the diameter of the carbon nanoparticles, relative to the fullerenes, is an effective mediator towards topologically enhanced emittance of our miniaturised emitters. A 90% improvement in IR emission power density has been shown which we have rationalised with an increase in the mean thickness of the deposited carbon nanoparticle adlayer. © 2013 AIP Publishing LLC.

The inverse problem in magnetic force microscopy--inferring sample magnetization from MFM images.

Nanomagnetic structures have the potential to surpass silicon's scaling limitations both as elements in hybrid CMOS logic and as novel computational elements. Magnetic force microscopy (MFM) offers a convenient characterization technique for use in the design of such nanomagnetic structures. MFM measures the magnetic field and not the sample's magnetization. As such the question of the uniqueness of the relationship between an external magnetic field and a magnetization distribution is a relevant one. To study this problem we present a simple algorithm which searches for magnetization distributions consistent with an external magnetic field and solutions to the micromagnetic equations' qualitative features. The algorithm is not computationally intensive and is found to be effective for our test cases. On the basis of our results we propose a systematic approach for interpreting MFM measurements.

2.1 GHz MOS mixer linearisation approach for IIP2 enhancement using multiple factor compensation

An integrated downconversion CMOS mixer incorporating a comprehensive compensation scheme is presented which aims to minimise second-order intermodulation distortion (IMD2). Unlike previously reported IMD2 calibration schemes which tune only one nonlinear factor at a time, the presented solution allows simultaneous adjustment of several different factors thus achieving a better compensation. The mixer has been implemented in UMC 0.18 μm CMOS to verify the proposed scheme and for comparison with alternative compensation methods. Measurements show that the solution described can improve the input intercept point (IIP2) by over 20 dB while maintaining good amplification and noise performance. IMD2 calibration results are presented and show useful advantages over other approaches. To the best of the authors' knowledge, this scheme for IMD2 calibration has not been previously reported. © The Institution of Engineering and Technology 2013.

Nanoscale plasmonic memristor with optical readout functionality.

We experimentally demonstrate for the first time a nanoscale resistive random access memory (RRAM) electronic device integrated with a plasmonic waveguide providing the functionality of optical readout. The device fabrication is based on silicon on insulator CMOS compatible approach of local oxidation of silicon, which enables the realization of RRAM and low optical loss channel photonic waveguide at the same fabrication step. This plasmonic device operates at telecom wavelength of 1.55 μm and can be used to optically read the logic state of a memory by measuring two distinct levels of optical transmission. The experimental characterization of the device shows optical bistable behavior between these levels of transmission in addition to well-defined hysteresis. We attribute the changes in the optical transmission to the creation of a nanoscale absorbing and scattering metallic filament in the amorphous silicon layer, where the plasmonic mode resides.

Waveguide based compact silicon Schottky photodetector with enhanced responsivity in the telecom spectral band.

We experimentally demonstrate an on-chip compact and simple to fabricate silicon Schottky photodetector for telecom wavelengths operating on the basis of internal photoemission process. The device is realized using CMOS compatible approach of local-oxidation of silicon, which enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. The photodetector demonstrates enhanced internal responsivity of 12.5mA/W for operation wavelength of 1.55µm corresponding to an internal quantum efficiency of 1%, about two orders of magnitude higher than our previously demonstrated results [22]. We attribute this improved detection efficiency to the presence of surface roughness at the boundary between the materials forming the Schottky contact. The combination of enhanced quantum efficiency together with a simple fabrication process provides a promising platform for the realization of all silicon photodetectors and their integration with other nanophotonic and nanoplasmonic structures towards the construction of monolithic silicon opto-electronic circuitry on-chip.

On chip plasmonic enhanced silicon Schottky detector for telecom wavelengths

We demonstrate an integrated on-chip plasmonic enhanced Schottky detector for telecom wavelengths based on the internal photoemission process. This CMOS compatible device may serve as a promising alternative to the Si-Ge detectors. © 2012 OSA.

800V lateral IGBT in bulk Si for low power compact SMPS applications

An 800V rated lateral IGBT for high frequency, low-cost off-line applications has been developed. The LIGBT features a new method of adjusting the bipolar gain, based on a floating N+ stripe in front of the P+ anode/drain region. The floating N+ layer enhances the carrier recombination at the anode/drain side of the drift region resulting in a very significant decrease in the turn-off speed and substantially lower overall losses. Switching speeds as low as 140ns at 25oC and 300ns at 125oC have been achieved with corresponding equivalent Rdson at 125oC below 90mω.cm2. A fully operational AC-DC converter using a controller with an integrated LIGBT+depletion mode MOSFET chip has been designed and qualified in plastic SOP8 packages and used in 5W, 65kHz SMPS applications. The device is fabricated in 0.6μm bulk silicon CMOS technology without any additional masking steps. © 2013 IEEE.

On chip plasmonic enhanced silicon schottky detector for telecom wavelengths

We demonstrate an integrated on-chip plasmonic enhanced Schottky detector for telecom wavelengths based on the internal photoemission process. This CMOS compatible device may serve as a promising alternative to the Si-Ge detectors. © 2011 Optical Society of America.

In-Situ grown carbon nanotubes for enhanced CO2 detection in non-dispersive-infra-red system

Non-dispersive-infra-red (NDIR) sensors are believed to be one of the most selective and robust solutions for CO2 detection, though cost prohibits their broader integration. In this paper we propose a commercially viable silicon-on-insulator (SOI) complementary metal-oxide (CMOS) micro-electro-mechanical (MEMS) technology for an IR thermal emitter. For the first time, vertically aligned multi walled carbon nanotubes (VA-MWCNTs) are suggested as a possible coating for the enhancement of the emission intensity of the optical source of a NDIR system. VA-MWCNTs have been grown in situ by chemical vapour deposition (CVD) exclusively on the heater area. Optical microscopy, scanning electron microscopy and Raman spectroscopy have been used to verify the quality of the VA-MWCNTs growth. The CNT-coated emitter demonstrated an increased response to CO2 of approx. 60%. Furthermore, we show that the VA-MWCNTs are stable up to temperatures of 500°C for up to 100 hours. © 2013 IEEE.

Amorphous silicon thin film transistor biosensing system

Electronic systems are a very good platform for sensing biological signals for fast point-of-care diagnostics or threat detection. One of the solutions is the lab-on-a-chip integrated circuit (IC), which is low cost and high reliability, offering the possibility for label-free detection. In recent years, similar integrated biosensors based on the conventional complementary metal oxide semiconductor (CMOS) technology have been reported. However, post-fabrication processes are essential for all classes of CMOS biochips, requiring biocompatible electrode deposition and circuit encapsulation. In this work, we present an amorphous silicon (a-Si) thin film transistor (TFT) array based sensing approach, which greatly simplifies the fabrication procedures and even decreases the cost of the biosensor. The device contains several identical sensor pixels with amplifiers to boost the sensitivity. Ring oscillator and logic circuits are also integrated to achieve different measurement methodologies, including electro-analytical methods such as amperometric and cyclic voltammetric modes. The system also supports different operational modes. For example, depending on the required detection arrangement, a sample droplet could be placed on the sensing pads or the device could be immersed into the sample solution for real time in-situ measurement. The entire system is designed and fabricated using a low temperature TFT process that is compatible to plastic substrates. No additional processing is required prior to biological measurement. A Cr/Au double layer is used for the biological-electronic interface. The success of the TFT-based system used in this work will open new avenues for flexible label-free or low-cost disposable biosensors. © 2013 Materials Research Society.