High mobility N-channel and P-channel nanocrystalline silicon thin-film transistors

We report high hole and electron mobilities in nanocrystalline silicon (nc-Si:H) top-gate staggered thin-film transistors (TFTs) fabricated by direct plasma-enhanced chemical vapor deposition (PECVD) at 260°C. The n-channel nc-Si:H TFT with n+ nc-Si:H ohmic contacts shows a field-effect electron mobility (μnFE) of 130 cm2/Vs, which increases to 150 cm2/Vs with Cr-silicide contacts, along with a field-effect hole mobility (μhFE) of 25 cm2/Vs. To the best of our knowledge, the hole and electron mobilities reported here are the highest achieved to date using direct PECVD. © 2005 IEEE.

Performance prediction of graphene nanoribbon and carbon nanotube transistors

Carbon nanotubes (CNTs) and graphene nanoribbons (GNRs) field-effect transistor (FET) can be the basis for a quasi-one- dimensional (Q1D) transistor technology. Recent experiments show that the on-off ratio for GNR devices can be improved to level exploration of transistor action is justified. Here we use the tight-binding energy dipersion approximation, to assess the performance of semiconducting CNT and GNR is qualitatively in terms of drain current drive strength, bandgap and density of states for a specified device. By reducing the maximum conductance 4e2/h by half, we observed that our model has a particularly good fit with 50 nm channel single walled carbon nanotube (SWCNT) experimental data. Given the same bandgap, CNTs outperform GNRs due to valley degeneracy. Nevertheless, the variation of the device contacts will decide which transistor will exhibit better conductivity and thus higher ON currents. © 2011 American Institute of Physics.

Effect of gate dielectric scaling in nanometer scale vertical thin film transistors

A short channel vertical thin film transistor (VTFT) with 30 nm SiN x gate dielectric is reported for low voltage, high-resolution active matrix applications. The device demonstrates an ON/OFF current ratio as high as 10 9, leakage current in the fA range, and a sub-threshold slope steeper than 0.23 V/dec exhibiting a marked improvement with scaling of the gate dielectric thickness. © 2011 American Institute of Physics.

Soft-lithographic processed soluble micropatterns of reduced graphene oxide for wafer-scale thin film transistors and gas sensors

PDMS based imprinting is firstly developed for patterning of rGO on a large area. High quality stripe and square shaped rGO patterns are obtained and the electrical properties of the rGO film can be adjusted by the concentration of GO suspension. The arrays of rGO electronics are fabricated from the patterned film by a simple shadow mask method. Gas sensors, which are based on these rGO electronics, show high sensitivity and recyclable usage in sensing NH 3. © 2012 The Royal Society of Chemistry.

Metastability mechanisms in thin film transistors quantitatively resolved using post-stress relaxation of threshold voltage

A new approach is presented to resolve bias-induced metastability mechanisms in hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs). The post stress relaxation of threshold voltage (V(T)) was employed to quantitatively distinguish between the charge trapping process in gate dielectric and defect state creation in active layer of transistor. The kinetics of the charge de-trapping from the SiN traps is analytically modeled and a Gaussian distribution of gap states is extracted for the SiN. Indeed, the relaxation in V(T) is in good agreement with the theory underlying the kinetics of charge de-trapping from gate dielectric. For the TFTs used in this work, the charge trapping in the SiN gate dielectric is shown to be the dominant metastability mechanism even at bias stress levels as low as 10 V.

Comparative switching behaviour of silicon transistors and practical silicon carbide transistors

The motivation for our work is to identify a space for silicon carbide (SiC) devices in the silicon (Si) world. This paper presents a detailed experimental investigation of the switching behaviour of silicon and silicon carbide transistors (a JFET and a cascode device comprising a Si-MOSFET and a SiC-JFET). The experimental method is based on a clamped inductive load chopper circuit that puts considerable stress on the device and increases the transient power dissipation. A precise comparison of switching behaviour of Si and SiC devices on similar terms is the novelty of our work. The cascode is found to be an attractive fast switching device, capable of operating in two different configurations whose switching equivalent circuits are proposed here. The effect of limited dv/dt of the Si-MOSFET on the switching of the SiC-JFET in a cascode is also critically analysed.

Steady-state analytical model for the trench insulated gate bipolar transistor

A steady-state, physically-based analytical model for the Trench Insulated Gate Bipolar Transistor which accounts for a combined PIN diode - PNP transistor carrier dynamics is proposed. Previous models (i.e. PIN model and PNP transistor model) cannot account properly for the carrier dynamics in Trench IGBT since neither the PNP transistor nor the PIN diode effect can be neglected. An optimized Trench IGBT with a large ratio between the accumulation layer and the cell size leads to substantially improved on-state characteristics, which makes the Trench IGBT potentially the most attractive device in the area of high voltage fast switching devices.

Conduction bottleneck in silicon nanochain single electron transistors operating at room temperature

Single electron transistors are fabricated on single Si nanochains, synthesised by thermal evaporation of SiO solid sources. The nanochains consist of one-dimensional arrays of ~10nm Si nanocrystals, separated by SiO 2 regions. At 300 K, strong Coulomb staircases are seen in the drain-source current-voltage (I ds-V ds) characteristics, and single-electron oscillations are seen in the drain-source current-gate voltage (I ds-V ds) characteristics. From 300-20 K, a large increase in the Coulomb blockade region is observed. The characteristics are explained using singleelectron Monte Carlo simulation, where an inhomogeneous multiple tunnel junction represents a nanochain. Any reduction in capacitance at a nanocrystal well within the nanochain creates a conduction " bottleneck", suppressing current at low voltage and improving the Coulomb staircase. The single-electron charging energy at such an island can be very high, ~20k BT at 300 K. © 2012 The Japan Society of Applied Physics.