Dead-time minimisation using active voltage control gate drive for high-power IGBT converters

High-power converters usually need longer dead-times than their lower-power counterparts and a lower switching frequency. Also due to the complicated assembly layout and severe variations in parasitics, in practice the conventional dead-time specific adjustment or compensation for high-power converters is less effective, and usually this process is time-consuming and bespoke. For general applications, minimising or eliminating dead-time in the gate drive technology is a desirable solution. With the growing acceptance of power electronics building blocks (PEBB) and intelligent power modules (IPM), gate drives with intelligent functions are in demand. Smart functions including dead time elimination/minimisation can improve modularity, flexibility and reliability. In this paper, a dead-time minimisation using Active Voltage Control (AVC) gate drive is presented. © 2012 IEEE.

Low power consumption and high sensitivity carbon monoxide gas sensor using indium oxide nanowire.

In this paper, micro gas sensor was fabricated using indium oxide nanowire for effective gas detection and monitoring system. Indium oxide nanowire was grown using thermal CVD, and their structural properties were examined by the SEM, XRD and TEM. The electric properties for microdropped indium oxide nanowire device were measured, and gas response characteristics were examined for CO gas. Sensors showed high sensitivity and stability for CO gas. And with below 20 mw power consumption, 5 ppm CO could be detected.

Partial soi power LDMOS with a variable low-kappa; Dielectric buried layer and a buried P layer

A power LDMOS on partial silicon on insulator (PSOI) with a variable low-κ dielectric (VLKD) buried layer and a buried p (BP) layer is proposed (VLKD BPSOI). At a low κ value, the electric field strength in the buried dielectric (EI) is enhanced, and a Si window makes the substrate share the vertical voltage drop, leading to a high vertical breakdown voltage (BV). Moreover, three interface field peaks are introduced by the BP, the Si window, and the VLKD, which modulate the fields in the SOI layer, the VLKD layer, and the substrate; consequently, a high BV is obtained. Furthermore, the BP reduces the specific on-resistance (Ron), and the Si window alleviates the self-heating effect (SHE). The BV for VLKD BPSOI is enhanced by 34.5%, and Ron is decreased by 26.6%, compared with those for the conventional PSOI, and VLKD BPSOI also maintains a low SHE. © 2006 IEEE.

Relay node placement for wireless sensor networks deployed in tunnels

Node placement plays a significant role in the effective and successful deployment of Wireless Sensor Networks (WSNs), i.e., meeting design goals such as cost effectiveness, coverage, connectivity, lifetime and data latency. In this paper, we propose a new strategy to assist in the placement of Relay Nodes (RNs) for a WSN monitoring underground tunnel infrastructure. By applying for the first time an accurate empirical mean path loss propagation model along with a well fitted fading distribution model specifically defined for the tunnel environment, we address the RN placement problem with guaranteed levels of radio link performance. The simulation results show that the choice of appropriate path loss model and fading distribution model for a typical environment is vital in the determination of the number and the positions of RNs. Furthermore, we adapt a two-tier clustering multi-hop framework in which the first tier of the RN placement is modelled as the minimum set cover problem, and the second tier placement is solved using the search-and-find algorithm. The implementation of the proposed scheme is evaluated by simulation, and it lays the foundations for further work in WSN planning for underground tunnel applications. © 2010 IEEE.

Low-temperature (≤600 °C) semi-insulating oxygen-doped silicon films by the PECVD technique for large-area power applications

This work describes the deposition, annealing and characterisation of semi-insulating oxygen-doped silicon films at temperatures compatible with polysilicon circuitry on glass. The semi-insulating layers are deposited by the plasma enhanced chemical vapour deposition technique from silane (SiH4), nitrous oxide (N2O) and helium (He) gas mixtures at a temperature of 350 °C. The as-deposited films are then furnace annealed at 600 °C which is the maximum process temperature. Raman analysis shows the as-deposited and annealed films to be completely amorphous. The most important deposition variable is the N2O SiH4 gas ratio. By varying the N2O SiH4 ratio the conductivity of the annealed films can be accurately controlled, for the first time, down to a minimum of ≈10-7Ω-1cm-1 where they exhibit a T -1 4 temperature dependence indicative of a hopping conduction mechanism. Helium dilution of the reactant gases is shown to improve both film uniformity and reproducibility. A model for the microstructure of these semi-insulating amorphous oxygen-doped silicon films is proposed to explain the observed physical and electrical properties. © 1995.