Persistent photoconductivity in Hf-In-Zn-O thin film transistors

Passivated Hf-In-Zn-O (HIZO) thin film transistors suffer from a negative threshold voltage shift under visible light stress due to persistent photoconductivity (PPC). Ionization of oxygen vacancy sites is identified as the origin of the PPC following observations of its temperature- and wavelength-dependence. This is further corroborated by the photoluminescence spectrum of the HIZO. We also show that the gate voltage can control the decay of PPC in the dark, giving rise to a memory action. © 2010 American Institute of Physics.

Instability in threshold voltage and subthreshold behavior in Hf-In-Zn-O thin film transistors induced by bias-and light-stress

Electrical bias and light stressing followed by natural recovery of amorphous hafnium-indium-zinc-oxide (HIZO) thin film transistors with a silicon oxide/nitride dielectric stack reveals defect density changes, charge trapping and persistent photoconductivity (PPC). In the absence of light, the polarity of bias stress controls the magnitude and direction of the threshold voltage shift (Δ VT), while under light stress, VT consistently shifts negatively. In all cases, there was no significant change in field-effect mobility. Light stress gives rise to a PPC with wavelength-dependent recovery on time scale of days. We observe that the PPC becomes more pronounced at shorter wavelengths. © 2010 American Institute of Physics.

Advantages of top-gate, high-k dielectric carbon nanotube field-effect transistors

The subthreshold slope, transconductance, threshold voltage, and hysteresis of a carbon nanotube field-effect transistor (CNT FET) were examined as its configuration was changed from bottom-gate exposed channel, bottom-gate covered channel to top-gate FET. An individual single wall CNT was grown by chemical vapor deposition and its gate configuration was changed while determining its transistor characteristics to ensure that the measurements were not a function of different chirality or diameter CNTs. The bottom-gate exposed CNT FET utilized 900 nm SiO2 as the gate insulator. This CNT FET was then covered with TiO2 to form the bottom-gate covered channel CNT FET. Finally, the top-gate CNT FET was fabricated and the device utilized TiO 2 (K ∼ 80, equivalent oxide thickness=0.25 nm) as the gate insulator. Of the three configurations investigated, the top-gate device exhibited best subthreshold slope (67-70 mV/dec), highest transconductance (1.3 μS), and negligible hysteresis in terms of threshold voltage shift. © 2006 American Institute of Physics.