Computer generated hologram with geometric occlusion using GPU-accelerated depth buffer rasterization for three-dimensional display

We present a method of rapidly producing computer-generated holograms that exhibit geometric occlusion in the reconstructed image. Conceptually, a bundle of rays is shot from every hologram sample into the object volume.We use z buffering to find the nearest intersecting object point for every ray and add its complex field contribution to the corresponding hologram sample. Each hologram sample belongs to an independent operation, allowing us to exploit the parallel computing capability of modern programmable graphics processing units (GPUs). Unlike algorithms that use points or planar segments as the basis for constructing the hologram, our algorithm's complexity is dependent on fixed system parameters, such as the number of ray-casting operations, and can therefore handle complicated models more efficiently. The finite number of hologram pixels is, in effect, a windowing function, and from analyzing the Wigner distribution function of windowed free-space transfer function we find an upper limit on the cone angle of the ray bundle. Experimentally, we found that an angular sampling distance of 0:01' for a 2:66' cone angle produces acceptable reconstruction quality. © 2009 Optical Society of America.

Vertically oriented epitaxial germanium nanowires on silicon substrates using thin germanium buffer layers.

We demonstrate a method to realize vertically oriented Ge nanowires on Si(111) substrates. Ge nanowires were grown by chemical vapor deposition using Au nanoparticles to seed nanowire growth via a vapor-liquid-solid growth mechanism. Rapid oxidation of Si during Au nanoparticle application inhibits the growth of vertically oriented Ge nanowires directly on Si. The present method employs thin Ge buffer layers grown at low temperature less than 600 degrees C to circumvent the oxidation problem. By using a thin Ge buffer layer with root-mean-square roughness of approximately 2 nm, the yield of vertically oriented Ge nanowires is as high as 96.3%. This yield is comparable to that of homoepitaxial Ge nanowires. Furthermore, branched Ge nanowires could be successfully grown on these vertically oriented Ge nanowires by a secondary seeding technique. Since the buffer layers are grown under moderate conditions without any high temperature processing steps, this method has a wide process window highly suitable for Si-based microelectronics.

Off-wall boundary conditions for turbulent flows obtained from buffer-layer minimal flow units

There is strong evidence that the transport processes in the buffer region of wall-bounded turbulence are common across various flow configurations, even in the embryonic turbulence in transition (Park et al., Phys. Fl. 24). We use this premise to develop off-wall boundary conditions for turbulent simulations. Boundary conditions are constructed from DNS databases using periodic minimal flow units and reduced order modeling. The DNS data was taken from a channel at Reτ=400 and a zero-pressure gradient transitional boundary layer (Sayadi et al., submitted to J. Fluid Mech.). Both types of boundary conditions were first tested on a DNS of the core of the channel flow with the aim of extending their application to LES and to spatially evolving flows.

Effects of buffer layer properties and annealing process on bulk heterojunction morphology and organic solar cell performance

The performance of polymer-fullerene bulk heterojunction (BHJ) solar cells is strongly dependent on the vertical distribution of the donor and acceptor regions within the BHJ layer. In this work, we investigate in detail the effect of the hole transport layer (HTL) physical properties and the thermal annealing on the BHJ morphology and the solar cell performance. For this purpose, we have prepared solar cells with four distinct formulations of poly(3,4- ethylenedioxythiophene) poly(styrenesulfonate) (PEDOT:PSS) buffer layers. The samples were subjected to thermal annealing, applied either before (pre-annealing) or after (post-annealing) the cathode metal deposition. The effect of the HTL and the annealing process on the BHJ ingredient distribution - namely, poly(3-hexylthiophene) (P3HT) and [6,6]-phenyl C61 butyric acid methyl ester (PCBM) - has been studied by spectroscopic ellipsometry and atomic force microscopy. The results revealed P3HT segregation at the top region of the films, which had a detrimental effect on all pre-annealed devices, whereas PCBM was found to accumulate at the bottom interface. This demixing process depends on the PEDOT:PSS surface energy; the more hydrophilic the surface the more profound is the vertical phase separation within the BHJ. At the same time those samples suffer from high recombination losses as evident from the analysis of the J-V measurements obtained in the dark. Our results underline the significant effect of the HTL-active and active-ETL (electron transport layer) interfacial composition that should be taken into account during the optimization of all polymer-fullerene solar cells. © 2012 The Royal Society of Chemistry.

Performance of hybrid buffer Poly(3,4-ethylenedioxythiophene) poly(styrenesulfonate) layers doped with plasmonic silver nanoparticles

We compare the performance of a typical hole transport layer for organic photovoltaics (OPVs), Poly(3,4-ethylenedioxythiophene) poly(styrenesulfonate) (PEDOT:PSS) thin film with a series of PEDOT:PSS layers doped with silver (Ag) nanoparticles (NPs) of various size distributions. These hybrid layers have attracted great attention as buffer layers in plasmonic OPVs, although there is no report up to date on their isolated performance. In the present study we prepared a series of PEDOT:PSS layers sandwiched between indium tin oxide (ITO) and gold (Au) electrodes. Ag NPs were deposited on top of the ITO by electron beam evaporation followed by spin coating of PEDOT:PSS. Electrical characterization performed in the dark showed linear resistive behavior for all the samples; lower resistance was observed for the hybrid ones. It was found that the resistivity of the samples decreases with increasing the particle's size. A substantial increase of the electric field between the ITO and the Au electrodes was seen through the formation of current paths through the Ag NPs. A striking observation is the slight increase in the slope of the current density versus voltage curves when measured under illumination for the case of the plasmonic layers, indicating that changes in the electric field in the vicinity of the NP due to plasmonic excitation is a non-vanishing factor. © 2014 Published by Elsevier B.V. All rights reserved.

GaN-based LEDs grown on 6-inch diameter Si (111) substrates by MOVPE

The issues and challenges of growing GaN-based structures on large area Si substrates have been studied. These include Si slip resulting from large temperature non-uniformities and cracking due to differential thermal expansion. Using an A1N nucleation layer in conjunction with an AlGaN buffer layer for stress management, and together with the interactive use of real time in-situ optical monitoring it was possible to realise flat, crack-free and uniform GaN and LED structures on 6-inch Si (111) substrates. The EL performance of processed LED devices was also studied on-wafer, giving good EL characteristics including a forward bias voltage of ∼3.5 V at 20 mA from a 500 μm × 500 μm device. © 2009 SPIE.

InGaN/GaN LEDs grown on Si(111): Dependence of device performance on threading dislocation density and emission wavelength

We demonstrate the growth of crack-free blue and greenemitting LED structures grown on 2-inch and 6-inch Si(111) substrates by metalorganic vapour phase epitaxy (MOVPE), using AlN nucleation layers and AlGaN buffer layers for stress management. LED device performance and its dependence on threading dislocation (TD) density and emission wavelength were studied. Despite the inherently low light extraction efficiency, an output power of 1.2 mW at 50 mA was measured from a 500 μm square planar device, emitting at 455 nm. The light output decreases dramatically as the emission wavelength increases from 455 nm to 510 nm. For LED devices emitting at similar wavelength, the light output was more than doubled when the TD density was reduced from 5×1 09 cm-2 to 2×109 cm-2. Our results clearly show that high TD density is detrimental to the overall light output, highlighting the need for further TD reduction for structures grown on Si. © 2010 Wiley-VCH Verlag GmbH & Co. KGaA.

Carbon nanotube array: a new MIP platform.

Here we demonstrate that a free-standing carbon nanotube (CNT) array can be used as a large surface area and high porosity 3D platform for molecular imprinted polymer (MIP), especially for surface imprinting. The thickness of polymer grafted around each CNT can be fine-tuned to imprint different sizes of target molecules, and yet it can be thin enough to expose every imprint site to the target molecules in solution without sacrificing the capacity of binding sites. The performance of this new CNT-MIP architecture was first assessed with a caffeine-imprinted polypyrrole (PPy) coating on two types of CNT arrays: sparse and dense CNTs. Real-time pulsed amperometric detection was used to study the rebinding of the caffeine molecules onto these CNT-MIPPy sensors. The dense CNT-MIPPy sensor presented the highest sensitivity, about 15 times better when compared to the conventional thin film, whereas an improvement of 3.6 times was recorded on the sparse CNT. However, due to the small tube-to-tube spacing in the dense CNT array, electrode fouling was observed during the detection of concentrated caffeine in phosphate buffer solution. A new I-V characterization method using pulsed amperometry was introduced to investigate the electrical characterization of these new devices. The resistance value derived from the I-V plot provides insight into the electrical conductivity of the CNT transducer and also the effective surface area for caffeine imprinting.

Tunable electronic transport characteristics of surface-architecture-controlled ZnO nanowire field effect transistors.

Surface-architecture-controlled ZnO nanowires were grown using a vapor transport method on various ZnO buffer film coated c-plane sapphire substrates with or without Au catalysts. The ZnO nanowires that were grown showed two different types of geometric properties: corrugated ZnO nanowires having a relatively smaller diameter and a strong deep-level emission photoluminescence (PL) peak and smooth ZnO nanowires having a relatively larger diameter and a weak deep-level emission PL peak. The surface morphology and size-dependent tunable electronic transport properties of the ZnO nanowires were characterized using a nanowire field effect transistor (FET) device structure. The FETs made from smooth ZnO nanowires with a larger diameter exhibited negative threshold voltages, indicating n-channel depletion-mode behavior, whereas those made from corrugated ZnO nanowires with a smaller diameter had positive threshold voltages, indicating n-channel enhancement-mode behavior.

Theoretical and numerical investigation of SiC JFET and MOSFET at 6.5 kV

This paper presents a preliminary theoretical and numerical investigation of 4H-SiC JFET and MOSFET at 6.5 kV. To improve the on-state/breakdown performance of the JFET, buried layers in conjunction with a highly doped buffer layer have been used. Trench technology has been employed for the MOSFET. The devices were simulated and optimized using MEDICI[I] simulator. From the comparison between the two devices, it turns out that the JFET offers a better on-state/breakdown trade-off, while the trench MOSFET has the advantage of MOS-control.