6 resultados para adaptive conjoint analysis


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Presentado en el 13th WSEAS International Conference on Automatic Control, Modelling and Simulation, ACMOS'11

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Survival from out-of-hospital cardiac arrest depends largely on two factors: early cardiopulmonary resuscitation (CPR) and early defibrillation. CPR must be interrupted for a reliable automated rhythm analysis because chest compressions induce artifacts in the ECG. Unfortunately, interrupting CPR adversely affects survival. In the last twenty years, research has been focused on designing methods for analysis of ECG during chest compressions. Most approaches are based either on adaptive filters to remove the CPR artifact or on robust algorithms which directly diagnose the corrupted ECG. In general, all the methods report low specificity values when tested on short ECG segments, but how to evaluate the real impact on CPR delivery of continuous rhythm analysis during CPR is still unknown. Recently, researchers have proposed a new methodology to measure this impact. Moreover, new strategies for fast rhythm analysis during ventilation pauses or high-specificity algorithms have been reported. Our objective is to present a thorough review of the field as the starting point for these late developments and to underline the open questions and future lines of research to be explored in the following years.

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Singular Value Decomposition (SVD) is a key linear algebraic operation in many scientific and engineering applications. In particular, many computational intelligence systems rely on machine learning methods involving high dimensionality datasets that have to be fast processed for real-time adaptability. In this paper we describe a practical FPGA (Field Programmable Gate Array) implementation of a SVD processor for accelerating the solution of large LSE problems. The design approach has been comprehensive, from the algorithmic refinement to the numerical analysis to the customization for an efficient hardware realization. The processing scheme rests on an adaptive vector rotation evaluator for error regularization that enhances convergence speed with no penalty on the solution accuracy. The proposed architecture, which follows a data transfer scheme, is scalable and based on the interconnection of simple rotations units, which allows for a trade-off between occupied area and processing acceleration in the final implementation. This permits the SVD processor to be implemented both on low-cost and highend FPGAs, according to the final application requirements.

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xlix, 121 p.