Calpain-Mediated Processing of Adenylate Cyclase Toxin Generates a Cytosolic Soluble Catalytically Active N-Terminal Domain

Bordetella pertussis, the whooping cough pathogen, secretes several virulence factors among which adenylate cyclase toxin (ACT) is essential for establishment of the disease in the respiratory tract. ACT weakens host defenses by suppressing important bactericidal activities of the phagocytic cells. Up to now, it was believed that cell intoxication by ACT was a consequence of the accumulation of abnormally high levels of cAMP, generated exclusively beneath the host plasma membrane by the toxin N-terminal catalytic adenylate cyclase (AC) domain, upon its direct translocation across the lipid bilayer. Here we show that host calpain, a calcium-dependent Cys-protease, is activated into the phagocytes by a toxin-triggered calcium rise, resulting in the proteolytic cleavage of the toxin N-terminal domain that releases a catalytically active "soluble AC''. The calpain-mediated ACT processing allows trafficking of the "soluble AC'' domain into subcellular organella. At least two strategic advantages arise from this singular toxin cleavage, enhancing the specificity of action, and simultaneously preventing an indiscriminate activation of cAMP effectors throughout the cell. The present study provides novel insights into the toxin mechanism of action, as the calpain-mediated toxin processing would confer ACT the capacity for a space- and time-coordinated production of different cAMP "pools'', which would play different roles in the cell pathophysiology.

Adaptive Scalable SVD Unit for Fast Processing of Large LSE Problems

Singular Value Decomposition (SVD) is a key linear algebraic operation in many scientific and engineering applications. In particular, many computational intelligence systems rely on machine learning methods involving high dimensionality datasets that have to be fast processed for real-time adaptability. In this paper we describe a practical FPGA (Field Programmable Gate Array) implementation of a SVD processor for accelerating the solution of large LSE problems. The design approach has been comprehensive, from the algorithmic refinement to the numerical analysis to the customization for an efficient hardware realization. The processing scheme rests on an adaptive vector rotation evaluator for error regularization that enhances convergence speed with no penalty on the solution accuracy. The proposed architecture, which follows a data transfer scheme, is scalable and based on the interconnection of simple rotations units, which allows for a trade-off between occupied area and processing acceleration in the final implementation. This permits the SVD processor to be implemented both on low-cost and highend FPGAs, according to the final application requirements.