7 resultados para ADAPTIVE STABILIZATION

em Archivo Digital para la Docencia y la Investigación - Repositorio Institucional de la Universidad del País Vasco


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This paper investigates the local asymptotic stabilization of a very general class of instable autonomous nonlinear difference equations which are subject to perturbed dynamics which can have a different order than that of the nominal difference equation. In the general case, the controller consists of two combined parts, namely, the feedback nominal controller which stabilizes the nominal (i.e., perturbation-free) difference equation plus an incremental controller which completes the stabilization in the presence of perturbed or unmodeled dynamics in the uncontrolled difference equation. A stabilization variant consists of using a single controller to stabilize both the nominal difference equation and also the perturbed one under a small-type characterization of the perturbed dynamics. The study is based on Banach fixed point principle, and it is also valid with slight modification for the stabilization of unstable oscillatory solutions.

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Presentado en el 13th WSEAS International Conference on Automatic Control, Modelling and Simulation, ACMOS'11

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Singular Value Decomposition (SVD) is a key linear algebraic operation in many scientific and engineering applications. In particular, many computational intelligence systems rely on machine learning methods involving high dimensionality datasets that have to be fast processed for real-time adaptability. In this paper we describe a practical FPGA (Field Programmable Gate Array) implementation of a SVD processor for accelerating the solution of large LSE problems. The design approach has been comprehensive, from the algorithmic refinement to the numerical analysis to the customization for an efficient hardware realization. The processing scheme rests on an adaptive vector rotation evaluator for error regularization that enhances convergence speed with no penalty on the solution accuracy. The proposed architecture, which follows a data transfer scheme, is scalable and based on the interconnection of simple rotations units, which allows for a trade-off between occupied area and processing acceleration in the final implementation. This permits the SVD processor to be implemented both on low-cost and highend FPGAs, according to the final application requirements.

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xlix, 121 p.