Selectively filled photonic liquid crystal fibers = Fibras de cristal fotónico selectivamente llenas con cristal líquido

El presente trabajo de Tesis se ha centrado en el diseño, fabricación y caracterización de dispositivos basados en fibras de cristal fotónico infiltrado selectivamente con cristales líquidos, polímeros y una mezcla de ambos. Todos los dispositivos son sintonizables, y su área de aplicación se centra en comunicaciones ópticas y sensores. La manipulación y fusionado de fibras fotónicas, el llenado selectivo de determinadas cavidades y la alineación recíproca de fibras mantenedoras de polarización son tareas muy específicas y delicadas para las que se requieren protocolos muy estrictos. Previo a la fabricación de dispositivos ha sido necesaria por tanto una tarea de sistematización y creación de protocolos de fabricación. Una vez establecidos se ha procedido a la fabricación y caracterización de dispositivos. Los dispositivos fabricados se enumeran a continuación para posteriormente detallar una a una las singularidades de cada uno. • Interferómetros intermodales hechos a partir de una porción de fibra fotónica soldada entre dos fibras estándar, bien monomodo o PANDA (mantenedora de polarización). Estos interferómetros han sido sumergidos o bien llenados selectivamente con cristales líquidos para así sintonizar la señal interferométrica guiada a través de la fibra. • Infiltración de fibras fotónicas con cristales líquidos colestéricos con especial énfasis en la fase azul (blue phase) de estos materiales. Las moléculas de cristal líquido se autoalinean en volumen por lo que la infiltración de fibras fotónicas con estos cristales líquidos es muy interesante, pues es conocida la dificultad de alinear apropiadamente cristales líquidos dentro de cavidades micrométricas de las fibras fotónicas. • Grabación de redes holográficas de forma selectiva en las cavidades de una fibra fotónica. Estas redes holográficas, llamadas POLICRYPS (POlymer-LIquid CRYstal-Polymer Slices), son redes fabricadas a base de franjas de polímero y cristal líquido alineado perpendicularmente a dichas franjas. Las franjas son a su vez perpendiculares al eje de la fibra como lo puede ser una red de Bragg convencional. El cristal líquido, al estar alineado perpendicularmente a dichos franjas y paralelo al eje de la fibra, se puede conmutar aplicando un campo eléctrico externo, modificando así el índice efectivo de la red. Se puede fabricar por lo tanto una red de Bragg sintonizable en fibra, muy útil en comunicaciones ópticas. • Llenado selectivo de fibras fotónicas con polidimetilsiloxano (PDMS), un polímero de tipo silicona. Si se realiza un llenado selectivo asimétrico se puede inducir birrefringencia en la fibra. El índice de refracción del PDMS tiene una fuerte dependencia térmica, por lo que se puede sintonizar la birrefringencia de la fibra. • Estudio teórico de llenado selectivo de fibras fotónicas con PDMS dopado con nanopartículas de plata de 5, 40 y 80 nm. Estas nanopartículas poseen un pico de absorción en torno a los 450 nm debido a resonancias superficiales localizadas de plasmones (LSPR). La resonancia del plasmon tiene una fuerte dependencia con el índice de refracción del material colindante, y al ser éste PDMS, la variación de índice de refracción se ve amplificada, obteniendo una absorción sintonizable. Se ha propuesto la fabricación de polarizadores sintonizables usando esta técnica. Como ya se ha dicho, previamente a la fabricación ha sido necesaria la protocolización de diversos procedimientos de fabricación de alta complejidad, así como protocolizar el proceso de toma de medidas para optimizar los resultados. Los procedimientos que han requerido la formulación de protocolos específicos han sido los siguientes: • Llenado selectivo de cavidades en una fibra fotónica. Dichas fibras tienen generalmente un diámetro externo de 125 μm, y sus cavidades son de entre 5 y 10 μm de diámetro. Se han desarrollado tres técnicas diferentes para el llenado/bloqueado selectivo, pudiéndose combinar varios protocolos para la optimización del proceso. Las técnicas son las siguientes: o Llenado y bloqueado con un prepolímero. Dicho prepolímero, también llamado adhesivo óptico, está inicialmente en estado líquido y posee una cierta viscosidad. Las cavidades de la fibra fotónica que se desea llenar o bloquear poseen un diámetro diferente al resto, por lo que en el proceso de llenado aparecen dos frentes de llenado dependientes de su diámetro. A mayor diámetro, mayor velocidad de llenado. Polimerizando cuando existe dicha diferencia en los frentes se puede cortar por medio, obteniendo así una fibra parcialmente bloqueada. o Colapsamiento de las cavidades de menor diámetro mediante aplicación de calor. El calor producido por un arco voltaico de una soldadora de fibra estándar fusiona el material exterior de la fibra produciendo el colapsamiento de las cavidades de menor diámetro. En esta técnica también es necesaria una diferencia de diámetros en las cavidades de la fibra. o Bloqueo una a una de las cavidades de la fibra fotónica con adhesivo óptico. Este procedimiento es muy laborioso y requiere mucha precisión. Con este sistema se pueden bloquear las cavidades deseadas de una fibra sin importar su diámetro. • Alineación de una fuente de luz linealmente polarizada con una fibra mantenedora de polarización ya sea PANDA o fotónica. Así mismo también se han alineado entre sí fibras mantenedoras de polarización, para que sus ejes rápidos se fusionen paralelos y así el estado de polarización de la luz guiada se mantenga. • Sistematización de toma de medidas para caracterizar los interferómetros modales. Éstos son altamente sensibles a diversas variables por lo que el proceso de medida es complejo. Se deben aislar variables de forma estrictamente controlada. Aunque todos los dispositivos tienen en común el llenado selectivo de cavidades en una fibra fotónica cada dispositivo tiene sus peculiaridades, que van a ser explicadas a continuación. ABSTRACT The present Thesis has been centered in the design, fabrication and characterization of devices based on photonic crystal fibers selectively filled with liquid crystals, polymers and a mixture of both. All devices are tunable and their work field is optical communications and sensing The handling and splicing of photonic crystal fibers, the selective filling of their holes and the aligning of polarization maintaining fibers are very specific and delicate tasks for which very strict protocols are required. Before the fabrication of devices has therefore been necessary task systematization and creation of manufacturing protocols. Once established we have proceeded to the fabrication and characterization of devices. The fabricated devices are listed below and their peculiarities are detailed one by one: • Intermodal interferometers made with a portion of photonic crystal fiber spliced between two optical communication fiber pigtails, either single mode or PANDA (polarization-maintaining) fiber. These interferometers have been submerged or selectively filled with liquid crystals to tune the interferometric guided signal. • Infiltration of photonic fibers with cholesteric liquid crystals with special emphasis on their blue phase (blue phase). The liquid crystal molecules are self-aligning in volume so the infiltration of photonic fibers with these liquid crystals is very interesting. It is notoriously difficult to properly align liquid crystals within micron cavities such as photonic fibers. • Selectively recording of holographic gratings in the holes of photonic crystal fibers. These holographic gratings, called POLICRYPS (POlymer-LIquid CRYstal-Polymes Slices), are based on walls made of polymer and liquid crystal aligned perpendicular to them. These walls are perpendicular to the axis of the fiber as it can be a conventional Bragg grating. The liquid crystal is aligned perpendicular to the walls and parallel to the fiber axis, and can be switched by applying an external electric field and thus change the effective index of the grating. It is thus possible to manufacture a tunable Bragg grating fiber, useful in optical communications. •Asymmetrically selective filling of photonic crystal fibers with a silicone polymer like called polydimethylsiloxane (PDMS) to induce birefringence in the fiber. The refractive index of PDMS has temperature dependence, so that the birefringence of the fiber can be tuned. • Theoretical study of photonic crystal fibers selectively filled with PDMS doped with silver nanoparticles of 5, 40 and 80 nm. These nanoparticles have an absorption peak around 450 nm due to localized surface plasmon resonances (LSPR). Plasmon resonance has a strong dependence on the refractive index of the adjacent material, and as this is PDMS, the refractive index variation is amplified, obtaining a tunable absorption. Fabrication of tunable polarizers using this technique has been proposed. Before starting the fabrication, it has been necessary to optimize several very delicate procedures and different protocols have been designed. The most delicate procedures are as follows: • Selective filling of holes in a photonic crystal fiber. These fibers generally have an outer diameter of 125 μm, and their holes have a diameter around between 5 and 10 μm. It has been developed three different techniques for filling / selective blocking, and they can be combined for process optimization. The techniques are: o Filling and blocked with a prepolymer. This prepolymer also called optical adhesive is initially in liquid state and has a certain viscosity. The holes of the photonic crystal fiber that are desired to be filled or blocked should have a different diameter, so that in the filling process appear two different fronts depending on the hole diameter. The holes with larger diameter are filled faster. Then the adhesive is polymerized when there is such a difference on the front. A partially blocked fiber is obtained cutting between fronts. o Collapsing of holes of smaller diameter by application of heat. The heat produced by an arc of a standard fusion splicer fuses the outer fiber material producing the collapsing of the cavities of smaller diameter. In this technique also you need a difference of diameters in the fiber holes. o Blocking one by one the holes of photonic crystal fiber with optical adhesive. This procedure is very laborious and requires great precision. This system can block unwanted cavities regardless fiber diameter. • Aligning a linearly polarized light source with a polarization-maintaining fiber (either a PANDA fiber as a photonic crystal fiber). It is needed also an aligning between polarization-maintaining fibers, so that their fast axes parallel merge and that is state of polarization of light guided is maintained. • Systematization of taking measurements to characterize the modal interferometers. These are highly sensitive to several variables so the measurement process is very complicated. Variables must be fixed in a very controlled manner. Although all devices have the common characteristic of being selectively filled PCFs with some kind of material, each one has his own peculiarities, which are explained below.

A methodology to analyze, design and implement very fast and robust controls of Buck-type converters

La electrónica digital moderna presenta un desafío a los diseñadores de sistemas de potencia. El creciente alto rendimiento de microprocesadores, FPGAs y ASICs necesitan sistemas de alimentación que cumplan con requirimientos dinámicos y estáticos muy estrictos. Específicamente, estas alimentaciones son convertidores DC-DC de baja tensión y alta corriente que necesitan ser diseñados para tener un pequeño rizado de tensión y una pequeña desviación de tensión de salida bajo transitorios de carga de una alta pendiente. Además, dependiendo de la aplicación, se necesita cumplir con otros requerimientos tal y como proveer a la carga con ”Escalado dinámico de tensión”, donde el convertidor necesitar cambiar su tensión de salida tan rápidamente posible sin sobreoscilaciones, o ”Posicionado Adaptativo de la Tensión” donde la tensión de salida se reduce ligeramente cuanto más grande sea la potencia de salida. Por supuesto, desde el punto de vista de la industria, las figuras de mérito de estos convertidores son el coste, la eficiencia y el tamaño/peso. Idealmente, la industria necesita un convertidor que es más barato, más eficiente, más pequeño y que aún así cumpla con los requerimienos dinámicos de la aplicación. En este contexto, varios enfoques para mejorar la figuras de mérito de estos convertidores se han seguido por la industria y la academia tales como mejorar la topología del convertidor, mejorar la tecnología de semiconducores y mejorar el control. En efecto, el control es una parte fundamental en estas aplicaciones ya que un control muy rápido hace que sea más fácil que una determinada topología cumpla con los estrictos requerimientos dinámicos y, consecuentemente, le da al diseñador un margen de libertar más amplio para mejorar el coste, la eficiencia y/o el tamaño del sistema de potencia. En esta tesis, se investiga cómo diseñar e implementar controles muy rápidos para el convertidor tipo Buck. En esta tesis se demuestra que medir la tensión de salida es todo lo que se necesita para lograr una respuesta casi óptima y se propone una guía de diseño unificada para controles que sólo miden la tensión de salida Luego, para asegurar robustez en controles muy rápidos, se proponen un modelado y un análisis de estabilidad muy precisos de convertidores DC-DC que tienen en cuenta circuitería para sensado y elementos parásitos críticos. También, usando este modelado, se propone una algoritmo de optimización que tiene en cuenta las tolerancias de los componentes y sensados distorsionados. Us ando este algoritmo, se comparan controles muy rápidos del estado del arte y su capacidad para lograr una rápida respuesta dinámica se posiciona según el condensador de salida utilizado. Además, se propone una técnica para mejorar la respuesta dinámica de los controladores. Todas las propuestas se han corroborado por extensas simulaciones y prototipos experimentales. Con todo, esta tesis sirve como una metodología para ingenieros para diseñar e implementar controles rápidos y robustos de convertidores tipo Buck. ABSTRACT Modern digital electronics present a challenge to designers of power systems. The increasingly high-performance of microprocessors, FPGAs (Field Programmable Gate Array) and ASICs (Application-Specific Integrated Circuit) require power supplies to comply with very demanding static and dynamic requirements. Specifically, these power supplies are low-voltage/high-current DC-DC converters that need to be designed to exhibit low voltage ripple and low voltage deviation under high slew-rate load transients. Additionally, depending on the application, other requirements need to be met such as to provide to the load ”Dynamic Voltage Scaling” (DVS), where the converter needs to change the output voltage as fast as possible without underdamping, or ”Adaptive Voltage Positioning” (AVP) where the output voltage is slightly reduced the greater the output power. Of course, from the point of view of the industry, the figures of merit of these converters are the cost, efficiency and size/weight. Ideally, the industry needs a converter that is cheaper, more efficient, smaller and that can still meet the dynamic requirements of the application. In this context, several approaches to improve the figures of merit of these power supplies are followed in the industry and academia such as improving the topology of the converter, improving the semiconductor technology and improving the control. Indeed, the control is a fundamental part in these applications as a very fast control makes it easier for the topology to comply with the strict dynamic requirements and, consequently, gives the designer a larger margin of freedom to improve the cost, efficiency and/or size of the power supply. In this thesis, how to design and implement very fast controls for the Buck converter is investigated. This thesis proves that sensing the output voltage is all that is needed to achieve an almost time-optimal response and a unified design guideline for controls that only sense the output voltage is proposed. Then, in order to assure robustness in very fast controls, a very accurate modeling and stability analysis of DC-DC converters is proposed that takes into account sensing networks and critical parasitic elements. Also, using this modeling approach, an optimization algorithm that takes into account tolerances of components and distorted measurements is proposed. With the use of the algorithm, very fast analog controls of the state-of-the-art are compared and their capabilities to achieve a fast dynamic response are positioned de pending on the output capacitor. Additionally, a technique to improve the dynamic response of controllers is also proposed. All the proposals are corroborated by extensive simulations and experimental prototypes. Overall, this thesis serves as a methodology for engineers to design and implement fast and robust controls for Buck-type converters.

Numerical simulation of the upward propagation of a flame in a vertical tube filled with a very lean mixture.

Upwardpropagation of a premixed flame in averticaltubefilled with a very leanmixture is simulated numerically using a single irreversible Arrhenius reaction model with infinitely high activation energy. In the absence of heat losses and preferential diffusion effects, a curved flame with stationary shape and velocity close to those of an open bubble ascending in the same tube is found for values of the fuel mass fraction above a certain minimum that increases with the radius of the tube, while the numerical computations cease to converge to a stationary solution below this minimum mass fraction. The vortical flow of the gas behind the flame and in its transport region is described for tubes of different radii. It is argued that this flow may become unstable when the fuel mass fraction is decreased, and that this instability, together with the flame stretch due to the strong curvature of the flame tip in narrow tubes, may be responsible for the minimum fuel mass fraction. Radiation losses and a Lewis number of the fuel slightly above unity decrease the final combustion temperature at the flame tip and increase the minimum fuel mass fraction, while a Lewis number slightly below unity has the opposite effect.

Influence of local wind speed and direction on wind power dynamics - Application to offshore very short-term forecasting

Wind power time series usually show complex dynamics mainly due to non-linearities related to the wind physics and the power transformation process in wind farms. This article provides an approach to the incorporation of observed local variables (wind speed and direction) to model some of these effects by means of statistical models. To this end, a benchmarking between two different families of varying-coefficient models (regime-switching and conditional parametric models) is carried out. The case of the offshore wind farm of Horns Rev in Denmark has been considered. The analysis is focused on one-step ahead forecasting and a time series resolution of 10 min. It has been found that the local wind direction contributes to model some features of the prevailing winds, such as the impact of the wind direction on the wind variability, whereas the non-linearities related to the power transformation process can be introduced by considering the local wind speed. In both cases, conditional parametric models showed a better performance than the one achieved by the regime-switching strategy. The results attained reinforce the idea that each explanatory variable allows the modelling of different underlying effects in the dynamics of wind power time series.

Strict and non-strict independent and-parallelism in logic programs: Correctness, efficiency, and compile-time conditions.

This paper presents some fundamental properties of independent and-parallelism and extends its applicability by enlarging the class of goals eligible for parallel execution. A simple model of (independent) and-parallel execution is proposed and issues of correctness and efficiency discussed in the light of this model. Two conditions, "strict" and "non-strict" independence, are defined and then proved sufficient to ensure correctness and efñciency of parallel execution: if goals which meet these conditions are executed in parallel the solutions obtained are the same as those produced by standard sequential execution. Also, in absence of failure, the parallel proof procedure does not genérate any additional work (with respect to standard SLD-resolution) while the actual execution time is reduced. Finally, in case of failure of any of the goals no slow down will occur. For strict independence the results are shown to hold independently of whether the parallel goals execute in the same environment or in sepárate environments. In addition, a formal basis is given for the automatic compile-time generation of independent and-parallelism: compile-time conditions to efficiently check goal independence at run-time are proposed and proved sufficient. Also, rules are given for constructing simpler conditions if information regarding the binding context of the goals to be executed in parallel is available to the compiler.

Consciousness, Action Selection, Meaning and Phenomenic Anticipation

Phenomenal states are generally considered the ultimate sources of intrinsic motivation for autonomous biological agents. In this article, we will address the issue of the necessity of exploiting these states for the design and implementation of robust goal-directed artificial systems. We will provide an analysis of consciousness in terms of a precise definition of how an agent "understands" the informational flows entering the agent and its very own action possibilities. This abstract model of consciousness and understanding will be based in the analysis and evaluation of phenomenal states along potential future trajectories in the state space of the agents. This implies that a potential strategy to follow in order to build autonomous but still customer-useful systems is to embed them with the particular, ad hoc phenomenality that captures the system-external requirements that define the system usefulness from a customer-based, requirements-strict engineering viewpoint.

Effectiveness of global analysis in strict independence-based automatic program parallelization

This paper presents a study of the effectiveness of global analysis in the parallelization of logic programs using strict independence. A number of well-known approximation domains are selected and tlieir usefulness for the application in hand is explained. Also, methods for using the information provided by such domains to improve parallelization are proposed. Local and global analyses are built using these domains and such analyses are embedded in a complete parallelizing compiler. Then, the performance of the domains (and the system in general) is assessed for this application through a number of experiments. We argüe that the results offer significant insight into the characteristics of these domains, the demands of the application, and the tradeoffs involved.

Extracting non-strict independent and-parallelism using sharing and freeness information

Logic programming systems which exploit and-parallelism among non-deterministic goals rely on notions of independence among those goals in order to ensure certain efficiency properties. "Non-strict" independence (NSI) is a more relaxed notion than the traditional notion of "strict" independence (SI) which still ensures the relevant efficiency properties and can allow considerable more parallelism than SI. However, all compilation technology developed to date has been based on SI, because of the intrinsic complexity of exploiting NSI. This is related to the fact that NSI cannot be determined "a priori" as SI. This paper filis this gap by developing a technique for compile-time detection and annotation of NSI. It also proposes algorithms for combined compiletime/ run-time detection, presenting novel run-time checks for this type of parallelism. Also, a transformation procedure to eliminate shared variables among parallel goals is presented, aimed at performing as much work as possible at compile-time. The approach is based on the knowledge of certain properties regarding the run-time instantiations of program variables —sharing and freeness— for which compile-time technology is available, with new approaches being currently proposed. Thus, the paper does not deal with the analysis itself, but rather with how the analysis results can be used to parallelize programs.

Non-strict independent and-parallelism

This paper presents and develops a generalized concept of Non-Strict Independent And Parallelism (NSIAP). NSIAP extends the applicability of Independent And- Parallelism (IAP) by enlarging the class of goals which are eligible for parallel execution. At the same time it maintains IAP's ability to run non-deterministic goals in parallel and to preserve the computational complexity expected in the execution of the program by the programmer. First, a parallel execution framework is defined and some fundamental correctness results, in the sense of equivalence of solutions with the sequential model, are discussed for this framework. The issue of efficiency is then considered. Two new definitions of NSI are given for the cases of puré and impure goals respectively and efficiency results are provided for programs parallelized under these definitions which include treatment of the case of goal failure: not only is reduction of execution time guaranteed (modulo run-time overheads) in the absence of failure but it is also shown that in the worst case of failure no speed-down will occur. In addition to applying to NSI, these results carry over and complete previous results shown in the context of IAP which did not deal with the case of goal failure. Finally, some practical examples of the application of the NSIAP concept to the parallelization of a set of programs are presented and performance results, showing the advantage of using NSI, are given.

Some issues in analysis and specialization of modular ciao-prolog programs

Separating programs into modules is a well-known technique which has proven very useful in program development and maintenance. Starting by introducing a number of possible scenarios, in this paper we study different issues which appear when developing analysis and specialization techniques for modular logic programming. We discuss a number of design alternatives and their consequences for the different scenarios considered and describe where applicable the decisions made in the Ciao system analyzer and specializer. In our discussion we use the module system of Ciao Prolog. This is both for concreteness and because Ciao Prolog is a second-generation Prolog system which has been designed with global analysis and specialization in mind, and which has a strict module system. The aim of this work is not to provide a theoretical basis on modular analysis and specialization, but rather to discuss some interesting practical issues.

Towards extracting non-strict independent and-parallelism using sharing and freeness information

Logic programming systems which exploit and-parallelism among non-deterministic goals rely on notions of independence among those goals in order to ensure certain efficiency properties. "Non-strict" independence (NSI) is a more relaxed notion than the traditional notion of "strict" independence (SI) which still ensures the relevant efficiency properties and can allow considerable more parallelism than SI. However, all compilation technology developed to date has been based on SI, presumably because of the intrinsic complexity of exploiting NSI. This is related to the fact that NSI cannot be determined "a priori" as SI. This paper fills this gap by developing a technique for compile-time detection and annotation of NSI. It also proposes algorithms for combined compile- time/run-time detection, presenting novel run-time checks for this type of parallelism. Also, a transformation procedure to eliminate shared variables among parallel goals is presented, attempting to perform as much work as possible at compiletime. The approach is based on the knowledge of certain properties about run-time instantiations of program variables —sharing and freeness— for which compile-time technology is available, with new approaches being currently proposed.

La arquitectura de Curro Inza : una aproximación crítica y proyectual

El arquitecto Curro Inza (1929-1976) pertenece al grupo que se ha denominado como organicismo madrileño y Escuela de Madrid, cuyas máximas realizaciones se produjeron durante los años sesenta del pasado siglo. Hasta ahora su obra y persona han generado opiniones bien extremas, pero apenas han sido investigadas, cuando en realidad su arquitectura trata asuntos que hoy se muestran de actual interés. El estudio que aquí se presenta tiene un doble objetivo. El primero es agrupar la información arquitectónica del autor y catalogar las obras de su archivo personal (inédito hasta ahora). Se ordena, clasifica y cataloga toda la documentación arquitectónica del archivo Inza, dejándose depositada en la Biblioteca de la ETSAM, quedando disponible y facilitando posteriores investigaciones sobre este arquitecto. Se procede asimismo a la digitalizaran de los proyectos principales garantizando su optima conservación para el futuro Una vez logrado el primer objetivo, el segundo consiste en realizar un análisis proyectual y critico de su obra, un punto de vista hasta ahora apenas abordado. Me propongo profundizar en una obra definida como compleja pero poco explicada, realizando una revisión crítica de sus escritos y de sus proyectos, y relacionando esta con otras arquitecturas (nacionales e internacionales) que sitúen al autor dentro del discurso contemporáneo. Para desentrañar las claves de su arquitectura se aborda el trabajo de Inza desde cinco miradas distintas y simultaneas. Desde cada una de estas miradas o categorías) se hace una aproximación crítica recorriendo los proyectos. Unas categorías que, a la postre, conforman el índice de este trabajo. Aunque la compilación y revisión del archivo posee algo de búsqueda arqueológica, el estudio no pretende tener un interés únicamente o intrínsecamente histórico. El trabajo tiene en realidad como fin estudiar la forma de proyectar de un arquitecto hasta ahora poco referencial y que entiendo, puede hoy establecer puentes con el presente y el futuro a través de su arquitectura. Intentar entender los mecanismos que arman esta arquitectura, sus orígenes, su evolución y la construcción de su lenguaje. En resumen, explicar y analizar la obra desde un punto de vista proyectual haciendo una lectura critica que desentrañe estrategias de las que hoy pudiéramos aprender y nos resultasen operativas.ABSTRACT: The architect Curro Inza (1929-1976) belongs to the group known as Madrilian organicism and the School of Madrid, whose most important works were built during the 1960 and 1970 decades. Curro Inza's work has received up until now very different, even extreme opinions, but his work has not been studied in depth, which is surprising if we consider that his architecture treats issues which are of great interest today. The present study has aimed at two objectives. The first has been to gather the information concerned with the author and his work, and to catalog all of the works of this personal archive (unpublished up until now). The work we have done here has consisted in compiling, digitalizing, classifying and cataloguing all of the documentation found in Curro Inza's personal archive; this archive has been deposited in the Biblioteca de la Escuela Superior de Artquitectura de Madrid (ETSAM) . We have also digitalized the main projects in order to assure the best storage conditions for the future. The second objective has consisted in analyzing Curro Inza's work from a project and critical point of view, an approach which has not yet been explored. Within this second objective, I have studied Inza's work, which is well defined and personal as well as complex, but which has received little attention and has not been explained. I have done a critical revision of both his projects and his writings, and have related these with other, both national and international, architectures, in order to place Inza's work within the contemporary architectural discourse. In order to decipher the essence of Inza's architecture, I have approached his work from five, simultaneous perspectives. I have described the projects critically from each of the five perspectives or categories; these five categories give shape to the organization of the dissertation. Even if the compilation and revision of Inza's archive is somehow an archaeological search, this study aims at having a larger scope than its strict, exclusive historical interest. In this study I have studied Inza's projects from a critical point of view and in relation to contemporary architecture and architectural thought, attempting to draw connections between Inza's work and modern, present architecture. We have also attempted to understand and describe Inza's language and conception of architectural discourse, as well as his origins, evolution and expression of his thought. In summary, I have analyzed and explained Curro Inza's work from a projectual point of view, drawing a critical reading of the strategies used by the author, and from which we could learn and work today.

Comparison of V2IC control with voltage mode and current mode controls for high frequency (MHz) and very fast response applications

High switching frequencies (several MHz) allow the integration of low power DC/DC converters. Although, in theory, a high switching frequency would make possible to implement a conventional Voltage Mode control (VMC) or Peak Current Mode control (PCMC) with very high bandwidth, in practice, parasitic effects and robustness limits the applicability of these control techniques. This paper compares VMC and CMC techniques with the V2IC control. This control is based on two loops. The fast internal loop has information of the output capacitor current and the error voltage, providing fast dynamic response under load and voltage reference steps, while the slow external voltage loop provides accurate steady state regulation. This paper shows the fast dynamic response of the V2IC control under load and output voltage reference steps and its robustness operating with additional output capacitors added by the customer.

Monte Carlo simulation on a system of hard cylinders at a very high packing fraction

Using the Monte Carlo method the behavior of a system of true hard cylinders has been studied. Values of the length-to-breadth ratio L/D and packing fraction η have been chosen similar to those of real nematic liquid crystals. Results include radial distribution function g(r), structure factor S(k), and orientational order parameter M. These results lead to the conclusion that the hard cylinder model may be a useful reference for real mesomorphic phases.

Design and Validation of an Optimized MB-OFDM Ultra Wideband Transceiver System

Esta tesis está incluida dentro del campo del campo de Multiband Orthogonal Frequency Division Multiplexing Ultra Wideband (MB-OFDM UWB), el cual ha adquirido una gran importancia en las comunicaciones inalámbricas de alta tasa de datos en la última década. UWB surgió con el objetivo de satisfacer la creciente demanda de conexiones inalámbricas en interiores y de uso doméstico, con bajo coste y alta velocidad. La disponibilidad de un ancho de banda grande, el potencial para alta velocidad de transmisión, baja complejidad y bajo consumo de energía, unido al bajo coste de implementación, representa una oportunidad única para que UWB se convierta en una solución ampliamente utilizada en aplicaciones de Wireless Personal Area Network (WPAN). UWB está definido como cualquier transmisión que ocupa un ancho de banda de más de 20% de su frecuencia central, o más de 500 MHz. En 2002, la Comisión Federal de Comunicaciones (FCC) definió que el rango de frecuencias de transmisión de UWB legal es de 3.1 a 10.6 GHz, con una energía de transmisión de -41.3 dBm/Hz. Bajo las directrices de FCC, el uso de la tecnología UWB puede aportar una enorme capacidad en las comunicaciones de corto alcance. Considerando las ecuaciones de capacidad de Shannon, incrementar la capacidad del canal requiere un incremento lineal en el ancho de banda, mientras que un aumento similar de la capacidad de canal requiere un aumento exponencial en la energía de transmisión. En los últimos años, s diferentes desarrollos del UWB han sido extensamente estudiados en diferentes áreas, entre los cuales, el protocolo de comunicaciones inalámbricas MB-OFDM UWB está considerado como la mejor elección y ha sido adoptado como estándar ISO/IEC para los WPANs. Combinando la modulación OFDM y la transmisión de datos utilizando las técnicas de salto de frecuencia, el sistema MB-OFDM UWB es capaz de soportar tasas de datos con que pueden variar de los 55 a los 480 Mbps, alcanzando una distancia máxima de hasta 10 metros. Se esperara que la tecnología MB-OFDM tenga un consumo energético muy bajo copando un are muy reducida en silicio, proporcionando soluciones de bajo coste que satisfagan las demandas del mercado. Para cumplir con todas estas expectativas, el desarrollo y la investigación del MBOFDM UWB deben enfrentarse a varios retos, como son la sincronización de alta sensibilidad, las restricciones de baja complejidad, las estrictas limitaciones energéticas, la escalabilidad y la flexibilidad. Tales retos requieren un procesamiento digital de la señal de última generación, capaz de desarrollar sistemas que puedan aprovechar por completo las ventajas del espectro UWB y proporcionar futuras aplicaciones inalámbricas en interiores. Esta tesis se centra en la completa optimización de un sistema de transceptor de banda base MB-OFDM UWB digital, cuyo objetivo es investigar y diseñar un subsistema de comunicación inalámbrica para la aplicación de las Redes de Sensores Inalámbricas Visuales. La complejidad inherente de los procesadores FFT/IFFT y el sistema de sincronización así como la alta frecuencia de operación para todos los elementos de procesamiento, se convierten en el cuello de la botella para el diseño y la implementación del sistema de UWB digital en base de banda basado en MB-OFDM de baja energía. El objetivo del transceptor propuesto es conseguir baja energía y baja complejidad bajo la premisa de un alto rendimiento. Las optimizaciones están realizadas tanto a nivel algorítmico como a nivel arquitectural para todos los elementos del sistema. Una arquitectura hardware eficiente en consumo se propone en primer lugar para aquellos módulos correspondientes a núcleos de computación. Para el procesado de la Transformada Rápida de Fourier (FFT/IFFT), se propone un algoritmo mixed-radix, basado en una arquitectura con pipeline y se ha desarrollado un módulo de Decodificador de Viterbi (VD) equilibrado en coste-velocidad con el objetivo de reducir el consumo energético e incrementar la velocidad de procesamiento. También se ha implementado un correlador signo-bit simple basado en la sincronización del tiempo de símbolo es presentado. Este correlador es usado para detectar y sincronizar los paquetes de OFDM de forma robusta y precisa. Para el desarrollo de los subsitemas de procesamiento y realizar la integración del sistema completo se han empleado tecnologías de última generación. El dispositivo utilizado para el sistema propuesto es una FPGA Virtex 5 XC5VLX110T del fabricante Xilinx. La validación el propuesta para el sistema transceptor se ha implementado en dicha placa de FPGA. En este trabajo se presenta un algoritmo, y una arquitectura, diseñado con filosofía de co-diseño hardware/software para el desarrollo de sistemas de FPGA complejos. El objetivo principal de la estrategia propuesta es de encontrar una metodología eficiente para el diseño de un sistema de FPGA configurable optimizado con el empleo del mínimo esfuerzo posible en el sistema de procedimiento de verificación, por tanto acelerar el periodo de desarrollo del sistema. La metodología de co-diseño presentada tiene la ventaja de ser fácil de usar, contiene todos los pasos desde la propuesta del algoritmo hasta la verificación del hardware, y puede ser ampliamente extendida para casi todos los tipos de desarrollos de FPGAs. En este trabajo se ha desarrollado sólo el sistema de transceptor digital de banda base por lo que la comprobación de señales transmitidas a través del canal inalámbrico en los entornos reales de comunicación sigue requiriendo componentes RF y un front-end analógico. No obstante, utilizando la metodología de co-simulación hardware/software citada anteriormente, es posible comunicar el sistema de transmisor y el receptor digital utilizando los modelos de canales propuestos por IEEE 802.15.3a, implementados en MATLAB. Por tanto, simplemente ajustando las características de cada modelo de canal, por ejemplo, un incremento del retraso y de la frecuencia central, podemos estimar el comportamiento del sistema propuesto en diferentes escenarios y entornos. Las mayores contribuciones de esta tesis son: • Se ha propuesto un nuevo algoritmo 128-puntos base mixto FFT usando la arquitectura pipeline multi-ruta. Los complejos multiplicadores para cada etapa de procesamiento son diseñados usando la arquitectura modificada shiftadd. Los sistemas word length y twiddle word length son comparados y seleccionados basándose en la señal para cuantización del SQNR y el análisis de energías. • El desempeño del procesador IFFT es analizado bajo diferentes situaciones aritméticas de bloques de punto flotante (BFP) para el control de desbordamiento, por tanto, para encontrar la arquitectura perfecta del algoritmo IFFT basado en el procesador FFT propuesto. • Para el sistema de receptor MB-OFDM UWB se ha empleado una sincronización del tiempo innovadora, de baja complejidad y esquema de compensación, que consiste en funciones de Detector de Paquetes (PD) y Estimación del Offset del tiempo. Simplificando el cross-correlation y maximizar las funciones probables solo a sign-bit, la complejidad computacional se ve reducida significativamente. • Se ha propuesto un sistema de decodificadores Viterbi de 64 estados de decisión-débil usando velocidad base-4 de arquitectura suma-comparaselecciona. El algoritmo Two-pointer Even también es introducido en la unidad de rastreador de origen con el objetivo de conseguir la eficiencia en el hardware. • Se han integrado varias tecnologías de última generación en el completo sistema transceptor basebanda , con el objetivo de implementar un sistema de comunicación UWB altamente optimizado. • Un diseño de flujo mejorado es propuesto para el complejo sistema de implementación, el cual puede ser usado para diseños de Cadena de puertas de campo programable general (FPGA). El diseño mencionado no sólo reduce dramáticamente el tiempo para la verificación funcional, sino también provee un análisis automático como los errores del retraso del output para el sistema de hardware implementado. • Un ambiente de comunicación virtual es establecido para la validación del propuesto sistema de transceptores MB-OFDM. Este método es provisto para facilitar el uso y la conveniencia de analizar el sistema digital de basebanda sin parte frontera analógica bajo diferentes ambientes de comunicación. Esta tesis doctoral está organizada en seis capítulos. En el primer capítulo se encuentra una breve introducción al campo del UWB, tanto relacionado con el proyecto como la motivación del desarrollo del sistema de MB-OFDM. En el capítulo 2, se presenta la información general y los requisitos del protocolo de comunicación inalámbrica MBOFDM UWB. En el capítulo 3 se habla de la arquitectura del sistema de transceptor digital MB-OFDM de banda base . El diseño del algoritmo propuesto y la arquitectura para cada elemento del procesamiento está detallado en este capítulo. Los retos de diseño del sistema que involucra un compromiso de discusión entre la complejidad de diseño, el consumo de energía, el coste de hardware, el desempeño del sistema, y otros aspectos. En el capítulo 4, se ha descrito la co-diseñada metodología de hardware/software. Cada parte del flujo del diseño será detallado con algunos ejemplos que se ha hecho durante el desarrollo del sistema. Aprovechando esta estrategia de diseño, el procedimiento de comunicación virtual es llevado a cabo para probar y analizar la arquitectura del transceptor propuesto. Los resultados experimentales de la co-simulación y el informe sintético de la implementación del sistema FPGA son reflejados en el capítulo 5. Finalmente, en el capítulo 6 se incluye las conclusiones y los futuros proyectos, y también los resultados derivados de este proyecto de doctorado. ABSTRACT In recent years, the Wireless Visual Sensor Network (WVSN) has drawn great interest in wireless communication research area. They enable a wealth of new applications such as building security control, image sensing, and target localization. However, nowadays wireless communication protocols (ZigBee, Wi-Fi, and Bluetooth for example) cannot fully satisfy the demands of high data rate, low power consumption, short range, and high robustness requirements. New communication protocol is highly desired for such kind of applications. The Ultra Wideband (UWB) wireless communication protocol, which has increased in importance for high data rate wireless communication field, are emerging as an important topic for WVSN research. UWB has emerged as a technology that offers great promise to satisfy the growing demand for low-cost, high-speed digital wireless indoor and home networks. The large bandwidth available, the potential for high data rate transmission, and the potential for low complexity and low power consumption, along with low implementation cost, all present a unique opportunity for UWB to become a widely adopted radio solution for future Wireless Personal Area Network (WPAN) applications. UWB is defined as any transmission that occupies a bandwidth of more than 20% of its center frequency, or more than 500 MHz. In 2002, the Federal Communications Commission (FCC) has mandated that UWB radio transmission can legally operate in the range from 3.1 to 10.6 GHz at a transmitter power of －41.3 dBm/Hz. Under the FCC guidelines, the use of UWB technology can provide enormous capacity over short communication ranges. Considering Shannon’s capacity equations, increasing the channel capacity requires linear increasing in bandwidth, whereas similar channel capacity increases would require exponential increases in transmission power. In recent years, several different UWB developments has been widely studied in different area, among which, the MB-OFDM UWB wireless communication protocol is considered to be the leading choice and has recently been adopted in the ISO/IEC standard for WPANs. By combing the OFDM modulation and data transmission using frequency hopping techniques, the MB-OFDM UWB system is able to support various data rates, ranging from 55 to 480 Mbps, over distances up to 10 meters. The MB-OFDM technology is expected to consume very little power and silicon area, as well as provide low-cost solutions that can satisfy consumer market demands. To fulfill these expectations, MB-OFDM UWB research and development have to cope with several challenges, which consist of high-sensitivity synchronization, low- complexity constraints, strict power limitations, scalability, and flexibility. Such challenges require state-of-the-art digital signal processing expertise to develop systems that could fully take advantages of the UWB spectrum and support future indoor wireless applications. This thesis focuses on fully optimization for the MB-OFDM UWB digital baseband transceiver system, aiming at researching and designing a wireless communication subsystem for the Wireless Visual Sensor Networks (WVSNs) application. The inherent high complexity of the FFT/IFFT processor and synchronization system, and high operation frequency for all processing elements, becomes the bottleneck for low power MB-OFDM based UWB digital baseband system hardware design and implementation. The proposed transceiver system targets low power and low complexity under the premise of high performance. Optimizations are made at both algorithm and architecture level for each element of the transceiver system. The low-power hardwareefficient structures are firstly proposed for those core computation modules, i.e., the mixed-radix algorithm based pipelined architecture is proposed for the Fast Fourier Transform (FFT/IFFT) processor, and the cost-speed balanced Viterbi Decoder (VD) module is developed, in the aim of lowering the power consumption and increasing the processing speed. In addition, a low complexity sign-bit correlation based symbol timing synchronization scheme is presented so as to detect and synchronize the OFDM packets robustly and accurately. Moreover, several state-of-the-art technologies are used for developing other processing subsystems and an entire MB-OFDM digital baseband transceiver system is integrated. The target device for the proposed transceiver system is Xilinx Virtex 5 XC5VLX110T FPGA board. In order to validate the proposed transceiver system in the FPGA board, a unified algorithm-architecture-circuit hardware/software co-design environment for complex FPGA system development is presented in this work. The main objective of the proposed strategy is to find an efficient methodology for designing a configurable optimized FPGA system by using as few efforts as possible in system verification procedure, so as to speed up the system development period. The presented co-design methodology has the advantages of easy to use, covering all steps from algorithm proposal to hardware verification, and widely spread for almost all kinds of FPGA developments. Because only the digital baseband transceiver system is developed in this thesis, the validation of transmitting signals through wireless channel in real communication environments still requires the analog front-end and RF components. However, by using the aforementioned hardware/software co-simulation methodology, the transmitter and receiver digital baseband systems get the opportunity to communicate with each other through the channel models, which are proposed from the IEEE 802.15.3a research group, established in MATLAB. Thus, by simply adjust the characteristics of each channel model, e.g. mean excess delay and center frequency, we can estimate the transmission performance of the proposed transceiver system through different communication situations. The main contributions of this thesis are: • A novel mixed radix 128-point FFT algorithm by using multipath pipelined architecture is proposed. The complex multipliers for each processing stage are designed by using modified shift-add architectures. The system wordlength and twiddle word-length are compared and selected based on Signal to Quantization Noise Ratio (SQNR) and power analysis. • IFFT processor performance is analyzed under different Block Floating Point (BFP) arithmetic situations for overflow control, so as to find out the perfect architecture of IFFT algorithm based on the proposed FFT processor. • An innovative low complex timing synchronization and compensation scheme, which consists of Packet Detector (PD) and Timing Offset Estimation (TOE) functions, for MB-OFDM UWB receiver system is employed. By simplifying the cross-correlation and maximum likelihood functions to signbit only, the computational complexity is significantly reduced. • A 64 state soft-decision Viterbi Decoder system by using high speed radix-4 Add-Compare-Select architecture is proposed. Two-pointer Even algorithm is also introduced into the Trace Back unit in the aim of hardware-efficiency. • Several state-of-the-art technologies are integrated into the complete baseband transceiver system, in the aim of implementing a highly-optimized UWB communication system. • An improved design flow is proposed for complex system implementation which can be used for general Field-Programmable Gate Array (FPGA) designs. The design method not only dramatically reduces the time for functional verification, but also provides automatic analysis such as errors and output delays for the implemented hardware systems. • A virtual communication environment is established for validating the proposed MB-OFDM transceiver system. This methodology is proved to be easy for usage and convenient for analyzing the digital baseband system without analog frontend under different communication environments. This PhD thesis is organized in six chapters. In the chapter 1 a brief introduction to the UWB field, as well as the related work, is done, along with the motivation of MBOFDM system development. In the chapter 2, the general information and requirement of MB-OFDM UWB wireless communication protocol is presented. In the chapter 3, the architecture of the MB-OFDM digital baseband transceiver system is presented. The design of the proposed algorithm and architecture for each processing element is detailed in this chapter. Design challenges of such system involve trade-off discussions among design complexity, power consumption, hardware cost, system performance, and some other aspects. All these factors are analyzed and discussed. In the chapter 4, the hardware/software co-design methodology is proposed. Each step of this design flow will be detailed by taking some examples that we met during system development. Then, taking advantages of this design strategy, the Virtual Communication procedure is carried out so as to test and analyze the proposed transceiver architecture. Experimental results from the co-simulation and synthesis report of the implemented FPGA system are given in the chapter 5. The chapter 6 includes conclusions and future work, as well as the results derived from this PhD work.