Age-Related Effects in Working Memory Recognition Modulated by Retroactive Interference

One of the main causes for age-related declines in working memory is a higher vulnerability to retroactive interference due to a reduced ability to suppress irrelevant information. However, the underlying neural correlates remain to be established. Magnetoencephalography was used to investigate differential neural patterns in young and older adults performing an interference-based memory task with two experimental conditions, interrupting and distracting, during successful recognition. Behaviorally, both types of retroactive interference significantly impaired accuracy at recognition more in older adults than in young adults with the latter exhibiting greater disruptions by interrupters. Magnetoencephalography revealed the presence of differential age-related neural patterns. Specifically, time-modulated activations in temporo-occipital and superior parietal regions were higher in young adults compared with older adults for the interrupting condition. These results suggest that age-related deficits in inhibitory mechanisms that increase vulnerability to retroactive interference may be associated with neural under-recruitments in a high-interference task.

Using pMOS Pass-Gates to Boost SRAM Performance by Exploiting Strain Effects in Sub-20-nm FinFET Technologies

Strained fin is one of the techniques used to improve the devices as their size keeps reducing in new nanoscale nodes. In this paper, we use a predictive technology of 14 nm where pMOS mobility is significantly improved when those devices are built on top of long, uncut fins, while nMOS devices present the opposite behavior due to the combination of strains. We explore the possibility of boosting circuit performance in repetitive structures where long uncut fins can be exploited to increase fin strain impact. In particular, pMOS pass-gates are used in 6T complementary SRAM cells (CSRAM) with reinforced pull-ups. Those cells are simulated under process variability and compared to the regular SRAM. We show that when layout dependent effects are considered the CSRAM design provides 10% to 40% faster access time while keeping the same area, power, and stability than a regular 6T SRAM cell. The conclusions also apply to 8T SRAM cells. The CSRAM cell also presents increased reliability in technologies whose nMOS devices have more mismatch than pMOS transistors.