Fabrication of sub-100 nm IDT SAW devices on insulating, semiconducting and conductive substrates

This work describes the electron-beam (e-beam) lithography process developed to manufacture nano interdigital transducers (IDTs) to be used in high frequency (GHz) surface acoustic wave (SAW) applications. The combination of electron-beam (e-beam) lithography and lift-off process is shown to be effective in fabricating well-defined IDT finger patterns with a line width below 100 nm with a good yield. Working with insulating piezoelectric substrates brings about e-beam deflection. It is also shown how a very thin organic anti-static layer works well in avoiding this charge accumulation during e-beam lithography on the resist layer. However, the use of this anti-static layer is not required with the insulating piezoelectric layer laying on a semiconducting substrate such as highly doped silicon. The effect of the e-beam dose on a number of different layers (of insulating, insulating on semiconducting, semiconducting, and conductive natures) is provided. Among other advantages, the use of reduced e-beam doses increases the manufacturing time. The principal aim of this work is to explain the interrelation among e-beam dose, substrate nature and IDT structure. An extensive study of the e-beam lithography of long IDT-fingers is provided, in a wide variety of electrode widths, electrode numbers and electrode pitches. It is worthy to highlight that this work shows the influence of the e-beam dose on five substrates of different conductive nature

Impact of metal-organic vapor phase epitaxy environment on silicon bulk lifetime for III–V-on-Si multijunction solar cells

With the final goal of integrating III-V materials on silicon substrates for tandem solar cells, the influence of the Metal-Organic Vapor Phase Epitaxy (MOVPE) environment on the minority carrier properties of silicon wafers has been evaluated. These properties will essentially determine the photovoltaic performance of the bottom cell in a III-V-on-Si tandem solar cell. A comparison of the base minority carrier lifetimes obtained for different thermal processes carried out in a MOVPE reactor on Czochralski silicon wafers has been carried out. An important degradation of minority carrier lifetime during the surface preparation (i.e. H2 anneal) has been observed. Three different mechanisms have been proposed for explaining this behavior: 1) the introduction of extrinsic impurities coming from the reactor; 2) the activation of intrinsic lifetime killing impurities coming from the wafer itself; and finally, 3) the formation of crystal defects, which eventually become recombination centers. The effect of the emitter formation by phosphorus diffusion has also been evaluated. In this sense, it has been reported that lifetime can be recovered during the emitter formation either by the effect of the P on extracting impurities, or by the role of the atomic hydrogen on passivating the defects.