Decoding urban landscapes through the analysis of place names and imaginaries at a local scale.

Toponomastics is increasingly interested in the subjective role of place names in quotidian life. In the frame of Urban Geography, the interest in this matter is currently growing, as the recently change in modes of habitation has urged our discipline to find new ways of exploring the cities. In this context, the study of how name's significance is connected to a urban society constitutes a very interesting approach. We believe in the importance of place names as tools for decoding urban areas and societies at a local-scale. This consideration has been frequently taken into account in the analysis of exonyms, although in their case they are not exempt of political and practical implications that prevail over the tool function. The study of toponomastic processes helps us understanding how the city works, by analyzing the liaison between urban landscape, imaginaries and toponyms which is reflected in the scarcity of some names, in the biased creation of new toponyms and in the pressure exercised over every place name by tourists, residents and local government for changing, maintaining or eliminating them. Our study-case, Toledo, is one of the oldest cities in Spain, full of myths, stories and histories that can only be understood combined with processes of internal evolution of the city linked to the arrival of new residents and the more and more notorious change of its historical landscape. At a local scale, we are willing to decode the information which is contained in its toponyms about its landscape and its society.

Mesh traversal and sorting for efficient memory usage in scientific codes

Applications that operate on meshes are very popular in High Performance Computing (HPC) environments. In the past, many techniques have been developed in order to optimize the memory accesses for these datasets. Different loop transformations and domain decompositions are com- monly used for structured meshes. However, unstructured grids are more challenging. The memory accesses, based on the mesh connectivity, do not map well to the usual lin- ear memory model. This work presents a method to improve the memory performance which is suitable for HPC codes that operate on meshes. We develop a method to adjust the sequence in which the data are used inside the algorithm, by means of traversing and sorting the mesh. This sorted mesh can be transferred sequentially to the lower memory levels and allows for minimum data transfer requirements. The method also reduces the lower memory requirements dra- matically: up to 63% of the L1 cache misses are removed in a traditional cache system. We have obtained speedups of up to 2.58 on memory operations as measured in a general- purpose CPU. An improvement is also observed with se- quential access memories, where we have observed reduc- tions of up to 99% in the required low-level memory size.

Explointing FPGA block memories for protected cryptographic implementations

Modern Field Programmable Gate Arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like huge block memory (BRAM), Digital Signal Processing (DSP) cores, embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGA are also widely used in security-critical application where protection against known attacks is of prime importance. We focus ourselves on physical attacks which target physical implementations. To design countermeasures against such attacks, the strategy for FPGA designers should also be different from that in ASIC. The available features should be exploited to design compact and strong countermeasures. In this paper, we propose methods to exploit the BRAMs in FPGAs for designing compact countermeasures. BRAM can be used to optimize intrinsic countermeasures like masking and dual-rail logic, which otherwise have significant overhead (at least 2X). The optimizations are applied on a real AES-128 co-processor and tested for area overhead and resistance on Xilinx Virtex-5 chips. The presented masking countermeasure has an overhead of only 16% when applied on AES. Moreover Dual-rail Precharge Logic (DPL) countermeasure has been optimized to pack the whole sequential part in the BRAM, hence enhancing the security. Proper robustness evaluations are conducted to analyze the optimization for area and security.

Star dust memories, or how to detect allergen traces in powder foods

Allergies and food intolerances are at the forefront of institutional interest (European Regulation No 1169/2011) for their impact on consumer health. Allergies to peanuts and other nuts and gluten intolerance, makes production processes involving mixtures of powders a great concern for the industry, given the need to indicate the existence of traces of any of them. The food industry requires non-destructive and non-invasive methods of quantification that meet sensitivity requirements but also specificity levels. Optical methods such as NIR spectrophotometry or hyper-spectral image are currently some of the technologies that show potential success. This is the context of this paper that evaluates how to use NIR spectroscopy (900-1600nm) to detect traces of 15 different kinds of nuts and 20 other flours.