Alta velocidad ferroviaria en California(USA): quinta parte (V) LAV San Francisco–Sacramento (Bay Crossing Alternative) = High speed railway in California (USA): fith part (V) HSRL San Francisco–Sacramento (Bay Crossing Alternative)

Implantación de la Red de Alta velocidad Ferroviaria en California. Tramo San Francisco-Sacramento. Este artículo de la serie “Alta velocidad Ferroviaria en California (CHSRS), se ocupa de la línea San Francisco– Sacramento “Bay Crossing Alternative”, que cierra la red de alta velocidad ferroviaria del Estado de California, permitiendo en la terminal HSR de Sacramento, conectar con la línea Fresno–Sacramento, en coincidencia de trazados para en el futuro prolongar la red californiana de alta velocidad ferroviaria hasta su entronque con la del Estado de Nevada, vía Tahoe Lake–Reno. La línea San Francisco–Sacramento “Bay Crossing Alternative”, consta de tres trayectos: El primero de ellos “San Francisco urbano” va desde la terminal HSR “San Francisco Airport”, donde termina la alternativa “Golden Gate” de la línea Fresno–San Francisco, hasta el viaducto de acceso al Paso de la Bahía, que constituye el segundo trayecto “San Francisco–Richmond”, trayecto estrella de la red, de 15,48 Km de longitud sobre la Bahía de San Francisco, con desarrollo a través de 11,28 Km en puente colgante múltiple, con vanos de 800 m de luz y 67 m de altura libre bajo el tablero que permite la navegación en la Bahía. El tercer trayecto “Richmond–Sacramento” cruza la Bahía de San Pablo con un puente colgante de 1,6 Km de longitud y tipología similar a los múltiples de la Bahía de San Francisco, pasa por Vallejo (la por plazo breve de tiempo, antigua capital del Estado de California) y por la universitaria Davis, antes de finalmente llegar a la HSR Terminal Station de Sacramento Roseville. This article of the series “California High Speed Railway System”(CHSRS) treats on Line San Francisco–Sacramento “Bay Crossing Alternative” (BCA). This line closes the system of California high speed state railway, and connects with the line Fresno–Sacramento “Stockton Arch Alternative”, joining its alignments in the HSR Terminal of Sacramento Roseville. From this station it will be possible, in the future, to extend the Californian railway system till the Nevada railway system, vía Tahoe Lake and Reno. The BCA consists of three sections: The first one passing through San Francisco city, goes from HSR San Francisco Airport Terminal Station (where the line Fresno–San Francisco “Golden Gate Alternative” ends), up to the Viaduct access at the Bay Crossing. The second section San Francisco–Richmond, constitutes the star section of the system, with 15,48 Km length on the San Francisco Bay, where 11,28 Km in multi suspension bridge, 800 m span and 67 m gauge under panel, to allow navigation through the Bay. The third section Richmond–Sacramento crosses the San Pablo Bay through another suspension bridge of similar typology to that of San Francisco Bay crossing; pass through Vallejo (the ancient and for a short time Head of the State of California) and through Davis, university city, to arrive to the HSR Terminal Station of Sacramento Roseville.

FPGA-Based Wireless Sensor Node Architecture for High Performance Applications

While for years traditional wireless sensor nodes have been based on ultra-low power microcontrollers with sufficient but limited computing power, the complexity and number of tasks of today’s applications are constantly increasing. Increasing the node duty cycle is not feasible in all cases, so in many cases more computing power is required. This extra computing power may be achieved by either more powerful microcontrollers, though more power consumption or, in general, any solution capable of accelerating task execution. At this point, the use of hardware based, and in particular FPGA solutions, might appear as a candidate technology, since though power use is higher compared with lower power devices, execution time is reduced, so energy could be reduced overall. In order to demonstrate this, an innovative WSN node architecture is proposed. This architecture is based on a high performance high capacity state-of-the-art FPGA, which combines the advantages of the intrinsic acceleration provided by the parallelism of hardware devices, the use of partial reconfiguration capabilities, as well as a careful power-aware management system, to show that energy savings for certain higher-end applications can be achieved. Finally, comprehensive tests have been done to validate the platform in terms of performance and power consumption, to proof that better energy efficiency compared to processor based solutions can be achieved, for instance, when encryption is imposed by the application requirements.