5 resultados para high charge state

em Universidad Politécnica de Madrid


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Radiative shock waves play a pivotal role in the transport energy into the stellar medium. This fact has led to many efforts to scale the astrophysical phenomena to accessible laboratory conditions and their study has been highlighted as an area requiring further experimental investigations. Low density material with high atomic mass is suitable to achieve radiative regime, and, therefore, low density xenon gas is commonly used for the medium in which the radiative shocks such as radiative blast waves propagate. In this work, by means of collisional-radiative steady-state calculations, a characterization and an analysis of microscopic magnitudes of laboratory blast waves launched in xenon clusters are made. Thus, for example, the average ionization, the charge state distribution, the cooling time or photon mean free paths are studied. Furthermore, for a particular experiment, the effects of the self-absorption and self-emission in the specific intensity emitted by the shock front and that is going through the radiative precursor are investigated. Finally, for that experiment, since the electron temperature is not measured experimentally, an estimation of this magnitude is made both for the shock shell and the radiative precursor.

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Implantación de la Red de Alta velocidad Ferroviaria en California. Tramo San Francisco-Sacramento. Este artículo de la serie “Alta velocidad Ferroviaria en California (CHSRS), se ocupa de la línea San Francisco– Sacramento “Bay Crossing Alternative”, que cierra la red de alta velocidad ferroviaria del Estado de California, permitiendo en la terminal HSR de Sacramento, conectar con la línea Fresno–Sacramento, en coincidencia de trazados para en el futuro prolongar la red californiana de alta velocidad ferroviaria hasta su entronque con la del Estado de Nevada, vía Tahoe Lake–Reno. La línea San Francisco–Sacramento “Bay Crossing Alternative”, consta de tres trayectos: El primero de ellos “San Francisco urbano” va desde la terminal HSR “San Francisco Airport”, donde termina la alternativa “Golden Gate” de la línea Fresno–San Francisco, hasta el viaducto de acceso al Paso de la Bahía, que constituye el segundo trayecto “San Francisco–Richmond”, trayecto estrella de la red, de 15,48 Km de longitud sobre la Bahía de San Francisco, con desarrollo a través de 11,28 Km en puente colgante múltiple, con vanos de 800 m de luz y 67 m de altura libre bajo el tablero que permite la navegación en la Bahía. El tercer trayecto “Richmond–Sacramento” cruza la Bahía de San Pablo con un puente colgante de 1,6 Km de longitud y tipología similar a los múltiples de la Bahía de San Francisco, pasa por Vallejo (la por plazo breve de tiempo, antigua capital del Estado de California) y por la universitaria Davis, antes de finalmente llegar a la HSR Terminal Station de Sacramento Roseville. This article of the series “California High Speed Railway System”(CHSRS) treats on Line San Francisco–Sacramento “Bay Crossing Alternative” (BCA). This line closes the system of California high speed state railway, and connects with the line Fresno–Sacramento “Stockton Arch Alternative”, joining its alignments in the HSR Terminal of Sacramento Roseville. From this station it will be possible, in the future, to extend the Californian railway system till the Nevada railway system, vía Tahoe Lake and Reno. The BCA consists of three sections: The first one passing through San Francisco city, goes from HSR San Francisco Airport Terminal Station (where the line Fresno–San Francisco “Golden Gate Alternative” ends), up to the Viaduct access at the Bay Crossing. The second section San Francisco–Richmond, constitutes the star section of the system, with 15,48 Km length on the San Francisco Bay, where 11,28 Km in multi suspension bridge, 800 m span and 67 m gauge under panel, to allow navigation through the Bay. The third section Richmond–Sacramento crosses the San Pablo Bay through another suspension bridge of similar typology to that of San Francisco Bay crossing; pass through Vallejo (the ancient and for a short time Head of the State of California) and through Davis, university city, to arrive to the HSR Terminal Station of Sacramento Roseville.

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Recently, a novel method to trap and pattern ensembles of nanoparticles has been proposed and tested. It relies on the photovoltaic (PV) properties of certain ferroelectric crystals such as LiNbO3 [1,2]. These crystals, when suitably doped, develop very high electric fields in response to illumination with light of suitable wavelength. The PV effect lies in the asymmetrical excitation of electrons giving rise to PV currents and associated space-charge fields (photorefractive effect). The field generated in the bulk of the sample propagates to the surrounding medium as evanescent fields. When dielectric or metal nanoparticles are deposited on the surface of the sample the evanescent fields give rise to either electrophoretic or dielectrophoretic forces, depending on the charge state of the particles, that induce the trapping and patterning effects [3,4]. The purpose of this work has been to explore the effects of such PV fields in the biology and biomedical areas. A first work was able to show the necrotic effects induced by such fields on He-La tumour cells grown on the surface of an illuminated iron-doped LiNbO3 crystal [5]. In principle, it is conceived that LiNbO3 nanoparticles may be advantageously used for such biomedical purposes considering the possibility of such nanoparticles being incorporated into the cells. Previous experiments using microparticles have been performed [5] with similar results to those achieved with the substrate. Therefore, the purpose of this work has been to fabricate and characterize the LiNbO3 nanoparticles and assess their necrotic effects when they are incorporated on a culture of tumour cells. Two different preparation methods have been used: 1) mechanical grinding from crystals, and 2) bottom-up sol-gel chemical synthesis from metal-ethoxide precursors. This later method leads to a more uniform size distribution of smaller particles (down to around 50 nm). Fig. 1(a) and 1(b) shows SEM images of the nanoparticles obtained with both method. An ad hoc software taking into account the physical properties of the crystal, particullarly donor and aceptor concentrations has been developped in order to estimate the electric field generated in noparticles. In a first stage simulations of the electric current of nanoparticles, in a conductive media, due to the PV effect have been carried out by MonteCarlo simulations using the Kutharev 1-centre transport model equations [6] . Special attention has been paid to the dependence on particle size and [Fe2+]/[Fe3+]. First results on cubic particles shows large dispersion for small sizes due to the random number of donors and its effective concentration (Fig 2). The necrotic (toxicity) effect of nanoparticles incorporated into a tumour cell culture subjected to 30 min. illumination with a blue LED is shown in Fig.3. For each type of nanoparticle the percent of cell survival in dark and illumination conditions has been plot as a function of the particle dilution factor. Fig. 1a corresponds to mechanical grinding particles whereas 1b and 1c refer to chemically synthesized particles with two oxidation states. The light effect is larger with mechanical grinding nanoparticles, but dark toxicity is also higher. For chemically synthesized nanoparticles dark toxicity is low but only in oxidized samples, where the PV effect is known to be larger, the light effect is appreciable. These preliminary results demonstrate that Fe:LiNbO· nanoparticles have a biological damaging effect on cells, although there are many points that should be clarified and much space for PV nanoparticles optimization. In particular, it appears necessary to determine the fraction of nanoparticles that become incorporated into the cells and the possible existence of threshold size effects. This work has been supported by MINECO under grant MAT2011-28379-C03.

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While for years traditional wireless sensor nodes have been based on ultra-low power microcontrollers with sufficient but limited computing power, the complexity and number of tasks of today’s applications are constantly increasing. Increasing the node duty cycle is not feasible in all cases, so in many cases more computing power is required. This extra computing power may be achieved by either more powerful microcontrollers, though more power consumption or, in general, any solution capable of accelerating task execution. At this point, the use of hardware based, and in particular FPGA solutions, might appear as a candidate technology, since though power use is higher compared with lower power devices, execution time is reduced, so energy could be reduced overall. In order to demonstrate this, an innovative WSN node architecture is proposed. This architecture is based on a high performance high capacity state-of-the-art FPGA, which combines the advantages of the intrinsic acceleration provided by the parallelism of hardware devices, the use of partial reconfiguration capabilities, as well as a careful power-aware management system, to show that energy savings for certain higher-end applications can be achieved. Finally, comprehensive tests have been done to validate the platform in terms of performance and power consumption, to proof that better energy efficiency compared to processor based solutions can be achieved, for instance, when encryption is imposed by the application requirements.

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Los transistores de alta movilidad electrónica basados en GaN han sido objeto de una extensa investigación ya que tanto el GaN como sus aleaciones presentan unas excelentes propiedades eléctricas (alta movilidad, elevada concentración de portadores y campo eléctrico crítico alto). Aunque recientemente se han incluido en algunas aplicaciones comerciales, su expansión en el mercado está condicionada a la mejora de varios asuntos relacionados con su rendimiento y habilidad. Durante esta tesis se han abordado algunos de estos aspectos relevantes; por ejemplo, la fabricación de enhancement mode HEMTs, su funcionamiento a alta temperatura, el auto calentamiento y el atrapamiento de carga. Los HEMTs normalmente apagado o enhancement mode han atraído la atención de la comunidad científica dedicada al desarrollo de circuitos amplificadores y conmutadores de potencia, ya que su utilización disminuiría significativamente el consumo de potencia; además de requerir solamente una tensión de alimentación negativa, y reducir la complejidad del circuito y su coste. Durante esta tesis se han evaluado varias técnicas utilizadas para la fabricación de estos dispositivos: el ataque húmedo para conseguir el gate-recess en heterostructuras de InAl(Ga)N/GaN; y tratamientos basados en flúor (plasma CF4 e implantación de F) de la zona debajo de la puerta. Se han llevado a cabo ataques húmedos en heteroestructuras de InAl(Ga)N crecidas sobre sustratos de Si, SiC y zafiro. El ataque completo de la barrera se consiguió únicamente en las muestras con sustrato de Si. Por lo tanto, se puede deducir que la velocidad de ataque depende de la densidad de dislocaciones presentes en la estructura, ya que el Si presenta un peor ajuste del parámetro de red con el GaN. En relación a los tratamientos basados en flúor, se ha comprobado que es necesario realizar un recocido térmico después de la fabricación de la puerta para recuperar la heteroestructura de los daños causados durante dichos tratamientos. Además, el estudio de la evolución de la tensión umbral con el tiempo de recocido ha demostrado que en los HEMTs tratados con plasma ésta tiende a valores más negativos al aumentar el tiempo de recocido. Por el contrario, la tensión umbral de los HEMTs implantados se desplaza hacia valores más positivos, lo cual se atribuye a la introducción de iones de flúor a niveles más profundos de la heterostructura. Los transistores fabricados con plasma presentaron mejor funcionamiento en DC a temperatura ambiente que los implantados. Su estudio a alta temperatura ha revelado una reducción del funcionamiento de todos los dispositivos con la temperatura. Los valores iniciales de corriente de drenador y de transconductancia medidos a temperatura ambiente se recuperaron después del ciclo térmico, por lo que se deduce que dichos efectos térmicos son reversibles. Se han estudiado varios aspectos relacionados con el funcionamiento de los HEMTs a diferentes temperaturas. En primer lugar, se han evaluado las prestaciones de dispositivos de AlGaN/GaN sobre sustrato de Si con diferentes caps: GaN, in situ SiN e in situ SiN/GaN, desde 25 K hasta 550 K. Los transistores con in situ SiN presentaron los valores más altos de corriente drenador, transconductancia, y los valores más bajos de resistencia-ON, así como las mejores características en corte. Además, se ha confirmado que dichos dispositivos presentan gran robustez frente al estrés térmico. En segundo lugar, se ha estudiado el funcionamiento de transistores de InAlN/GaN con diferentes diseños y geometrías. Dichos dispositivos presentaron una reducción casi lineal de los parámetros en DC en el rango de temperaturas de 25°C hasta 225°C. Esto se debe principalmente a la dependencia térmica de la movilidad electrónica, y también a la reducción de la drift velocity con la temperatura. Además, los transistores con mayores longitudes de puerta mostraron una mayor reducción de su funcionamiento, lo cual se atribuye a que la drift velocity disminuye más considerablemente con la temperatura cuando el campo eléctrico es pequeño. De manera similar, al aumentar la distancia entre la puerta y el drenador, el funcionamiento del HEMT presentó una mayor reducción con la temperatura. Por lo tanto, se puede deducir que la degradación del funcionamiento de los HEMTs causada por el aumento de la temperatura depende tanto de la longitud de la puerta como de la distancia entre la puerta y el drenador. Por otra parte, la alta densidad de potencia generada en la región activa de estos transistores conlleva el auto calentamiento de los mismos por efecto Joule, lo cual puede degradar su funcionamiento y Habilidad. Durante esta tesis se ha desarrollado un simple método para la determinación de la temperatura del canal basado en medidas eléctricas. La aplicación de dicha técnica junto con la realización de simulaciones electrotérmicas han posibilitado el estudio de varios aspectos relacionados con el autocalentamiento. Por ejemplo, se han evaluado sus efectos en dispositivos sobre Si, SiC, y zafiro. Los transistores sobre SiC han mostrado menores efectos gracias a la mayor conductividad térmica del SiC, lo cual confirma el papel clave que desempeña el sustrato en el autocalentamiento. Se ha observado que la geometría del dispositivo tiene cierta influencia en dichos efectos, destacando que la distribución del calor generado en la zona del canal depende de la distancia entre la puerta y el drenador. Además, se ha demostrado que la temperatura ambiente tiene un considerable impacto en el autocalentamiento, lo que se atribuye principalmente a la dependencia térmica de la conductividad térmica de las capas y sustrato que forman la heterostructura. Por último, se han realizado numerosas medidas en pulsado para estudiar el atrapamiento de carga en HEMTs sobre sustratos de SiC con barreras de AlGaN y de InAlN. Los resultados obtenidos en los transistores con barrera de AlGaN han presentado una disminución de la corriente de drenador y de la transconductancia sin mostrar un cambio en la tensión umbral. Por lo tanto, se puede deducir que la posible localización de las trampas es la región de acceso entre la puerta y el drenador. Por el contrario, la reducción de la corriente de drenador observada en los dispositivos con barrera de InAlN llevaba asociado un cambio significativo en la tensión umbral, lo que implica la existencia de trampas situadas en la zona debajo de la puerta. Además, el significativo aumento del valor de la resistencia-ON y la degradación de la transconductancia revelan la presencia de trampas en la zona de acceso entre la puerta y el drenador. La evaluación de los efectos del atrapamiento de carga en dispositivos con diferentes geometrías ha demostrado que dichos efectos son menos notables en aquellos transistores con mayor longitud de puerta o mayor distancia entre puerta y drenador. Esta dependencia con la geometría se puede explicar considerando que la longitud y densidad de trampas de la puerta virtual son independientes de las dimensiones del dispositivo. Finalmente se puede deducir que para conseguir el diseño óptimo durante la fase de diseño no sólo hay que tener en cuenta la aplicación final sino también la influencia que tiene la geometría en los diferentes aspectos estudiados (funcionamiento a alta temperatura, autocalentamiento, y atrapamiento de carga). ABSTRACT GaN-based high electron mobility transistors have been under extensive research due to the excellent electrical properties of GaN and its related alloys (high carrier concentration, high mobility, and high critical electric field). Although these devices have been recently included in commercial applications, some performance and reliability issues need to be addressed for their expansion in the market. Some of these relevant aspects have been studied during this thesis; for instance, the fabrication of enhancement mode HEMTs, the device performance at high temperature, the self-heating and the charge trapping. Enhancement mode HEMTs have become more attractive mainly because their use leads to a significant reduction of the power consumption during the stand-by state. Moreover, they enable the fabrication of simpler power amplifier circuits and high-power switches because they allow the elimination of negativepolarity voltage supply, reducing significantly the circuit complexity and system cost. In this thesis, different techniques for the fabrication of these devices have been assessed: wet-etching for achieving the gate-recess in InAl(Ga)N/GaN devices and two different fluorine-based treatments (CF4 plasma and F implantation). Regarding the wet-etching, experiments have been carried out in InAl(Ga)N/GaN grown on different substrates: Si, sapphire, and SiC. The total recess of the barrier was achieved after 3 min of etching in devices grown on Si substrate. This suggests that the etch rate can critically depend on the dislocations present in the structure, since the Si exhibits the highest mismatch to GaN. Concerning the fluorine-based treatments, a post-gate thermal annealing was required to recover the damages caused to the structure during the fluorine-treatments. The study of the threshold voltage as a function of this annealing time has revealed that in the case of the plasma-treated devices it become more negative with the time increase. On the contrary, the threshold voltage of implanted HEMTs showed a positive shift when the annealing time was increased, which is attributed to the deep F implantation profile. Plasma-treated HEMTs have exhibited better DC performance at room temperature than the implanted devices. Their study at high temperature has revealed that their performance decreases with temperature. The initial performance measured at room temperature was recovered after the thermal cycle regardless of the fluorine treatment; therefore, the thermal effects were reversible. Thermal issues related to the device performance at different temperature have been addressed. Firstly, AlGaN/GaN HEMTs grown on Si substrate with different cap layers: GaN, in situ SiN, or in situ SiN/GaN, have been assessed from 25 K to 550 K. In situ SiN cap layer has been demonstrated to improve the device performance since HEMTs with this cap layer have exhibited the highest drain current and transconductance values, the lowest on-resistance, as well as the best off-state characteristics. Moreover, the evaluation of thermal stress impact on the device performance has confirmed the robustness of devices with in situ cap. Secondly, the high temperature performance of InAlN/GaN HEMTs with different layouts and geometries have been assessed. The devices under study have exhibited an almost linear reduction of the main DC parameters operating in a temperature range from room temperature to 225°C. This was mainly due to the thermal dependence of the electron mobility, and secondly to the drift velocity decrease with temperature. Moreover, HEMTs with large gate length values have exhibited a great reduction of the device performance. This was attributed to the greater decrease of the drift velocity for low electric fields. Similarly, the increase of the gate-to-drain distance led to a greater reduction of drain current and transconductance values. Therefore, this thermal performance degradation has been found to be dependent on both the gate length and the gate-to-drain distance. It was observed that the very high power density in the active region of these transistors leads to Joule self-heating, resulting in an increase of the device temperature, which can degrade the device performance and reliability. A simple electrical method have been developed during this work to determine the channel temperature. Furthermore, the application of this technique together with the performance of electro-thermal simulations have enabled the evaluation of different aspects related to the self-heating. For instance, the influence of the substrate have been confirmed by the study of devices grown on Si, SiC, and Sapphire. HEMTs grown on SiC substrate have been confirmed to exhibit the lowest self-heating effects thanks to its highest thermal conductivity. In addition to this, the distribution of the generated heat in the channel has been demonstrated to be dependent on the gate-to-drain distance. Besides the substrate and the geometry of the device, the ambient temperature has also been found to be relevant for the self-heating effects, mainly due to the temperature-dependent thermal conductivity of the layers and the substrate. Trapping effects have been evaluated by means of pulsed measurements in AlGaN and InAIN barrier devices. AlGaN barrier HEMTs have exhibited a de crease in drain current and transconductance without measurable threshold voltage change, suggesting the location of the traps in the gate-to-drain access region. On the contrary, InAIN barrier devices have showed a drain current associated with a positive shift of threshold voltage, which indicated that the traps were possibly located under the gate region. Moreover, a significant increase of the ON-resistance as well as a transconductance reduction were observed, revealing the presence of traps on the gate-drain access region. On the other hand, the assessment of devices with different geometries have demonstrated that the trapping effects are more noticeable in devices with either short gate length or the gate-to-drain distance. This can be attributed to the fact that the length and the trap density of the virtual gate are independent on the device geometry. Finally, it can be deduced that besides the final application requirements, the influence of the device geometry on the performance at high temperature, on the self-heating, as well as on the trapping effects need to be taken into account during the device design stage to achieve the optimal layout.