20 resultados para frequency shift keying (FSK) signals

em Universidad Politécnica de Madrid


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Differential Phase Shift Keying (DPSK) modulation format has been shown as a robust solution for next-generation optical transmission systems. One key device enabling such systems is a delay interferometer, converting the phase modulation signal into the intensity modulation signal to be detected by the photodiodes. Usually, a standard Mach-Zehnder interferometer (MZI) is used for demodulating a DPSK signal. In this paper, we develop an MZI which is based on all-fiber Multimode Interference (MI) structure: a multimode fiber (MMF) with a central dip, located between two single-mode fibers (SMFs) without any transition zones. The MI based MZI (MI-MZI) is more stable than the standard MZI as the two arms share the same MMF, reducing the impact of the external effects, such as temperature and others. Performance of this MI-MZI is analyzed theoretically and experimentally from transmission spectrum. Experimental results shows that high interference extinction ratio is obtained, which is far higher than that obtained from a normal graded-index based MI-MZI. Finally, by software simulation, we demonstrate that our proposed MI-MZI can be used for demodulating a 40 Gbps DPSK signal. The performance of the MI-MZI based DPSK receiver is analyzed from the sensitivity. Simulation results show that sensitivity of the proposed receiver is about -22.3 dBm for a BER of 10-15 and about -23.8 dBm for a BER of 10-9.

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In this work we present a new way to mask the data in a one-user communication system when direct sequence - code division multiple access (DS-CDMA) techniques are used. The code is generated by a digital chaotic generator, originally proposed by us and previously reported for a chaos cryptographic system. It is demonstrated that if the user's data signal is encoded with a bipolar phase-shift keying (BPSK) technique, usual in DS-CDMA, it can be easily recovered from a time-frequency domain representation. To avoid this situation, a new system is presented in which a previous dispersive stage is applied to the data signal. A time-frequency domain analysis is performed, and the devices required at the transmitter and receiver end, both user-independent, are presented for the optical domain.

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Optical communications receivers using wavelet signals processing is proposed in this paper for dense wavelength-division multiplexed (DWDM) systems and modal-division multiplexed (MDM) transmissions. The optical signal-to-noise ratio (OSNR) required to demodulate polarization-division multiplexed quadrature phase shift keying (PDM-QPSK) modulation format is alleviated with the wavelet denoising process. This procedure improves the bit error rate (BER) performance and increasing the transmission distance in DWDM systems. Additionally, the wavelet-based design relies on signal decomposition using time-limited basis functions allowing to reduce the computational cost in Digital-Signal-Processing (DSP) module. Attending to MDM systems, a new scheme of encoding data bits based on wavelets is presented to minimize the mode coupling in few-mode (FWF) and multimode fibers (MMF). The Shifted Prolate Wave Spheroidal (SPWS) functions are proposed to reduce the modal interference.

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Differential Phase Shift Keying (DPSK) modulation format has been shown as a robust solution for next-generation optical transmission systems. One key device enabling such systems is the delay interferometer, converting the signal phase information into intensity modulation to be detected by the photodiodes. Usually, Mach-Zehnder interferometer (MZI) is used for demodulating DPSK signals. In this paper, we developed an MZI which is based on all-fiber Multimode Interference (MI) structure: a multimode fiber (MMF) located between two single-mode fibers (SMF) without any transition zones. The standard MZI is not very stable since the two beams go through two different paths before they recombine. In our design the two arms of the MZI are in the same fiber, which will make it less temperature-sensitive than the standard MZI. Performance of such MZI will be analyzed from transmission spectrum. Finally such all-fiber MI-based MZI (MI-MZI) is used to demodulate 10 Gbps DPSK signals. The demodulated signals are analyzed from eye diagram and bit error rate (BER).

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El objetivo principal de esta tesis ha sido el diseño y la optimización de receptores implementados con fibra óptica, para ser usados en redes ópticas de alta velocidad que empleen formatos de modulación de fase. En los últimos años, los formatos de modulación de fase (Phase Shift keying, PSK) han captado gran atención debido a la mejora de sus prestaciones respecto a los formatos de modulación convencionales. Principalmente, presentan una mejora de la eficiencia espectral y una mayor tolerancia a la degradación de la señal causada por la dispersión cromática, la dispersión por modo de polarización y los efectos no-lineales en la fibra óptica. En este trabajo, se analizan en detalle los formatos PSK, incluyendo sus variantes de modulación de fase diferencial (Differential Phase Shift Keying, DPSK), en cuadratura (Differential Quadrature Phase Shift Keying, DQPSK) y multiplexación en polarización (Polarization Multiplexing Differential Quadrature Phase Shift Keying, PM-DQPSK), con la finalidad de diseñar y optimizar los receptores que permita su demodulación. Para ello, se han analizado y desarrollado nuevas estructuras que ofrecen una mejora en las prestaciones del receptor y una reducción de coste comparadas con las actualmente disponibles. Para la demodulación de señales DPSK, en esta tesis, se proponen dos nuevos receptores basados en un interferómetro en línea Mach-Zehnder (MZI) implementado con tecnología todo-fibra. El principio de funcionamiento de los MZI todo-fibra propuestos se asienta en la interferencia modal que se produce en una fibra multimodo (MMF) cuando se situada entre dos monomodo (SMF). Este tipo de configuración (monomodo-multimodo-monomodo, SMS) presenta un buen ratio de extinción interferente si la potencia acoplada en la fibra multimodo se reparte, principal y equitativamente, entre dos modos dominantes. Con este objetivo, se han estudiado y demostrado tanto teórica como experimentalmente dos nuevas estructuras SMS que mejoran el ratio de extinción. Una de las propuestas se basa en emplear una fibra multimodo de índice gradual cuyo perfil del índice de refracción presenta un hundimiento en su zona central. La otra consiste en una estructura SMS con las fibras desalineadas y donde la fibra multimodo es una fibra de índice gradual convencional. Para las dos estructuras, mediante el análisis teórico desarrollado, se ha demostrado que el 80 – 90% de la potencia de entrada se acopla a los dos modos dominantes de la fibra multimodo y se consigue una diferencia inferior al 10% entre ellos. También se ha demostrado experimentalmente que se puede obtener un ratio de extinción de al menos 12 dB. Con el objeto de demostrar la capacidad de estas estructuras para ser empleadas como demoduladores de señales DPSK, se han realizado numerosas simulaciones de un sistema de transmisión óptico completo y se ha analizado la calidad del receptor bajo diferentes perspectivas, tales como la sensibilidad, la tolerancia a un filtrado óptico severo o la tolerancia a las dispersiones cromática y por modo de polarización. En todos los casos se ha concluido que los receptores propuestos presentan rendimientos comparables a los obtenidos con receptores convencionales. En esta tesis, también se presenta un diseño alternativo para la implementación de un receptor DQPSK, basado en el uso de una fibra mantenedora de la polarización (PMF). A través del análisi teórico y del desarrollo de simulaciones numéricas, se ha demostrado que el receptor DQPSK propuesto presenta prestaciones similares a los convencionales. Para complementar el trabajo realizado sobre el receptor DQPSK basado en PMF, se ha extendido el estudio de su principio de demodulación con el objeto de demodular señales PM-DQPSK, obteniendo como resultado la propuesta de una nueva estructura de demodulación. El receptor PM-DQPSK propuesto se basa en la estructura conjunta de una única línea de retardo junto con un rotador de polarización. Se ha analizado la calidad de los receptores DQPSK y PM-DQPSK bajo diferentes perspectivas, tales como la sensibilidad, la tolerancia a un filtrado óptico severo, la tolerancia a las dispersiones cromática y por modo de polarización o su comportamiento bajo condiciones no-ideales. En comparación con los receptores convencionales, nuestra propuesta exhibe prestaciones similares y además permite un diseño más simple que redunda en un coste potencialmente menor. En las redes de comunicaciones ópticas actuales se utiliza la tecnología de multimplexación en longitud de onda (WDM) que obliga al uso de filtros ópticos con bandas de paso lo más estrechas posibles y a emplear una serie de dispositivos que incorporan filtros en su arquitectura, tales como los multiplexores, demultiplexores, ROADMs, conmutadores y OXCs. Todos estos dispositivos conectados entre sí son equivalentes a una cadena de filtros cuyo ancho de banda se va haciendo cada vez más estrecho, llegando a distorsionar la forma de onda de las señales. Por esto, además de analizar el impacto del filtrado óptico en las señales de 40 Gbps DQPSK y 100 Gbps PM-DQPSK, este trabajo de tesis se completa estudiando qué tipo de filtro óptico minimiza las degradaciones causadas en la señal y analizando el número máximo de filtros concatenados que permiten mantener la calidad requerida al sistema. Se han estudiado y simulado cuatro tipos de filtros ópticos;Butterworth, Bessel, FBG y F-P. ABSTRACT The objective of this thesis is the design and optimization of optical fiber-based phase shift keying (PSK) demodulators for high-bit-rate optical networks. PSK modulation formats have attracted significant attention in recent years, because of the better performance with respect to conventional modulation formats. Principally, PSK signals can improve spectrum efficiency and tolerate more signal degradation caused by chromatic dispersion, polarization mode dispersion and nonlinearities in the fiber. In this work, many PSK formats were analyzed in detail, including the variants of differential phase modulation (Differential Phase Shift Keying, DPSK), in quadrature (Differential Quadrature Phase Shift Keying, DQPSK) and polarization multiplexing (Polarization Multiplexing Differential Quadrature Phase Shift Keying, PM-DQPSK), in order to design and optimize receivers enabling demodulations. Therefore, novel structures, which offer good receiver performances and a reduction in cost compared to the current structures, have been analyzed and developed. Two novel receivers based on an all-fiber in-line Mach-Zehnder interferometer (MZI) were proposed for DPSK signal demodulation in this thesis. The operating principle of the all-fiber MZI is based on the modal interference that occurs in a multimode fiber (MMF) when it is located between two single-mode fibers (SMFs). This type of configuration (Single-mode-multimode-single-mode, SMS) can provide a good extinction ratio if the incoming power from the SMF could be coupled equally into two dominant modes excited in the MMF. In order to improve the interference extinction ratio, two novel SMS structures have been studied and demonstrated, theoretically and experimentally. One of the two proposed MZIs is based on a graded-index multimode fiber (MMF) with a central dip in the index profile, located between two single-mode fibers (SMFs). The other one is based on a conventional graded-index MMF mismatch spliced between two SMFs. Theoretical analysis has shown that, in these two schemes, 80 – 90% of the incoming power can be coupled into the two dominant modes exited in the MMF, and the power difference between them is only ~10%. Experimental results show that interference extinction ratio of 12 dB could be obtained. In order to demonstrate the capacity of these two structures for use as DPSK signal demodulators, numerical simulations in a completed optical transmission system have been carried out, and the receiver quality has been analyzed under different perspectives, such as sensitivity, tolerance to severe optical filtering or tolerance to chromatic and polarization mode dispersion. In all cases, from the simulation results we can conclude that the two proposed receivers can provide performances comparable to conventional ones. In this thesis, an alternative design for the implementation of a DQPSK receiver, which is based on a polarization maintaining fiber (PMF), was also presented. To complement the work made for the PMF-based DQPSK receiver, the study of the demodulation principle has been extended to demodulate PM-DQPSK signals, resulting in the proposal of a novel demodulation structure. The proposed PM-DQPSK receiver is based on only one delay line and a polarization rotator. The quality of the proposed DQPSK and PM-DQPSK receivers under different perspectives, such as sensitivity, tolerance to severe optical filtering, tolerance to chromatic dispersion and polarization mode dispersion, or behavior under non-ideal conditions. Compared with the conventional receivers, our proposals exhibit similar performances but allow a simpler design which can potentially reduce the cost. The wavelength division multiplexing (WDM) technology used in current optical communications networks requires the use of optical filters with a passband as narrow as possible, and the use of a series of devices that incorporate filters in their architecture, such as multiplexers, demultiplexers, switches, reconfigurable add-drop multiplexers (ROADMs) and optical cross-connects (OXCs). All these devices connected together are equivalent to a chain of filters whose bandwidth becomes increasingly narrow, resulting in distortion to the waveform of the signals. Therefore, in addition to analyzing the impact of optical filtering on signal of 40 Gbps DQPSK and 100 Gbps PM-DQPSK, we study which kind of optical filter minimizes the signal degradation and analyze the maximum number of concatenated filters for maintaining the required quality of the system. Four types of optical filters, including Butterworth, Bessel, FBG and FP, have studied and simulated.

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Advanced optical modulation format polarization-division multiplexed quadrature phase shift keying (PDM-QPSK) has become a key ingredient in the design of 100 and 200-Gb/s dense wavelength-division multiplexed (DWDM) networks. The performance of this format varies according to the shape of the pulses employed by the optical carrier: non-return to zero (NRZ), return to zero (RZ) or carrier-suppressed return to zero (CSRZ). In this paper we analyze the tolerance of PDM-QPSK to linear and nonlinear optical impairments: amplified spontaneous emission (ASE) noise, crosstalk, distortion by optical filtering, chromatic dispersion (CD), polarization mode dispersion (PMD) and fiber Kerr nonlinearities. RZ formats with a low duty cycle value reduce pulse-to-pulse interaction obtaining a higher tolerance to CD, PMD and intrachannel nonlinearities.

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We propose and demonstrate a low-cost alternative scheme of direct-detection to detect a 100Gbps polarization-multiplexed differential quadrature phase-shift keying (PM-DQPSK) signal. The proposed scheme is based on a delay line and a polarization rotator; the phase-shift keying signal is first converted into a polarization shift keying signal. Then, this signal is converted into an intensity modulated signal by a polarization beam splitter. Finally, the intensity-modulated signal is detected by balanced photodetectors. In order to demonstrate that our proposed receiver is suitable for using as a PM-DQPSK demodulator, a set of simulations have been performed. In addition to testing the sensitivity, the performance under various impairments, including narrow optical filtering, polarization mode dispersion, chromatic dispersion and polarization sensitivity, is analyzed. The simulation results show that our performance receiver is as good as a conventional receiver based on four delay interferometers. Moreover, in comparison with the typical receiver, fewer components are used in our receiver. Hence, implementation is easier, and total cost is reduced. In addition, our receiver can be easily improved to a bit-rate tunable receiver.

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In this paper, the design and experimental characterization of a tunable microstrip bandpass filter based on liquid crystal technology are presented. A reshaped microstrip dual-mode filter structure has been used in order to improve the device performance. Specifically, the aim is to increase the pass-band return loss of the filter by narrowing the filter bandwidth. Simulations confirm the improvement of using this new structure, achieving a pass-band return loss increase of 1.5 dB at least. Because of the anisotropic properties of LC molecules, a filter central frequency shift from 4.688 GHz to 5.045 GHz, which means a relative tuning range of 7.3%, is measured when an external AC voltage from 0 Vrms to 15 Vrms is applied to the device.

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Foliage Penetration (FOPEN) radar systems were introduced in 1960, and have been constantly improved by several organizations since that time. The use of Synthetic Aperture Radar (SAR) approaches for this application has important advantages, due to the need for high resolution in two dimensions. The design of this type of systems, however, includes some complications that are not present in standard SAR systems. FOPEN SAR systems need to operate with a low central frequency (VHF or UHF bands) in order to be able to penetrate the foliage. High bandwidth is also required to obtain high resolution. Due to the low central frequency, large integration angles are required during SAR image formation, and therefore the Range Migration Algorithm (RMA) is used. This project thesis identifies the three main complications that arise due to these requirements. First, a high fractional bandwidth makes narrowband propagation models no longer valid. Second, the VHF and UHF bands are used by many communications systems. The transmitted signal spectrum needs to be notched to avoid interfering them. Third, those communications systems cause Radio Frequency Interference (RFI) on the received signal. The thesis carries out a thorough analysis of the three problems, their degrading effects and possible solutions to compensate them. The UWB model is applied to the SAR signal, and the degradation induced by it is derived. The result is tested through simulation of both a single pulse stretch processor and the complete RMA image formation. Both methods show that the degradation is negligible, and therefore the UWB propagation effect does not need compensation. A technique is derived to design a notched transmitted signal. Then, its effect on the SAR image formation is evaluated analytically. It is shown that the stretch processor introduces a processing gain that reduces the degrading effects of the notches. The remaining degrading effect after processing gain is assessed through simulation, and an experimental graph of degradation as a function of percentage of nulled frequencies is obtained. The RFI is characterized and its effect on the SAR processor is derived. Once again, a processing gain is found to be introduced by the receiver. As the RFI power can be much higher than that of the desired signal, an algorithm is proposed to remove the RFI from the received signal before RMA processing. This algorithm is a modification of the Chirp Least Squares Algorithm (CLSA) explained in [4], which adapts it to deramped signals. The algorithm is derived analytically and then its performance is evaluated through simulation, showing that it is effective in removing the RFI and reducing the degradation caused by both RFI and notching. Finally, conclusions are drawn as to the importance of each one of the problems in SAR system design.

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El requerimiento de proveer alta frecuencia de datos en los modernos sistema de comunicación inalámbricos resulta en complejas señales moduladas de radio-frequencia (RF) con un gran ancho de banda y alto ratio pico-promedio (PAPR). Para garantizar la linealidad del comportamiento, los amplificadores lineales de potencia comunes funcionan típicamente entre 4 y 10 dB de back-o_ desde la máxima potencia de salida, ocasionando una baja eficiencia del sistema. La eliminación y restauración de la evolvente (EER) y el seguimiento de la evolvente (ET) son dos prometedoras técnicas para resolver el problema de la eficiencia. Tanto en EER como en ET, es complicado diseñar un amplificador de potencia que sea eficiente para señales de RF de alto ancho de banda y alto PAPR. Una propuesta común para los amplificadores de potencia es incluir un convertidor de potencia de muy alta eficiencia operando a frecuencias más altas que el ancho de banda de la señal RF. En este caso, la potencia perdida del convertidor ocasionado por la alta frecuencia desaconseja su práctica cuando el ancho de banda es muy alto. La solución a este problema es el enfoque de esta disertación que presenta dos arquitecturas de amplificador evolvente: convertidor híbrido-serie con una técnica de evolvente lenta y un convertidor multinivel basado en un convertidor reductor multifase con control de tiempo mínimo. En la primera arquitectura, una topología híbrida está compuesta de una convertidor reductor conmutado y un regulador lineal en serie que trabajan juntos para ajustar la tensión de salida para seguir a la evolvente con precisión. Un algoritmo de generación de una evolvente lenta crea una forma de onda con una pendiente limitada que es menor que la pendiente máxima de la evolvente original. La salida del convertidor reductor sigue esa forma de onda en vez de la evolvente original usando una menor frecuencia de conmutación, porque la forma de onda no sólo tiene una pendiente reducida sino también un menor ancho de banda. De esta forma, el regulador lineal se usa para filtrar la forma de onda tiene una pérdida de potencia adicional. Dependiendo de cuánto se puede reducir la pendiente de la evolvente para producir la forma de onda, existe un trade-off entre la pérdida de potencia del convertidor reductor relacionada con la frecuencia de conmutación y el regulador lineal. El punto óptimo referido a la menor pérdida de potencia total del amplificador de evolvente es capaz de identificarse con la ayuda de modelo preciso de pérdidas que es una combinación de modelos comportamentales y analíticos de pérdidas. Además, se analiza el efecto en la respuesta del filtro de salida del convertidor reductor. Un filtro de dampeo paralelo extra es necesario para eliminar la oscilación resonante del filtro de salida porque el convertidor reductor opera en lazo abierto. La segunda arquitectura es un amplificador de evolvente de seguimiento de tensión multinivel. Al contrario que los convertidores que usan multi-fuentes, un convertidor reductor multifase se emplea para generar la tensión multinivel. En régimen permanente, el convertidor reductor opera en puntos del ciclo de trabajo con cancelación completa del rizado. El número de niveles de tensión es igual al número de fases de acuerdo a las características del entrelazamiento del convertidor reductor. En la transición, un control de tiempo mínimo (MTC) para convertidores multifase es novedosamente propuesto y desarrollado para cambiar la tensión de salida del convertidor reductor entre diferentes niveles. A diferencia de controles convencionales de tiempo mínimo para convertidores multifase con inductancia equivalente, el propuesto MTC considera el rizado de corriente por cada fase basado en un desfase fijo que resulta en diferentes esquemas de control entre las fases. La ventaja de este control es que todas las corrientes vuelven a su fase en régimen permanente después de la transición para que la siguiente transición pueda empezar muy pronto, lo que es muy favorable para la aplicación de seguimiento de tensión multinivel. Además, el control es independiente de la carga y no es afectado por corrientes de fase desbalanceadas. Al igual que en la primera arquitectura, hay una etapa lineal con la misma función, conectada en serie con el convertidor reductor multifase. Dado que tanto el régimen permanente como el estado de transición del convertidor no están fuertemente relacionados con la frecuencia de conmutación, la frecuencia de conmutación puede ser reducida para el alto ancho de banda de la evolvente, la cual es la principal consideración de esta arquitectura. La optimización de la segunda arquitectura para más alto anchos de banda de la evolvente es presentada incluyendo el diseño del filtro de salida, la frecuencia de conmutación y el número de fases. El área de diseño del filtro está restringido por la transición rápida y el mínimo pulso del hardware. La rápida transición necesita un filtro pequeño pero la limitación del pulso mínimo del hardware lleva el diseño en el sentido contrario. La frecuencia de conmutación del convertidor afecta principalmente a la limitación del mínimo pulso y a las pérdidas de potencia. Con una menor frecuencia de conmutación, el ancho de pulso en la transición es más pequeño. El número de fases relativo a la aplicación específica puede ser optimizado en términos de la eficiencia global. Otro aspecto de la optimización es mejorar la estrategia de control. La transición permite seguir algunas partes de la evolvente que son más rápidas de lo que el hardware puede soportar al precio de complejidad. El nuevo método de sincronización de la transición incrementa la frecuencia de la transición, permitiendo que la tensión multinivel esté más cerca de la evolvente. Ambas estrategias permiten que el convertidor pueda seguir una evolvente con un ancho de banda más alto que la limitación de la etapa de potencia. El modelo de pérdidas del amplificador de evolvente se ha detallado y validado mediante medidas. El mecanismo de pérdidas de potencia del convertidor reductor tiene que incluir las transiciones en tiempo real, lo cual es diferente del clásico modelos de pérdidas de un convertidor reductor síncrono. Este modelo estima la eficiencia del sistema y juega un papel muy importante en el proceso de optimización. Finalmente, la segunda arquitectura del amplificador de evolvente se integra con el amplificador de clase F. La medida del sistema EER prueba el ahorro de energía con el amplificador de evolvente propuesto sin perjudicar la linealidad del sistema. ABSTRACT The requirement of delivering high data rates in modern wireless communication systems results in complex modulated RF signals with wide bandwidth and high peak-to-average ratio (PAPR). In order to guarantee the linearity performance, the conventional linear power amplifiers typically work at 4 to 10 dB back-off from the maximum output power, leading to low system efficiency. The envelope elimination and restoration (EER) and envelope tracking (ET) are two promising techniques to overcome the efficiency problem. In both EER and ET, it is challenging to design efficient envelope amplifier for wide bandwidth and high PAPR RF signals. An usual approach for envelope amplifier includes a high-efficiency switching power converter operating at a frequency higher than the RF signal's bandwidth. In this case, the power loss of converter caused by high switching operation becomes unbearable for system efficiency when signal bandwidth is very wide. The solution of this problem is the focus of this dissertation that presents two architectures of envelope amplifier: a hybrid series converter with slow-envelope technique and a multilevel converter based on a multiphase buck converter with the minimum time control. In the first architecture, a hybrid topology is composed of a switched buck converter and a linear regulator in series that work together to adjust the output voltage to track the envelope with accuracy. A slow envelope generation algorithm yields a waveform with limited slew rate that is lower than the maximum slew rate of the original envelope. The buck converter's output follows this waveform instead of the original envelope using lower switching frequency, because the waveform has not only reduced slew rate but also reduced bandwidth. In this way, the linear regulator used to filter the waveform has additional power loss. Depending on how much reduction of the slew rate of envelope in order to obtain that waveform, there is a trade-off between the power loss of buck converter related to the switching frequency and the power loss of linear regulator. The optimal point referring to the lowest total power loss of this envelope amplifier is identified with the help of a precise power loss model that is a combination of behavioral and analytic loss model. In addition, the output filter's effect on the response is analyzed. An extra parallel damping filter is needed to eliminate the resonant oscillation of output filter L and C, because the buck converter operates in open loop. The second architecture is a multilevel voltage tracking envelope amplifier. Unlike the converters using multi-sources, a multiphase buck converter is employed to generate the multilevel voltage. In the steady state, the buck converter operates at complete ripple cancellation points of duty cycle. The number of the voltage levels is equal to the number of phases according the characteristics of interleaved buck converter. In the transition, a minimum time control (MTC) for multiphase converter is originally proposed and developed for changing the output voltage of buck converter between different levels. As opposed to conventional minimum time control for multiphase converter with equivalent inductance, the proposed MTC considers the current ripple of each phase based on the fixed phase shift resulting in different control schemes among the phases. The advantage of this control is that all the phase current return to the steady state after the transition so that the next transition can be triggered very soon, which is very favorable for the application of multilevel voltage tracking. Besides, the control is independent on the load condition and not affected by the unbalance of phase current. Like the first architecture, there is also a linear stage with the same function, connected in series with the multiphase buck converter. Since both steady state and transition state of the converter are not strongly related to the switching frequency, it can be reduced for wide bandwidth envelope which is the main consideration of this architecture. The optimization of the second architecture for wider bandwidth envelope is presented including the output filter design, switching frequency and the number of phases. The filter design area is restrained by fast transition and the minimum pulse of hardware. The fast transition needs small filter but the minimum pulse of hardware limitation pushes the filter in opposite way. The converter switching frequency mainly affects the minimum pulse limitation and the power loss. With lower switching frequency, the pulse width in the transition is smaller. The number of phases related to specific application can be optimized in terms of overall efficiency. Another aspect of optimization is improving control strategy. Transition shift allows tracking some parts of envelope that are faster than the hardware can support at the price of complexity. The new transition synchronization method increases the frequency of transition, allowing the multilevel voltage to be closer to the envelope. Both control strategies push the converter to track wider bandwidth envelope than the limitation of power stage. The power loss model of envelope amplifier is detailed and validated by measurements. The power loss mechanism of buck converter has to include the transitions in real time operation, which is different from classical power loss model of synchronous buck converter. This model estimates the system efficiency and play a very important role in optimization process. Finally, the second envelope amplifier architecture is integrated with a Class F amplifier. EER system measurement proves the power saving with the proposed envelope amplifier without disrupting the linearity performance.

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The electroencephalograph (EEG) signal is one of the most widely used signals in the biomedicine field due to its rich information about human tasks. This research study describes a new approach based on i) build reference models from a set of time series, based on the analysis of the events that they contain, is suitable for domains where the relevant information is concentrated in specific regions of the time series, known as events. In order to deal with events, each event is characterized by a set of attributes. ii) Discrete wavelet transform to the EEG data in order to extract temporal information in the form of changes in the frequency domain over time- that is they are able to extract non-stationary signals embedded in the noisy background of the human brain. The performance of the model was evaluated in terms of training performance and classification accuracies and the results confirmed that the proposed scheme has potential in classifying the EEG signals.

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This paper presents a theoretical analysis of possible jitter impact in application of numeric criterion for fastmeasurement of frequency by coincidence principle. The primary goal is the generation of a signal containing a known amount of each jitter components. This signal was used for testing signals with regular pulse trains. Initially, jitter components are analyzed and modeled individually. Next, sequences for combining different kinds of jitter are modeled, simulated and evaluated. Jitter model simulation in Matlab is utilized to show the independence of frequencymeasurement results on the total jitter present in the reference and desired pulse trains independently. A good agreement between previously introduced theory of fastmeasurement of frequency and simulation in jitter presence is verified; these results allows to engineers use the numeric criterion for fastmeasurement of frequency in spite to interactions among jitter components in various applications for frequency domain sensors.

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An increasing number of neuroimaging studies are concerned with the identification of interactions or statistical dependencies between brain areas. Dependencies between the activities of different brain regions can be quantified with functional connectivity measures such as the cross-correlation coefficient. An important factor limiting the accuracy of such measures is the amount of empirical data available. For event-related protocols, the amount of data also affects the temporal resolution of the analysis. We use analytical expressions to calculate the amount of empirical data needed to establish whether a certain level of dependency is significant when the time series are autocorrelated, as is the case for biological signals. These analytical results are then contrasted with estimates from simulations based on real data recorded with magnetoencephalography during a resting-state paradigm and during the presentation of visual stimuli. Results indicate that, for broadband signals, 50–100 s of data is required to detect a true underlying cross-correlations coefficient of 0.05. This corresponds to a resolution of a few hundred milliseconds for typical event-related recordings. The required time window increases for narrow band signals as frequency decreases. For instance, approximately 3 times as much data is necessary for signals in the alpha band. Important implications can be derived for the design and interpretation of experiments to characterize weak interactions, which are potentially important for brain processing.

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We consider the problem of developing efficient sampling schemes for multiband sparse signals. Previous results on multicoset sampling implementations that lead to universal sampling patterns (which guarantee perfect reconstruction), are based on a set of appropriate interleaved analog to digital converters, all of them operating at the same sampling frequency. In this paper we propose an alternative multirate synchronous implementation of multicoset codes, that is, all the analog to digital converters in the sampling scheme operate at different sampling frequencies, without need of introducing any delay. The interleaving is achieved through the usage of different rates, whose sum is significantly lower than the Nyquist rate of the multiband signal. To obtain universal patterns the sampling matrix is formulated and analyzed. Appropriate choices of the parameters, that is the block length and the sampling rates, are also proposed.

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Esta tesis está incluida dentro del campo del campo de Multiband Orthogonal Frequency Division Multiplexing Ultra Wideband (MB-OFDM UWB), el cual ha adquirido una gran importancia en las comunicaciones inalámbricas de alta tasa de datos en la última década. UWB surgió con el objetivo de satisfacer la creciente demanda de conexiones inalámbricas en interiores y de uso doméstico, con bajo coste y alta velocidad. La disponibilidad de un ancho de banda grande, el potencial para alta velocidad de transmisión, baja complejidad y bajo consumo de energía, unido al bajo coste de implementación, representa una oportunidad única para que UWB se convierta en una solución ampliamente utilizada en aplicaciones de Wireless Personal Area Network (WPAN). UWB está definido como cualquier transmisión que ocupa un ancho de banda de más de 20% de su frecuencia central, o más de 500 MHz. En 2002, la Comisión Federal de Comunicaciones (FCC) definió que el rango de frecuencias de transmisión de UWB legal es de 3.1 a 10.6 GHz, con una energía de transmisión de -41.3 dBm/Hz. Bajo las directrices de FCC, el uso de la tecnología UWB puede aportar una enorme capacidad en las comunicaciones de corto alcance. Considerando las ecuaciones de capacidad de Shannon, incrementar la capacidad del canal requiere un incremento lineal en el ancho de banda, mientras que un aumento similar de la capacidad de canal requiere un aumento exponencial en la energía de transmisión. En los últimos años, s diferentes desarrollos del UWB han sido extensamente estudiados en diferentes áreas, entre los cuales, el protocolo de comunicaciones inalámbricas MB-OFDM UWB está considerado como la mejor elección y ha sido adoptado como estándar ISO/IEC para los WPANs. Combinando la modulación OFDM y la transmisión de datos utilizando las técnicas de salto de frecuencia, el sistema MB-OFDM UWB es capaz de soportar tasas de datos con que pueden variar de los 55 a los 480 Mbps, alcanzando una distancia máxima de hasta 10 metros. Se esperara que la tecnología MB-OFDM tenga un consumo energético muy bajo copando un are muy reducida en silicio, proporcionando soluciones de bajo coste que satisfagan las demandas del mercado. Para cumplir con todas estas expectativas, el desarrollo y la investigación del MBOFDM UWB deben enfrentarse a varios retos, como son la sincronización de alta sensibilidad, las restricciones de baja complejidad, las estrictas limitaciones energéticas, la escalabilidad y la flexibilidad. Tales retos requieren un procesamiento digital de la señal de última generación, capaz de desarrollar sistemas que puedan aprovechar por completo las ventajas del espectro UWB y proporcionar futuras aplicaciones inalámbricas en interiores. Esta tesis se centra en la completa optimización de un sistema de transceptor de banda base MB-OFDM UWB digital, cuyo objetivo es investigar y diseñar un subsistema de comunicación inalámbrica para la aplicación de las Redes de Sensores Inalámbricas Visuales. La complejidad inherente de los procesadores FFT/IFFT y el sistema de sincronización así como la alta frecuencia de operación para todos los elementos de procesamiento, se convierten en el cuello de la botella para el diseño y la implementación del sistema de UWB digital en base de banda basado en MB-OFDM de baja energía. El objetivo del transceptor propuesto es conseguir baja energía y baja complejidad bajo la premisa de un alto rendimiento. Las optimizaciones están realizadas tanto a nivel algorítmico como a nivel arquitectural para todos los elementos del sistema. Una arquitectura hardware eficiente en consumo se propone en primer lugar para aquellos módulos correspondientes a núcleos de computación. Para el procesado de la Transformada Rápida de Fourier (FFT/IFFT), se propone un algoritmo mixed-radix, basado en una arquitectura con pipeline y se ha desarrollado un módulo de Decodificador de Viterbi (VD) equilibrado en coste-velocidad con el objetivo de reducir el consumo energético e incrementar la velocidad de procesamiento. También se ha implementado un correlador signo-bit simple basado en la sincronización del tiempo de símbolo es presentado. Este correlador es usado para detectar y sincronizar los paquetes de OFDM de forma robusta y precisa. Para el desarrollo de los subsitemas de procesamiento y realizar la integración del sistema completo se han empleado tecnologías de última generación. El dispositivo utilizado para el sistema propuesto es una FPGA Virtex 5 XC5VLX110T del fabricante Xilinx. La validación el propuesta para el sistema transceptor se ha implementado en dicha placa de FPGA. En este trabajo se presenta un algoritmo, y una arquitectura, diseñado con filosofía de co-diseño hardware/software para el desarrollo de sistemas de FPGA complejos. El objetivo principal de la estrategia propuesta es de encontrar una metodología eficiente para el diseño de un sistema de FPGA configurable optimizado con el empleo del mínimo esfuerzo posible en el sistema de procedimiento de verificación, por tanto acelerar el periodo de desarrollo del sistema. La metodología de co-diseño presentada tiene la ventaja de ser fácil de usar, contiene todos los pasos desde la propuesta del algoritmo hasta la verificación del hardware, y puede ser ampliamente extendida para casi todos los tipos de desarrollos de FPGAs. En este trabajo se ha desarrollado sólo el sistema de transceptor digital de banda base por lo que la comprobación de señales transmitidas a través del canal inalámbrico en los entornos reales de comunicación sigue requiriendo componentes RF y un front-end analógico. No obstante, utilizando la metodología de co-simulación hardware/software citada anteriormente, es posible comunicar el sistema de transmisor y el receptor digital utilizando los modelos de canales propuestos por IEEE 802.15.3a, implementados en MATLAB. Por tanto, simplemente ajustando las características de cada modelo de canal, por ejemplo, un incremento del retraso y de la frecuencia central, podemos estimar el comportamiento del sistema propuesto en diferentes escenarios y entornos. Las mayores contribuciones de esta tesis son: • Se ha propuesto un nuevo algoritmo 128-puntos base mixto FFT usando la arquitectura pipeline multi-ruta. Los complejos multiplicadores para cada etapa de procesamiento son diseñados usando la arquitectura modificada shiftadd. Los sistemas word length y twiddle word length son comparados y seleccionados basándose en la señal para cuantización del SQNR y el análisis de energías. • El desempeño del procesador IFFT es analizado bajo diferentes situaciones aritméticas de bloques de punto flotante (BFP) para el control de desbordamiento, por tanto, para encontrar la arquitectura perfecta del algoritmo IFFT basado en el procesador FFT propuesto. • Para el sistema de receptor MB-OFDM UWB se ha empleado una sincronización del tiempo innovadora, de baja complejidad y esquema de compensación, que consiste en funciones de Detector de Paquetes (PD) y Estimación del Offset del tiempo. Simplificando el cross-correlation y maximizar las funciones probables solo a sign-bit, la complejidad computacional se ve reducida significativamente. • Se ha propuesto un sistema de decodificadores Viterbi de 64 estados de decisión-débil usando velocidad base-4 de arquitectura suma-comparaselecciona. El algoritmo Two-pointer Even también es introducido en la unidad de rastreador de origen con el objetivo de conseguir la eficiencia en el hardware. • Se han integrado varias tecnologías de última generación en el completo sistema transceptor basebanda , con el objetivo de implementar un sistema de comunicación UWB altamente optimizado. • Un diseño de flujo mejorado es propuesto para el complejo sistema de implementación, el cual puede ser usado para diseños de Cadena de puertas de campo programable general (FPGA). El diseño mencionado no sólo reduce dramáticamente el tiempo para la verificación funcional, sino también provee un análisis automático como los errores del retraso del output para el sistema de hardware implementado. • Un ambiente de comunicación virtual es establecido para la validación del propuesto sistema de transceptores MB-OFDM. Este método es provisto para facilitar el uso y la conveniencia de analizar el sistema digital de basebanda sin parte frontera analógica bajo diferentes ambientes de comunicación. Esta tesis doctoral está organizada en seis capítulos. En el primer capítulo se encuentra una breve introducción al campo del UWB, tanto relacionado con el proyecto como la motivación del desarrollo del sistema de MB-OFDM. En el capítulo 2, se presenta la información general y los requisitos del protocolo de comunicación inalámbrica MBOFDM UWB. En el capítulo 3 se habla de la arquitectura del sistema de transceptor digital MB-OFDM de banda base . El diseño del algoritmo propuesto y la arquitectura para cada elemento del procesamiento está detallado en este capítulo. Los retos de diseño del sistema que involucra un compromiso de discusión entre la complejidad de diseño, el consumo de energía, el coste de hardware, el desempeño del sistema, y otros aspectos. En el capítulo 4, se ha descrito la co-diseñada metodología de hardware/software. Cada parte del flujo del diseño será detallado con algunos ejemplos que se ha hecho durante el desarrollo del sistema. Aprovechando esta estrategia de diseño, el procedimiento de comunicación virtual es llevado a cabo para probar y analizar la arquitectura del transceptor propuesto. Los resultados experimentales de la co-simulación y el informe sintético de la implementación del sistema FPGA son reflejados en el capítulo 5. Finalmente, en el capítulo 6 se incluye las conclusiones y los futuros proyectos, y también los resultados derivados de este proyecto de doctorado. ABSTRACT In recent years, the Wireless Visual Sensor Network (WVSN) has drawn great interest in wireless communication research area. They enable a wealth of new applications such as building security control, image sensing, and target localization. However, nowadays wireless communication protocols (ZigBee, Wi-Fi, and Bluetooth for example) cannot fully satisfy the demands of high data rate, low power consumption, short range, and high robustness requirements. New communication protocol is highly desired for such kind of applications. The Ultra Wideband (UWB) wireless communication protocol, which has increased in importance for high data rate wireless communication field, are emerging as an important topic for WVSN research. UWB has emerged as a technology that offers great promise to satisfy the growing demand for low-cost, high-speed digital wireless indoor and home networks. The large bandwidth available, the potential for high data rate transmission, and the potential for low complexity and low power consumption, along with low implementation cost, all present a unique opportunity for UWB to become a widely adopted radio solution for future Wireless Personal Area Network (WPAN) applications. UWB is defined as any transmission that occupies a bandwidth of more than 20% of its center frequency, or more than 500 MHz. In 2002, the Federal Communications Commission (FCC) has mandated that UWB radio transmission can legally operate in the range from 3.1 to 10.6 GHz at a transmitter power of -41.3 dBm/Hz. Under the FCC guidelines, the use of UWB technology can provide enormous capacity over short communication ranges. Considering Shannon’s capacity equations, increasing the channel capacity requires linear increasing in bandwidth, whereas similar channel capacity increases would require exponential increases in transmission power. In recent years, several different UWB developments has been widely studied in different area, among which, the MB-OFDM UWB wireless communication protocol is considered to be the leading choice and has recently been adopted in the ISO/IEC standard for WPANs. By combing the OFDM modulation and data transmission using frequency hopping techniques, the MB-OFDM UWB system is able to support various data rates, ranging from 55 to 480 Mbps, over distances up to 10 meters. The MB-OFDM technology is expected to consume very little power and silicon area, as well as provide low-cost solutions that can satisfy consumer market demands. To fulfill these expectations, MB-OFDM UWB research and development have to cope with several challenges, which consist of high-sensitivity synchronization, low- complexity constraints, strict power limitations, scalability, and flexibility. Such challenges require state-of-the-art digital signal processing expertise to develop systems that could fully take advantages of the UWB spectrum and support future indoor wireless applications. This thesis focuses on fully optimization for the MB-OFDM UWB digital baseband transceiver system, aiming at researching and designing a wireless communication subsystem for the Wireless Visual Sensor Networks (WVSNs) application. The inherent high complexity of the FFT/IFFT processor and synchronization system, and high operation frequency for all processing elements, becomes the bottleneck for low power MB-OFDM based UWB digital baseband system hardware design and implementation. The proposed transceiver system targets low power and low complexity under the premise of high performance. Optimizations are made at both algorithm and architecture level for each element of the transceiver system. The low-power hardwareefficient structures are firstly proposed for those core computation modules, i.e., the mixed-radix algorithm based pipelined architecture is proposed for the Fast Fourier Transform (FFT/IFFT) processor, and the cost-speed balanced Viterbi Decoder (VD) module is developed, in the aim of lowering the power consumption and increasing the processing speed. In addition, a low complexity sign-bit correlation based symbol timing synchronization scheme is presented so as to detect and synchronize the OFDM packets robustly and accurately. Moreover, several state-of-the-art technologies are used for developing other processing subsystems and an entire MB-OFDM digital baseband transceiver system is integrated. The target device for the proposed transceiver system is Xilinx Virtex 5 XC5VLX110T FPGA board. In order to validate the proposed transceiver system in the FPGA board, a unified algorithm-architecture-circuit hardware/software co-design environment for complex FPGA system development is presented in this work. The main objective of the proposed strategy is to find an efficient methodology for designing a configurable optimized FPGA system by using as few efforts as possible in system verification procedure, so as to speed up the system development period. The presented co-design methodology has the advantages of easy to use, covering all steps from algorithm proposal to hardware verification, and widely spread for almost all kinds of FPGA developments. Because only the digital baseband transceiver system is developed in this thesis, the validation of transmitting signals through wireless channel in real communication environments still requires the analog front-end and RF components. However, by using the aforementioned hardware/software co-simulation methodology, the transmitter and receiver digital baseband systems get the opportunity to communicate with each other through the channel models, which are proposed from the IEEE 802.15.3a research group, established in MATLAB. Thus, by simply adjust the characteristics of each channel model, e.g. mean excess delay and center frequency, we can estimate the transmission performance of the proposed transceiver system through different communication situations. The main contributions of this thesis are: • A novel mixed radix 128-point FFT algorithm by using multipath pipelined architecture is proposed. The complex multipliers for each processing stage are designed by using modified shift-add architectures. The system wordlength and twiddle word-length are compared and selected based on Signal to Quantization Noise Ratio (SQNR) and power analysis. • IFFT processor performance is analyzed under different Block Floating Point (BFP) arithmetic situations for overflow control, so as to find out the perfect architecture of IFFT algorithm based on the proposed FFT processor. • An innovative low complex timing synchronization and compensation scheme, which consists of Packet Detector (PD) and Timing Offset Estimation (TOE) functions, for MB-OFDM UWB receiver system is employed. By simplifying the cross-correlation and maximum likelihood functions to signbit only, the computational complexity is significantly reduced. • A 64 state soft-decision Viterbi Decoder system by using high speed radix-4 Add-Compare-Select architecture is proposed. Two-pointer Even algorithm is also introduced into the Trace Back unit in the aim of hardware-efficiency. • Several state-of-the-art technologies are integrated into the complete baseband transceiver system, in the aim of implementing a highly-optimized UWB communication system. • An improved design flow is proposed for complex system implementation which can be used for general Field-Programmable Gate Array (FPGA) designs. The design method not only dramatically reduces the time for functional verification, but also provides automatic analysis such as errors and output delays for the implemented hardware systems. • A virtual communication environment is established for validating the proposed MB-OFDM transceiver system. This methodology is proved to be easy for usage and convenient for analyzing the digital baseband system without analog frontend under different communication environments. This PhD thesis is organized in six chapters. In the chapter 1 a brief introduction to the UWB field, as well as the related work, is done, along with the motivation of MBOFDM system development. In the chapter 2, the general information and requirement of MB-OFDM UWB wireless communication protocol is presented. In the chapter 3, the architecture of the MB-OFDM digital baseband transceiver system is presented. The design of the proposed algorithm and architecture for each processing element is detailed in this chapter. Design challenges of such system involve trade-off discussions among design complexity, power consumption, hardware cost, system performance, and some other aspects. All these factors are analyzed and discussed. In the chapter 4, the hardware/software co-design methodology is proposed. Each step of this design flow will be detailed by taking some examples that we met during system development. Then, taking advantages of this design strategy, the Virtual Communication procedure is carried out so as to test and analyze the proposed transceiver architecture. Experimental results from the co-simulation and synthesis report of the implemented FPGA system are given in the chapter 5. The chapter 6 includes conclusions and future work, as well as the results derived from this PhD work.