Proposal of an Alternative Model for Speed-Flow Relationship in Two-Lane Highways

A research has been carried out in two-lanehighways in the Madrid Region to propose an alternativemodel for the speed-flowrelationship using regular loop data. The model is different in shape and, in some cases, slopes with respect to the contents of Highway Capacity Manual (HCM). A model is proposed for a mountainous area road, something for which the HCM does not provide explicitly a solution. The problem of a mountain road with high flows to access a popular recreational area is discussed, and some solutions are proposed. Up to 7 one-way sections of two-lanehighways have been selected, aiming at covering a significant number of different characteristics, to verify the proposed method the different classes of highways on which the Manual classifies them. In order to enunciate the model and to verify the basic variables of these types of roads a high number of data have been used. The counts were collected in the same way that the Madrid Region Highway Agency performs their counts. A total of 1.471 hours have been collected, in periods of 5 minutes. The models have been verified by means of specific statistical test (R2, T-Student, Durbin-Watson, ANOVA, etc.) and with the diagnostics of the contrast of assumptions (normality, linearity, homoscedasticity and independence). The model proposed for this type of highways with base conditions, can explain the different behaviors as traffic volumes increase, and follows a polynomial multiple regression model of order 3, S shaped. As secondary results of this research, the levels of service and the capacities of this road have been measured with the 2000 HCM methodology, and the results discussed. © 2011 Published by Elsevier Ltd.

Novel Inductor‐less Conversion Strategy Based on Multiphase Transformer‐Coupled Converters: Analysis, Design and Applications

There are many the requirements that modern power converters should fulfill. Most of the applications where these converters are used, demand smaller converters with high efficiency, improved power density and a fast dynamic response. For instance, loads like microprocessors demand aggressive current steps with very high slew rates (100A/mus and higher); besides, during these load steps, the supply voltage of the microprocessor should be kept within tight limits in order to ensure its correct performance. The accomplishment of these requirements is not an easy task; complex solutions like advanced topologies - such as multiphase converters- as well as advanced control strategies are often needed. Besides, it is also necessary to operate the converter at high switching frequencies and to use capacitors with high capacitance and low ESR. Improving the dynamic response of power converters does not rely only on the control strategy but also the power topology should be suited to enable a fast dynamic response. Moreover, in later years, a fast dynamic response does not only mean accomplishing fast load steps but output voltage steps are gaining importance as well. At least, two applications that require fast voltage changes can be named: Low power microprocessors. In these devices, the voltage supply is changed according to the workload and the operating frequency of the microprocessor is changed at the same time. An important reduction in voltage dependent losses can be achieved with such changes. This technique is known as Dynamic Voltage Scaling (DVS). Another application where important energy savings can be achieved by means of changing the supply voltage are Radio Frequency Power Amplifiers. For example, RF architectures based on ‘Envelope Tracking’ and ‘Envelope Elimination and Restoration’ techniques can take advantage of voltage supply modulation and accomplish important energy savings in the power amplifier. However, in order to achieve these efficiency improvements, a power converter with high efficiency and high enough bandwidth (hundreds of kHz or even tens of MHz) is necessary in order to ensure an adequate supply voltage. The main objective of this Thesis is to improve the dynamic response of DC-DC converters from the point of view of the power topology. And the term dynamic response refers both to the load steps and the voltage steps; it is also interesting to modulate the output voltage of the converter with a specific bandwidth. In order to accomplish this, the question of what is it that limits the dynamic response of power converters should be answered. Analyzing this question leads to the conclusion that the dynamic response is limited by the power topology and specifically, by the filter inductance of the converter which is found in series between the input and the output of the converter. The series inductance is the one that determines the gain of the converter and provides the regulation capability. Although the energy stored in the filter inductance enables the regulation and the capability of filtering the output voltage, it imposes a limitation which is the concern of this Thesis. The series inductance stores energy and prevents the current from changing in a fast way, limiting the slew rate of the current through this inductor. Different solutions are proposed in the literature in order to reduce the limit imposed by the filter inductor. Many publications proposing new topologies and improvements to known topologies can be found in the literature. Also, complex control strategies are proposed with the objective of improving the dynamic response in power converters. In the proposed topologies, the energy stored in the series inductor is reduced; examples of these topologies are Multiphase converters, Buck converter operating at very high frequency or adding a low impedance path in parallel with the series inductance. Control techniques proposed in the literature, focus on adjusting the output voltage as fast as allowed by the power stage; examples of these control techniques are: hysteresis control, V 2 control, and minimum time control. In some of the proposed topologies, a reduction in the value of the series inductance is achieved and with this, the energy stored in this magnetic element is reduced; less stored energy means a faster dynamic response. However, in some cases (as in the high frequency Buck converter), the dynamic response is improved at the cost of worsening the efficiency. In this Thesis, a drastic solution is proposed: to completely eliminate the series inductance of the converter. This is a more radical solution when compared to those proposed in the literature. If the series inductance is eliminated, the regulation capability of the converter is limited which can make it difficult to use the topology in one-converter solutions; however, this topology is suitable for power architectures where the energy conversion is done by more than one converter. When the series inductor is eliminated from the converter, the current slew rate is no longer limited and it can be said that the dynamic response of the converter is independent from the switching frequency. This is the main advantage of eliminating the series inductor. The main objective, is to propose an energy conversion strategy that is done without series inductance. Without series inductance, no energy is stored between the input and the output of the converter and the dynamic response would be instantaneous if all the devices were ideal. If the energy transfer from the input to the output of the converter is done instantaneously when a load step occurs, conceptually it would not be necessary to store energy at the output of the converter (no output capacitor COUT would be needed) and if the input source is ideal, the input capacitor CIN would not be necessary. This last feature (no CIN with ideal VIN) is common to all power converters. However, when the concept is actually implemented, parasitic inductances such as leakage inductance of the transformer and the parasitic inductance of the PCB, cannot be avoided because they are inherent to the implementation of the converter. These parasitic elements do not affect significantly to the proposed concept. In this Thesis, it is proposed to operate the converter without series inductance in order to improve the dynamic response of the converter; however, on the other side, the continuous regulation capability of the converter is lost. It is said continuous because, as it will be explained throughout the Thesis, it is indeed possible to achieve discrete regulation; a converter without filter inductance and without energy stored in the magnetic element, is capable to achieve a limited number of output voltages. The changes between these output voltage levels are achieved in a fast way. The proposed energy conversion strategy is implemented by means of a multiphase converter where the coupling of the phases is done by discrete two-winding transformers instead of coupledinductors since transformers are, ideally, no energy storing elements. This idea is the main contribution of this Thesis. The feasibility of this energy conversion strategy is first analyzed and then verified by simulation and by the implementation of experimental prototypes. Once the strategy is proved valid, different options to implement the magnetic structure are analyzed. Three different discrete transformer arrangements are studied and implemented. A converter based on this energy conversion strategy would be designed with a different approach than the one used to design classic converters since an additional design degree of freedom is available. The switching frequency can be chosen according to the design specifications without penalizing the dynamic response or the efficiency. Low operating frequencies can be chosen in order to favor the efficiency; on the other hand, high operating frequencies (MHz) can be chosen in order to favor the size of the converter. For this reason, a particular design procedure is proposed for the ‘inductorless’ conversion strategy. Finally, applications where the features of the proposed conversion strategy (high efficiency with fast dynamic response) are advantageus, are proposed. For example, in two-stage power architectures where a high efficiency converter is needed as the first stage and there is a second stage that provides the fine regulation. Another example are RF power amplifiers where the voltage is modulated following an envelope reference in order to save power; in this application, a high efficiency converter, capable of achieving fast voltage steps is required. The main contributions of this Thesis are the following: The proposal of a conversion strategy that is done, ideally, without storing energy in the magnetic element. The validation and the implementation of the proposed energy conversion strategy. The study of different magnetic structures based on discrete transformers for the implementation of the proposed energy conversion strategy. To elaborate and validate a design procedure. To identify and validate applications for the proposed energy conversion strategy. It is important to remark that this work is done in collaboration with Intel. The particular features of the proposed conversion strategy enable the possibility of solving the problems related to microprocessor powering in a different way. For example, the high efficiency achieved with the proposed conversion strategy enables it as a good candidate to be used for power conditioning, as a first stage in a two-stage power architecture for powering microprocessors.

Problemática del ruido neutrónico

El objetivo del presente proyecto es identificar y definir la problemática del ruido neutrónico en el tratamiento y procesamiento de los canales de medida y tratamiento del flujo neutrónico interno y externo en los sistemas de control y protección de los reactores nucleares tipo PWR (que trabajan con agua a presión) que dan lugar a actuaciones indeseadas de los sistemas de vigilancia y control no relacionadas con situaciones reales del proceso como cambios significativos en los parámetros de temperatura y por lo tanto de potencia del reactor que reducen la disponibilidad de operación de la central y provocan transitorios no justificados por dichas actuaciones. Finalmente, se proponen algunas soluciones. Abstract The aim of this project is to identify and define the problem of neutron noise in PWR nuclear power plants, its influence on the treatment and processing of the measurement channels and external neutron flux treatment, its contributions to the control and protection systems that result in undesired actions of monitoring and control systems that are not related to the actual process conditions. These actions reduce the availability of plant operation and unjustified transient causes. Finally, some possible solutions are proposed

Estructuras espaciales desmontables y desplegables. Estudio de la obra del arquitecto Emilio Pérez Pinero.

La presente tesis estudia las realizaciones del arquitecto Emilio Pérez Pinero, todas dentro de las estructuras espaciales de barras desmontables y desplegables, elabora la documentación que hace transmisible su investigación y generaliza el estudio del comportamiento en la parcela de las desplegables. La obra de este arquitecto forma un conjunto original, atractivo y sin continuadores, y por otra parte, no abundan las" investigaciones sobre este tipo de estructuras ( mucho menos las realizaciones), en las que hay que resolver tanto su definición como su movilidad y comportamiento estructural. El contenido de la parte correspondiente a las estructuras desmontables se limita a las cúpulas reticuladas de una capa, con el sistema de reticulado y montaje ideado por Pinero, por considerar que se debe documentar su aportación pero no incidir mas en un campo de investigación que cuenta con abundantes estudios. Se aporta la solución matemática y un programa de ordenador para la definición geométrica completa del reticulado empleado. Las estructuras desplegables se caracterizan por el empleo de barras dispuestas en "x" en el espesor de la estructura, con generación de superficies tanto planas como curvas. En ambos casos se analiza la movilidad en fase de mecanismo, tanto a las soluciones de Pinero como a las complementarlas que se exponen. Se estudian las relaciones geométricas que deben de cumplirse para que sea posible el movimiento de las barras, relaciones particularmente complejas en las desplegables según superficies esféricas, y que determinan su definición geométrica. En la fase de estructura, además de analizar lo realizado por Pinero, documentando y definiendo sus componentes, se proponen varias estructuras posibles para cada mecanismo, y se desarrolla en detalle el tipo de los emparrillados de canto constante, donde se incluye un estudio comparativo de nueve variantes distintas. Se muestra el amplio campo de uso posible para estas estructuras. ABSTRACT The • present doctoral dissertation studies the work of de spanish architect Emilio Pérez Pinero, all of it within de field of spatial demountable and deployable structures. This contribution compiles the necessary documentation for research in this field and, besides, generalizes the theoretical background for the analysis of this type of structures. Pérez Pinero's contributions are original and attractive, but, so far, he has not any followers ; on the other hand research in this field is scarce (much less actual realizations). In the part corresponding to demountable structures the research is limited to reticulated domes of only one layer, following Pérez Pinero's sys~ tem, trying to give a comprehensive documentation of it. The mathematical solution is given and so is a computer program for the complete definition of the geometry of the structure. One characteristic of deployable structures is the use of struts placed - formix "X" in the thickness of the structure, making possible the generation of plañe as well as curved surfaces. In both cases, the operation in the phase of mechanism is studied, both fot Pinero's solution and for the other schemes presented. The geometrical relationships that must be maintained in order to guarantee strut's movements, are studied; these relationships are particularly complex in the case of spherical surfaces, and, in this last casey determine completely its geometrical definition. In regard of the structure behaviour, besides analysing Pinero's works, a variety of solutions are proposed for each mechanism. Particularly, the configuration for double layer grids of constant thickness is developed with great detall, and a comparative study of nine different solutions of this special case is included. A wide range of the possible applications of this structural type is shown.

A scaled-time test method

The Pseudo-Dynamic Test Method (PDTM) is being developped currently as an alternative to the shaking table testing of large size models. However, the stepped slow execution of the former type of test has been found to be the source of important errors arising from the stress relaxation. A new continuous test method, wich allows the selection of a suitable time-scale factor in the response in order to control these errors, es proposed here. Such scaled-time response is theoretically obtained by simply augmenting the mass of the structure for wich some practical solutions are proposed.

An alternative for reducing the layers in the construction of three-phase planar transformers

A modified winding layout for three-phase transformers with PCB windings is proposed in this paper. This modified layout can be used in high current transformers with many PCB layers to simplify the fabrication process. One of the key factors that might increase the cost and complexity in the construction of planar transformers is the number of layers of each PCB winding. This issue becomes even more important in medium-high power three-phase transformers, where the number of PCB layers is higher. In addition to that, the proposed method allows the use of commercial core shapes that are commonly used to design single-phase transformers. This fact makes possible the reduction of cost and flexibility of the design solutions. The proposed solution has been validated and compared using the conventional and the proposed methodologies to design a high power (20 kW) transformer.

Core physics and safety analysis of Generation-IV Sodium Fast Reactors using existing and newly developed computational tools

El futuro de la energía nuclear de fisión dependerá, entre otros factores, de la capacidad que las nuevas tecnologías demuestren para solventar los principales retos a largo plazo que se plantean. Los principales retos se pueden resumir en los siguientes aspectos: la capacidad de proporcionar una solución final, segura y fiable a los residuos radiactivos; así como dar solución a la limitación de recursos naturales necesarios para alimentar los reactores nucleares; y por último, una mejora robusta en la seguridad de las centrales que en definitiva evite cualquier daño potencial tanto en la población como en el medio ambiente como consecuencia de cualquier escenario imaginable o más allá de lo imaginable. Siguiendo estas motivaciones, la Generación IV de reactores nucleares surge con el compromiso de proporcionar electricidad de forma sostenible, segura, económica y evitando la proliferación de material fisible. Entre los sistemas conceptuales que se consideran para la Gen IV, los reactores rápidos destacan por su capacidad potencial de transmutar actínidos a la vez que permiten una utilización óptima de los recursos naturales. Entre los refrigerantes que se plantean, el sodio parece una de las soluciones más prometedoras. Como consecuencia, esta tesis surgió dentro del marco del proyecto europeo CP-ESFR con el principal objetivo de evaluar la física de núcleo y seguridad de los reactores rápidos refrigerados por sodio, al tiempo que se desarrollaron herramientas apropiadas para dichos análisis. Efectivamente, en una primera parte de la tesis, se abarca el estudio de la física del núcleo de un reactor rápido representativo, incluyendo el análisis detallado de la capacidad de transmutar actínidos minoritarios. Como resultado de dichos análisis, se publicó un artículo en la revista Annals of Nuclear Energy [96]. Por otra parte, a través de un análisis de un hipotético escenario nuclear español, se evalúo la disponibilidad de recursos naturales necesarios en el caso particular de España para alimentar una flota específica de reactores rápidos, siguiendo varios escenarios de demanda, y teniendo en cuenta la capacidad de reproducción de plutonio que tienen estos sistemas. Como resultado de este trabajo también surgió una publicación en otra revista científica de prestigio internacional como es Energy Conversion and Management [97]. Con objeto de realizar esos y otros análisis, se desarrollaron diversos modelos del núcleo del ESFR siguiendo varias configuraciones, y para diferentes códigos. Por otro lado, con objeto de poder realizar análisis de seguridad de reactores rápidos, son necesarias herramientas multidimensionales de alta fidelidad específicas para reactores rápidos. Dichas herramientas deben integrar fenómenos relacionados con la neutrónica y con la termo-hidráulica, entre otros, mediante una aproximación multi-física. Siguiendo este objetivo, se evalúo el código de difusión neutrónica ANDES para su aplicación a reactores rápidos. ANDES es un código de resolución nodal que se encuentra implementado dentro del sistema COBAYA3 y está basado en el método ACMFD. Por lo tanto, el método ACMFD fue sometido a una revisión en profundidad para evaluar su aptitud para la aplicación a reactores rápidos. Durante ese proceso, se identificaron determinadas limitaciones que se discutirán a lo largo de este trabajo, junto con los desarrollos que se han elaborado e implementado para la resolución de dichas dificultades. Por otra parte, se desarrolló satisfactoriamente el acomplamiento del código neutrónico ANDES con un código termo-hidráulico de subcanales llamado SUBCHANFLOW, desarrollado recientemente en el KIT. Como conclusión de esta parte, todos los desarrollos implementados son evaluados y verificados. En paralelo con esos desarrollos, se calcularon para el núcleo del ESFR las secciones eficaces en multigrupos homogeneizadas a nivel nodal, así como otros parámetros neutrónicos, mediante los códigos ERANOS, primero, y SERPENT, después. Dichos parámetros se utilizaron más adelante para realizar cálculos estacionarios con ANDES. Además, como consecuencia de la contribución de la UPM al paquete de seguridad del proyecto CP-ESFR, se calcularon mediante el código SERPENT los parámetros de cinética puntual que se necesitan introducir en los típicos códigos termo-hidráulicos de planta, para estudios de seguridad. En concreto, dichos parámetros sirvieron para el análisis del impacto que tienen los actínidos minoritarios en el comportamiento de transitorios. Concluyendo, la tesis presenta una aproximación sistemática y multidisciplinar aplicada al análisis de seguridad y comportamiento neutrónico de los reactores rápidos de sodio de la Gen-IV, usando herramientas de cálculo existentes y recién desarrolladas ad' hoc para tal aplicación. Se ha empleado una cantidad importante de tiempo en identificar limitaciones de los métodos nodales analíticos en su aplicación en multigrupos a reactores rápidos, y se proponen interesantes soluciones para abordarlas. ABSTRACT The future of nuclear reactors will depend, among other aspects, on the capability to solve the long-term challenges linked to this technology. These are the capability to provide a definite, safe and reliable solution to the nuclear wastes; the limitation of natural resources, needed to fuel the reactors; and last but not least, the improved safety, which would avoid any potential damage on the public and or environment as a consequence of any imaginable and beyond imaginable circumstance. Following these motivations, the IV Generation of nuclear reactors arises, with the aim to provide sustainable, safe, economic and proliferationresistant electricity. Among the systems considered for the Gen IV, fast reactors have a representative role thanks to their potential capacity to transmute actinides together with the optimal usage of natural resources, being the sodium fast reactors the most promising concept. As a consequence, this thesis was born in the framework of the CP-ESFR project with the generic aim of evaluating the core physics and safety of sodium fast reactors, as well as the development of the approppriated tools to perform such analyses. Indeed, in a first part of this thesis work, the main core physics of the representative sodium fast reactor are assessed, including a detailed analysis of the capability to transmute minor actinides. A part of the results obtained have been published in Annals of Nuclear Energy [96]. Moreover, by means of the analysis of a hypothetical Spanish nuclear scenario, the availability of natural resources required to deploy an specific fleet of fast reactor is assessed, taking into account the breeding properties of such systems. This work also led to a publication in Energy Conversion and Management [97]. In order to perform those and other analyses, several models of the ESFR core were created for different codes. On the other hand, in order to perform safety studies of sodium fast reactors, high fidelity multidimensional analysis tools for sodium fast reactors are required. Such tools should integrate neutronic and thermal-hydraulic phenomena in a multi-physics approach. Following this motivation, the neutron diffusion code ANDES is assessed for sodium fast reactor applications. ANDES is the nodal solver implemented inside the multigroup pin-by-pin diffusion COBAYA3 code, and is based on the analytical method ACMFD. Thus, the ACMFD was verified for SFR applications and while doing so, some limitations were encountered, which are discussed through this work. In order to solve those, some new developments are proposed and implemented in ANDES. Moreover, the code was satisfactorily coupled with the thermal-hydraulic code SUBCHANFLOW, recently developed at KIT. Finally, the different implementations are verified. In addition to those developments, the node homogenized multigroup cross sections and other neutron parameters were obtained for the ESFR core using ERANOS and SERPENT codes, and employed afterwards by ANDES to perform steady state calculations. Moreover, as a result of the UPM contribution to the safety package of the CP-ESFR project, the point kinetic parameters required by the typical plant thermal-hydraulic codes were computed for the ESFR core using SERPENT, which final aim was the assessment of the impact of minor actinides in transient behaviour. All in all, the thesis provides a systematic and multi-purpose approach applied to the assessment of safety and performance parameters of Generation-IV SFR, using existing and newly developed analytical tools. An important amount of time was employed in identifying the limitations that the analytical nodal diffusion methods present when applied to fast reactors following a multigroup approach, and interesting solutions are proposed in order to overcome them.

DERIVE and Linear Algebra

This work describes an experience with a methodology for learning based on competences in Linear Algebra for engineering students. The experience has been based in autonomous team work of students. DERIVE tutorials for Linear Algebra topics are provided to the students. They have to work with the tutorials as their homework. After, worksheets with exercises have been prepared to be solved by the students organized in teams, using DERIVE function previously defined in the tutorials. The students send to the instructor the solution of the proposed exercises and they fill a survey with their impressions about the following items: ease of use of the files, usefulness of the tutorials for understanding the mathematical topics and the time spent in the experience. As a final work, we have designed an activity directed to the interested students. They have to prepare a project, related with a real problem in Science and Engineering. The students are free to choose the topic and to develop it but they have to use DERIVE in the solution. Obviously they are guided by the instructor. Some examples of activities related with Orthogonal Transformations will be presented.

A toolbox with DERIVE: calculus on several variables, Applications of Computer Algebra

A toolbox is a set of procedures taking advantage of the computing power and graphical capacities of a CAS. With these procedures the students can solve math problems, apply mathematics to engineering or simply reinforce the learning of certain mathematical concepts. From the point of view of their construction, we can consider two types of toolboxes: (i) the closed box, built by the teacher, in which the utility files are provided to the students together with the respective tutorials and several worksheets with proposed exercises and problems,

El nuevo escenario global y un modelo de negocio para la industria naval militar del 2025

Los retos y oportunidades a los que se enfrentan las organizaciones y administraciones de las primeras décadas del siglo XXI se caracterizan por una serie de fuerzas perturbadoras como la globalización, el avance de las tecnologías emergentes y el desequilibrio económico, que están actuando como impulsores de la transformación del mercado. La acción conjunta de estos factores está obligando a todas las empresas industriales a tener que trabajar con mayores y más exigentes niveles de productividad planteándose continuamente como mejorar y lograr satisfacer los requerimientos de los clientes. De esta situación surge la necesidad de volver a plantearse de nuevo ¿quién es el cliente?, ¿qué valora el cliente? y ¿cómo se pueden generan beneficios sostenibles? La aplicación de esta reflexión a la industria naval militar marca los objetivos a los que esta tesis doctoral busca dar respuesta. El primer objetivo, de carácter general, consiste en la definición de un modelo de negocio sostenible para la industria naval militar del 2025 que se adapte a los requisitos del cliente y al nuevo escenario político, económico, social, tecnológico y ambiental que rodea esta industria. El segundo objetivo, consecuencia del modelo general, trata de desarrollar una metodología para ejecutar programas de apoyo al ciclo de vida del “buque militar”. La investigación se estructura en cuatro partes: en la primera se justifica, por un lado, la necesidad del cambio de modelo y por otro se identifican los factores estructurantes para la definición del modelo. La segunda parte revisa la literatura existente sobre uno de los aspectos básicos para el nuevo modelo, el concepto Producto-Servicio. La tercera parte se centra totalmente en la industria naval militar estudiando los aspectos concretos del sector y, en base al trabajo de campo realizado, se identifican los puntos que más valoran las Marinas de Guerra y como estas gestionan al buque militar durante todo su ciclo de vida. Por último se presentan los principios del modelo propuesto y se desarrollan los pilares básicos para la ejecución de proyectos de Apoyo al Ciclo de Vida (ACV). Como resultado de la investigación, el modelo propuesto para la industria naval militar se fundamenta en once principios: 1. El buque militar (producto de alto valor añadido) debe ser diseñado y construido en un astillero del país que desarrolla el programa de defensa. 2. El diseño tiene que estar orientado al valor para el cliente, es decir, se tiene que diseñar el buque militar para que cumpla su misión, eficaz y eficientemente, durante toda su vida operativa, asegurando la seguridad del buque y de las personas y protegiendo el medio ambiente de acuerdo con las regulaciones vigentes. 3. La empresa debe suministrar soluciones integrales de apoyo al ciclo de vida al producto. 4. Desarrollar y mantener las capacidades de integración de sistemas complejos para todo el ciclo de vida del buque militar. 5. Incorporar las tecnologías digitales al producto, a los procesos, a las personas y al propio modelo de negocio. 6. Desarrollar planes de actuación con el cliente domestico a largo plazo. Estos planes tienen que estar basados en tres premisas: (i) deben incluir el ciclo de vida completo, desde la fase de investigación y desarrollo hasta la retirada del buque del servicio; (ii) la demanda debe ser sofisticada, es decir las exigencias del cliente, tanto desde la óptica de producto como de eficiencia, “tiran” del contratista y (iii) permitir el mantenimiento del nivel tecnológico y de las capacidades industriales de la compañía a futuro y posicionarla para que pueda competir en el mercado de exportación. 7. Impulsar el sector militar de exportación mediante una mayor actividad comercial a nivel internacional. 8. Fomentar la multilocalización ya que representa una oportunidad de crecimiento y favorece la exportación posibilitando el suministro de soluciones integrales en el país destino. 9. Reforzar la diplomacia institucional como palanca para la exportación. 10. Potenciar el liderazgo tecnológico tanto en producto como en procesos con políticas activas de I + D+ i. 11. Reforzar la capacidad de financiación con soluciones innovadoras. El segundo objetivo de esta tesis se centra en el desarrollo de soluciones integrales de Apoyo al Ciclo de Vida (ACV). La metodología planteada trata de minimizar la brecha entre capacidades y necesidades a lo largo de la vida operativa del barco. Es decir, el objetivo principal de los programas de ACV es que la unidad conserve durante toda su vida operativa, en términos relativos a las tecnologías existentes, las capacidades equivalentes a las que tendrá cuando entre en servicio. Los ejes de actuación para conseguir que un programa de Apoyo al Ciclo de Vida cumpla su objetivo son: el diseño orientado al valor, la ingeniería de Apoyo al Ciclo de Vida, los proyectos de refresco de tecnología, el mantenimiento Inteligente y los contratos basados en prestaciones. ABSTRACT On the first decades of the 21st century, organizations and administrations face challenges and come across opportunities threatened by a number of disruptive forces such as globalization, the ever-changing emerging technologies and the economic imbalances acting as drivers of the market transformation. This combination of factors is forcing all industrial companies to have more and higher demanding productivity levels, while bearing always in mind how to improve and meet the customer’s requirements. In this situation, we need to question ourselves again: Who is the customer? What does the customer value? And how can we deliver sustainable economic benefits? Considering this matter in a military naval industry framework sets the goals that this thesis intends to achieve. The first general goal is the definition of a new sustainable business model for the 2025 naval industry, adapted to the customer requirements and the new political, economic, social, technological and environmental scenario. And the second goal that arises as a consequence of the general model develops a methodology to implement “warship” through life support programs. The research is divided in four parts: the first one justifies, on the one hand, the need to change the existing model and, on the other, identifies the model structural factors. On the second part, current literature regarding one of the key issues on the new model (the Product-Service concept) is reviewed. Based on field research, the third part focuses entirely on military shipbuilding, analyzing specific key aspects of this field and identifying which of them are valued the most by Navies and how they manage through life cycles of warships. Finally, the foundation of the proposed model is presented and also the basic grounds for implementing a Through Life Support (TLS) program are developed. As a result of this research, the proposed model for the naval industry is based on eleven (11) key principles: 1. The warship (a high added value product) must be designed and built in a shipyard at the country developing the defense program. 2. Design must be customer value oriented, i.e.warship must be designed to effectively fulfill its mission throughout its operational life, ensuring safety at the ship and for the people and protecting the environment in accordance with current regulations. 3. The industry has to provide integrated Through Life Support solutions. 4. Develop and maintain integrated complex systems capabilities for the entire warship life cycle. 5. Introduce the product, processes, people and business model itself to digital technologies. 6. Develop long-term action plans with the domestic customer. These plans must be based on three premises: (i) the complete life cycle must be included, starting from the research and development stage throughout the ship’s disposal; (ii) customer demand has to be sophisticated, i.e. customer requirements, both from the efficiency and product perspective, "attract" the contractor and (iii) technological level and manufacturing capabilities of the company in the future must be maintained and a competitive position on the export market has to be achieved. 7. Promote the military exporting sector through increased international business. 8. Develop contractor multi-location as it entails an opportunity for growth and promote export opportunities providing integrated solutions in the customer's country. 9. Strengthen institutional diplomacy as a lever for export. 10. Promote technological leadership in both product and processes with active R & D & I policies (Research & Development & Innovation) 11. Strengthen financing capacity through innovative solutions. The second goal of this thesis is focused on developing integrated Through Life Support (TLS) solutions. The proposed methodology tries to minimize the gap between needs and capabilities through the ship operational life. It means, the main TLS program objective is to maintain the ship’s performance and capabilities during operational life, in relative terms to current technologies, equivalent to those the ship had when it entered service. The main actions to fulfill the TLS program objectives are: value-oriented design, TLS engineering, technology updating projects, intelligent maintenance and performance based contracts.

Comments and remarks over classic linear loop-gain method for oscillator design and analysis. New proposed method based on NDF/RRT

Abstract. This paper describes a new and original method for designing oscillators based on the Normalized Determinant Function (NDF) and Return Relations (RRT)- Firstly, a review of the loop-gain method will be performed. The loop-gain method pros, cons and some examples for exploring wrong solutions provided by this method will be shown. This method produces in some cases wrong solutions because some necessary conditions have not been fulfilled. The required necessary conditions to assure a right solution will be described. The necessity of using the NDF or the Transpose Return Relations (RRT), which are related with the True Loop-Gain, to test the additional conditions will be demonstrated. To conclude this paper, the steps for oscillator design and analysis, using the proposed NDF/RRj method, will be presented. The loop-gain wrong solutions will be compared with the NDF/RRj and the accuracy of this method to estimate the oscillation frequency and QL will be demonstrated. Some additional examples of plane reference oscillators (Z/Y/T), will be added and they will be analyzed with the new NDF/RRj proposed method, even these oscillators cannot be analyzed using the classic loop gain method.

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

Esta tesis doctoral se centra principalmente en técnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en inglés), que han sido propuestas dentro del campo de investigación académica desde hace 17 años. Las investigaciones relacionadas han experimentado un notable crecimiento en las últimas décadas, mientras que los diseños enfocados en la protección sólida y eficaz contra dichos ataques aún se mantienen como un tema de investigación abierto, en el que se necesitan iniciativas más confiables para la protección de la información persona de empresa y de datos nacionales. El primer uso documentado de codificación secreta se remonta a alrededor de 1700 B.C., cuando los jeroglíficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la información siempre ha supuesto un factor clave en la transmisión de datos relacionados con inteligencia diplomática o militar. Debido a la evolución rápida de las técnicas modernas de comunicación, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisión a través de cables sin seguridad o medios inalámbricos. Debido a las restricciones de potencia de cálculo antes de la era del ordenador, la técnica de cifrado simple era un método más que suficiente para ocultar la información. Sin embargo, algunas vulnerabilidades algorítmicas pueden ser explotadas para restaurar la regla de codificación sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el área de la criptografía, con el fin de proteger el sistema de información ante sofisticados algoritmos. Con la invención de los ordenadores se ha acelerado en gran medida la implementación de criptografía segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computación altamente reforzadas. Igualmente, sofisticados cripto-análisis han impulsado las tecnologías de computación. Hoy en día, el mundo de la información ha estado involucrado con el campo de la criptografía, enfocada a proteger cualquier campo a través de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificación optimizada de teorías matemáticas modernas y prácticas eficaces de hardware, siendo posible su implementación en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales métricas de conducción en el diseño electrónico, con el objetivo de promover la fabricación de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementación práctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de análisis. Sin embargo, algunas críticas sobre los algoritmos criptográficos teóricamente seguros surgieron casi inmediatamente después de este descubrimiento. En este sentido, los circuitos digitales consisten típicamente en un gran número de celdas lógicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricación. La lógica de los circuitos se realiza en función de las innumerables conmutaciones de estas células. Este mecanismo provoca inevitablemente cierta emanación física especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptografía de claves), analizar la arquitectura lógica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparación de correlación entre la cantidad de fuga estimada y las fugas medidas de forma real, información confidencial puede ser reconstruida en mucho menos tiempo y computación. Para ser precisos, SCA básicamente cubre una amplia gama de tipos de ataques, como los análisis de consumo de energía y radiación ElectroMagnética (EM). Ambos se basan en análisis estadístico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no están intrínsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementación de circuitos integrar medidas que permitan camuflar las fugas a través de "canales laterales". Las medidas contra SCA están evolucionando junto con el desarrollo de nuevas técnicas de ataque, así como la continua mejora de los dispositivos electrónicos. Las características físicas requieren contramedidas sobre la capa física, que generalmente se pueden clasificar en soluciones intrínsecas y extrínsecas. Contramedidas extrínsecas se ejecutan para confundir la fuente de ataque mediante la integración de ruido o mala alineación de la actividad interna. Comparativamente, las contramedidas intrínsecas están integradas en el propio algoritmo, para modificar la aplicación con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultación y Enmascaramiento son dos técnicas típicas incluidas en esta categoría. Concretamente, el enmascaramiento se aplica a nivel algorítmico, para alterar los datos intermedios sensibles con una máscara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptografías modernas son difíciles de enmascarar. Dicho método de ocultación, que ha sido verificado como una solución efectiva, comprende principalmente la codificación en doble carril, que está ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, además de la descripción de las metodologías de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la lógica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel lógico. Una característica de SCA reside en el formato de las fuentes de fugas. Un típico ataque de canal lateral se refiere al análisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades parásitas son las fuentes esenciales de fugas. Por lo tanto, una lógica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas lógicas básicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la lógica desde un nivel más alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones clásicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementación de un esquema de diseño personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el diseño y la implementación de una lógica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener dinámicamente el equilibrio de las fugas en las capas inferiores; II. Esta lógica explota las características de la arquitectura de las FPGAs, para reducir al mínimo el gasto de recursos en la implementación; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo genérico de diseño sobre FPGAs, con el fin de manipular los circuitos de forma automática. El kit de herramientas de diseño automático es compatible con la lógica de doble carril propuesta, para facilitar la aplicación práctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodología y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho más rígidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementación y reparación de lógica de doble carril genérica. La viabilidad de las soluciones propuestas es validada mediante la selección de algoritmos criptográficos ampliamente utilizados, y su evaluación exhaustiva en comparación con soluciones anteriores. Todas las propuestas están respaldadas eficazmente a través de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigación tiene la intención de cerrar la brecha entre las barreras de implementación y la aplicación efectiva de lógica de doble carril. En esencia, a lo largo de esta tesis se describirá un conjunto de herramientas de implementación para FPGAs que se han desarrollado para trabajar junto con el flujo de diseño genérico de las mismas, con el fin de lograr crear de forma innovadora la lógica de doble carril. Un nuevo enfoque en el ámbito de la seguridad en el cifrado se propone para obtener personalización, automatización y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigación se resumen brevemente a continuación: Lógica de Precharge Absorbed-DPL logic: El uso de la conversión de netlist para reservar LUTs libres para ejecutar la señal de precharge y Ex en una lógica DPL. Posicionamiento entrelazado Row-crossed con pares idénticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medición EM selectiva y mitigar los impactos de las variaciones de proceso. Ejecución personalizada y herramientas de conversión automática para la generación de redes idénticas para la lógica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asimétricas. (c) Para ser utilizado en otras lógicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. Plataforma CPA de pruebas personalizadas para el análisis de EM y potencia, incluyendo la construcción de dicha plataforma, el método de medición y análisis de los ataques. Análisis de tiempos para cuantificar los niveles de seguridad. División de Seguridad en la conversión parcial de un sistema de cifrado complejo para reducir los costes de la protección. Prueba de concepto de un sistema de calefacción auto-adaptativo para mitigar los impactos eléctricos debido a la variación del proceso de silicio de manera dinámica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuación: En el capítulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos básicos de teoría de modelos de análisis, además de la implementación de la plataforma y la ejecución de los ataques. En el capítulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Además de ello, en este capítulo se propone una lógica en doble carril compacta y segura como contribución de gran relevancia, así como también se presentará la transformación lógica basada en un diseño a nivel de puerta. Por otra parte, en el Capítulo 3 se abordan los desafíos relacionados con la implementación de lógica en doble carril genérica. Así mismo, se describirá un flujo de diseño personalizado para resolver los problemas de aplicación junto con una herramienta de desarrollo automático de aplicaciones propuesta, para mitigar las barreras de diseño y facilitar los procesos. En el capítulo 4 se describe de forma detallada la elaboración e implementación de las herramientas propuestas. Por otra parte, la verificación y validaciones de seguridad de la lógica propuesta, así como un sofisticado experimento de verificación de la seguridad del rutado, se describen en el capítulo 5. Por último, un resumen de las conclusiones de la tesis y las perspectivas como líneas futuras se incluyen en el capítulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada capítulo se describe de forma más detallada a continuación: En el capítulo 1 se introduce plataforma de implementación hardware además las teorías básicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura genérica y las características de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un módulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los métodos de canal lateral, que permiten revelar las fugas de disipación correlacionadas con los comportamientos internos; y el método para recuperar esta relación entre las fluctuaciones físicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del capítulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protección de la compensación dinámica de la lógica genérica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripción de los elementos compensados a nivel de puerta. En segundo lugar, la lógica PA-DPL es propuesta como aportación original, detallando el protocolo de la lógica y un caso de aplicación. En tercer lugar, dos flujos de diseño personalizados se muestran para realizar la conversión de doble carril. Junto con ello, se aclaran las definiciones técnicas relacionadas con la manipulación por encima de la netlist a nivel de LUT. Finalmente, una breve discusión sobre el proceso global se aborda en la parte final del capítulo. El Capítulo 3 estudia los principales retos durante la implementación de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantación a través de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos parásitos, sesgo tecnológico y la viabilidad de implementación. De acuerdo con estas elaboraciones, se plantean dos problemas: Cómo implementar la lógica propuesta sin penalizar los niveles de seguridad, y cómo manipular un gran número de celdas y automatizar el proceso. El PA-DPL propuesto en el capítulo 2 se valida con una serie de iniciativas, desde características estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los métodos de aplicación tales como las herramientas de personalización y automatización de EDA. Por otra parte, un sistema de calefacción auto-adaptativo es representado y aplicado a una lógica de doble núcleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variación del proceso durante la operación en tiempo real. El capítulo 4 se centra en los detalles de la implementación del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la lógica de circuito post P&R ncd (una versión binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y razón de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detección de enrutamiento y los enfoques para la reparación. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente idénticos para la lógica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este capítulo particularmente especifica las bases técnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El capítulo 5 se enfoca en la aplicación de los casos de estudio para la validación de los grados de seguridad de la lógica propuesta. Se discuten los problemas técnicos detallados durante la ejecución y algunas nuevas técnicas de implementación. (a) Se discute el impacto en el proceso de posicionamiento de la lógica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementación, tomando en cuenta la optimización global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparación optimizados; (b) las validaciones de seguridad se realizan con los métodos de correlación y análisis de tiempo; (c) Una táctica asintótica se aplica a un núcleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre métricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacción auto-adaptativa sobre la variación del proceso son mostrados; (e) Se introduce una aplicación práctica de las herramientas para un diseño de cifrado completa. Capítulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por último, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilización de las contribuciones de esta tesis a un alcance más allá de los dominios de la criptografía en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. A timing analysis based method for quantifying the security grades. A methodology of security partitions of complex crypto systems for reducing the protection cost. A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.

How should the sustainability of the location of dry ports be measured? A proposed methodology using Bayesian networks and multi-criteria decision analysis

The global economic structure, with its decentralized production and the consequent increase in freight traffic all over the world, creates considerable problems and challenges for the freight transport sector. This situation has led shipping to become the most suitable and cheapest way to transport goods. Thus, ports are configured as nodes with critical importance in the logistics supply chain as a link between two transport systems, sea and land. Increase in activity at seaports is producing three undesirable effects: increasing road congestion, lack of open space in port installations and a significant environmental impact on seaports. These adverse effects can be mitigated by moving part of the activity inland. Implementation of dry ports is a possible solution and would also provide an opportunity to strengthen intermodal solutions as part of an integrated and more sustainable transport chain, acting as a link between road and railway networks. In this sense, implementation of dry ports allows the separation of the links of the transport chain, thus facilitating the shortest possible routes for the lowest capacity and most polluting means of transport. Thus, the decision of where to locate a dry port demands a thorough analysis of the whole logistics supply chain, with the objective of transferring the largest volume of goods possible from road to more energy efficient means of transport, like rail or short-sea shipping, that are less harmful to the environment. However, the decision of where to locate a dry port must also ensure the sustainability of the site. Thus, the main goal of this article is to research the variables influencing the sustainability of dry port location and how this sustainability can be evaluated. With this objective, in this paper we present a methodology for assessing the sustainability of locations by the use of Multi-Criteria Decision Analysis (MCDA) and Bayesian Networks (BNs). MCDA is used as a way to establish a scoring, whilst BNs were chosen to eliminate arbitrariness in setting the weightings using a technique that allows us to prioritize each variable according to the relationships established in the set of variables. In order to determine the relationships between all the variables involved in the decision, giving us the importance of each factor and variable, we built a K2 BN algorithm. To obtain the scores of each variable, we used a complete cartography analysed by ArcGIS. Recognising that setting the most appropriate location to place a dry port is a geographical multidisciplinary problem, with significant economic, social and environmental implications, we consider 41 variables (grouped into 17 factors) which respond to this need. As a case of study, the sustainability of all of the 10 existing dry ports in Spain has been evaluated. In this set of logistics platforms, we found that the most important variables for achieving sustainability are those related to environmental protection, so the sustainability of the locations requires a great respect for the natural environment and the urban environment in which they are framed.

Trust and Privacy Solutions Based on Holistic Service Requirements

The products and services designed for Smart Cities provide the necessary tools to improve the management of modern cities in a more efficient way. These tools need to gather citizens’ information about their activity, preferences, habits, etc. opening up the possibility of tracking them. Thus, privacy and security policies must be developed in order to satisfy and manage the legislative heterogeneity surrounding the services provided and comply with the laws of the country where they are provided. This paper presents one of the possible solutions to manage this heterogeneity, bearing in mind these types of networks, such as Wireless Sensor Networks, have important resource limitations. A knowledge and ontology management system is proposed to facilitate the collaboration between the business, legal and technological areas. This will ease the implementation of adequate specific security and privacy policies for a given service. All these security and privacy policies are based on the information provided by the deployed platforms and by expert system processing.