UV laser-induced high resolution cleaving of Si wafers for micro-nano devices and polymeric waveguide characterization

In this work we propose a method for cleaving silicon-based photonic chips by using a laser based micromachining system, consisting of a ND:YVO4laser emitting at 355 nm in nanosecond pulse regime and a micropositioning system. The laser makes grooved marks placed at the desired locations and directions where cleaves have to be initiated, and after several processing steps, a crack appears and propagate along the crystallographic planes of the silicon wafer. This allows cleavage of the chips automatically and with high positioning accuracy, and provides polished vertical facets with better quality than the obtained with other cleaving process, which eases the optical characterization of photonic devices. This method has been found to be particularly useful when cleaving small-sized chips, where manual cleaving is hard to perform; and also for polymeric waveguides, whose facets get damaged or even destroyed with polishing or manual cleaving processing. Influence of length of the grooved line and speed of processing is studied for a variety of silicon chips. An application for cleaving and characterizing sol–gel waveguides is presented. The total amount of light coupled is higher than when using any other procedure.

Improving Hardware Reuse through XML-based Interface Encapsulation

This work proposes an encapsulation scheme aimed at simplifying the reuse process of hardware cores. This hardware encapsulation approach has been conceived with a twofold objective. First, we look for the improvement of the reuse interface associated with the hardware core description. This is carried out in a first encapsulation level by improving the limited types and configuration options available in the conventional HDLs interface, and also providing information related to the implementation itself. Second, we have devised a more generic interface focused on describing the function avoiding details from a particular implementation, what corresponds to a second encapsulation level. This encapsulation allows the designer to define how to configure and use the design to implement a given functionality. The proposed encapsulation schemes help improving the amount of information that can be supplied with the design, and also allow to automate the process of searching, configuring and implementing diverse alternatives.