Understanding phosphorus diffusion into silicon in a MOVPE environment for III-V on silicon solar cells

Dual-junction solar cells formed by a GaAsP or GaInP top cell and a silicon bottom cell seem to be attractive candidates to materialize the long sought-for integration of III?V materials on silicon for photovoltaic applications. When manufacturing a multi-junction solar cell on silicon, one of the first processes to be addressed is the development of the bottom subcell and, in particular, the formation of its emitter. In this study, we analyze, both experimentally and by simulations, the formation of the emitter as a result of phosphorus diffusion that takes place during the first stages of the epitaxial growth of the solar cell. Different conditions for the Metal-Organic Vapor Phase Epitaxy (MOVPE) process have been evaluated to understand the impact of each parameter, namely, temperature, phosphine partial pressure, time exposure and memory effects in the final diffusion profiles obtained. A model based on SSupremIV process simulator has been developed and validated against experimental profiles measured by ECV and SIMS to calculate P diffusion profiles in silicon formed in a MOVPE environment taking in consideration all these factors.

First order mem-circuits: modeling, nonlinear oscillations and bifurcations

This paper presents a theoretical framework intended to accommodate circuit devices described by characteristics involving more than two fundamental variables. This framework is motivated by the recent appearance of a variety of so-called mem-devices in circuit theory, and makes it possible to model the coexistence of memory effects of different nature in a single device. With a compact formalism, this setting accounts for classical devices and also for circuit elements which do not admit a two-variable description. Fully nonlinear characteristics are allowed for all devices, driving the analysis beyond the framework of Chua and Di Ventra We classify these fully nonlinear circuit elements in terms of the variables involved in their constitutive relations and the notions of the differential- and the state-order of a device. We extend the notion of a topologically degenerate configuration to this broader context, and characterize the differential-algebraic index of nodal models of such circuits. Additionally, we explore certain dynamical features of mem-circuits involving manifolds of non-isolated equilibria. Related bifurcation phenomena are explored for a family of nonlinear oscillators based on mem-devices.

Remote Effects of Hippocampal Sclerosis on Effective Connectivity during Working Memory Encoding: A Case of Connectional Diaschisis?

Accumulating evidence suggests a role for the medial temporal lobe (MTL) in working memory (WM). However, little is known concerning its functional interactions with other cortical regions in the distributed neural network subserving WM. To reveal these, we availed of subjects with MTL damage and characterized changes in effective connectivity while subjects engaged in WM task. Specifically, we compared dynamic causal models, extracted from magnetoencephalographic recordings during verbal WM encoding, in temporal lobe epilepsy patients (with left hippocampal sclerosis) and controls. Bayesian model comparison indicated that the best model (across subjects) evidenced bilateral, forward, and backward connections, coupling inferior temporal cortex (ITC), inferior frontal cortex (IFC), and MTL. MTL damage weakened backward connections from left MTL to left ITC, a decrease accompanied by strengthening of (bidirectional) connections between IFC and MTL in the contralesional hemisphere. These findings provide novel evidence concerning functional interactions between nodes of this fundamental cognitive network and sheds light on how these interactions are modified as a result of focal damage to MTL. The findings highlight that a reduced (top-down) influence of the MTL on ipsilateral language regions is accompanied by enhanced reciprocal coupling in the undamaged hemisphere providing a first demonstration of “connectional diaschisis.”

Age-Related Effects in Working Memory Recognition Modulated by Retroactive Interference

One of the main causes for age-related declines in working memory is a higher vulnerability to retroactive interference due to a reduced ability to suppress irrelevant information. However, the underlying neural correlates remain to be established. Magnetoencephalography was used to investigate differential neural patterns in young and older adults performing an interference-based memory task with two experimental conditions, interrupting and distracting, during successful recognition. Behaviorally, both types of retroactive interference significantly impaired accuracy at recognition more in older adults than in young adults with the latter exhibiting greater disruptions by interrupters. Magnetoencephalography revealed the presence of differential age-related neural patterns. Specifically, time-modulated activations in temporo-occipital and superior parietal regions were higher in young adults compared with older adults for the interrupting condition. These results suggest that age-related deficits in inhibitory mechanisms that increase vulnerability to retroactive interference may be associated with neural under-recruitments in a high-interference task.

Design techniques for xilinx virtex FPGA configuration memory scrubbers

SRAM-based FPGAs are in-field reconfigurable an unlimited number of times. This characteristic, together with their high performance and high logic density, proves to be very convenient for a number of ground and space level applications. One drawback of this technology is that it is susceptible to ionizing radiation, and this sensitivity increases with technology scaling. This is a first order concern for applications in harsh radiation environments, and starts to be a concern for high reliability ground applications. Several techniques exist for coping with radiation effects at user application. In order to be effective they need to be complemented with configuration memory scrubbing, which allows error mitigation and prevents failures due to error accumulation. Depending on the radiation environment and on the system dependability requirements, the configuration scrubber design can become more or less complex. This paper classifies and presents current and novel design methodologies and architectures for SRAM-based FPGAs, and in particular for Xilinx Virtex-4QV/5QV, configuration memory scrubbers.