3 resultados para MEMORY STORAGE

em Universidad Politécnica de Madrid


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The most ubiquitous neuron in the cerebral cortex, the pyramidal cell, is characterized by markedly different dendritic structure among different cortical areas. The complex pyramidal cell phenotype in granular prefrontal cortex (gPFC) of higher primates endows specific biophysical properties and patterns of connectivity, which differ from those in other cortical regions. However, within the gPFC, data have been sampled from only a select few cortical areas. The gPFC of species such as human and macaque monkey includes more than 10 cortical areas. It remains unknown as to what degree pyramidal cell structure may vary among these cortical areas. Here we undertook a survey of pyramidal cells in the dorsolateral, medial, and orbital gPFC of cercopithecid primates. We found marked heterogeneity in pyramidal cell structure within and between these regions. Moreover, trends for gradients in neuronal complexity varied among species. As the structure of neurons determines their computational abilities, memory storage capacity and connectivity, we propose that these specializations in the pyramidal cell phenotype are an important determinant of species-specific executive cortical functions in primates.

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The goal of the RAP-WAM AND-parallel Prolog abstract architecture is to provide inference speeds significantly beyond those of sequential systems, while supporting Prolog semantics and preserving sequential performance and storage efficiency. This paper presents simulation results supporting these claims with special emphasis on memory performance on a two-level sharedmemory multiprocessor organization. Several solutions to the cache coherency problem are analyzed. It is shown that RAP-WAM offers good locality and storage efficiency and that it can effectively take advantage of broadcast caches. It is argued that speeds in excess of 2 ML IPS on real applications exhibiting medium parallelism can be attained with current technology.

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The interactions among three important issues involved in the implementation of logic programs in parallel (goal scheduling, precedence, and memory management) are discussed. A simplified, parallel memory management model and an efficient, load-balancing goal scheduling strategy are presented. It is shown how, for systems which support "don't know" non-determinism, special care has to be taken during goal scheduling if the space recovery characteristics of sequential systems are to be preserved. A solution based on selecting only "newer" goals for execution is described, and an algorithm is proposed for efficiently maintaining and determining precedence relationships and variable ages across parallel goals. It is argued that the proposed schemes and algorithms make it possible to extend the storage performance of sequential systems to parallel execution without the considerable overhead previously associated with it. The results are applicable to a wide class of parallel and coroutining systems, and they represent an efficient alternative to "all heap" or "spaghetti stack" allocation models.