Hardening digital systems with distributed functionality: robust networks

Collaborative hardening and hardware redundancy are nowadays the most interesting solutions in terms of fault tolerance achieved and low extra cost imposed to the project budget. Thanks to the powerful and cheap digital devices that are available in the market, extra processing capabilities can be used for redundant tasks, not only in early data processing (sensed data) but also in routing and interfacing1

Functional validation of MB-OFDM system using HW-in the loop

Functional validation of complex digital systems is a hard and critical task in the design flow. In particular, when dealing with communication systems, like Multiband Orthogonal Frequency Division Multiplexing Ultra Wideband (MB-OFDM UWB), the design decisions taken during the process have to be validated at different levels in an easy way. In this work, a unified algorithm-architecture-circuit co-design environment for this type of systems, to be implemented in FPGA, is presented. The main objective is to find an efficient methodology for designing a configurable optimized MB-OFDM UWB system by using as few efforts as possible in verification stage, so as to speed up the development period. Although this efficient design methodology is tested and considered to be suitable for almost all types of complex FPGA designs, we propose a solution where both the circuit and the communication channel are tested at different levels (algorithmic, RTL, hardware device) using a common testbench.

La videovigilancia : tecnologías actuales y aspectos sociopolíticos

En este Proyecto de fin de carrera titulado: LA VÍDEOVIGILANCIA: TECNOLOGÍAS ACTUALES Y ASPECTOS SOCIOPOLÍTICOS, tiene como objetivo hacer un estudio en los sistemas de Vídeovigilancia basado en cámaras-IP, con fines de seguridad, control o supervisión. Nos basaremos en exponer los sistemas Vídeovigilancia basados en cámara-IP actuales de ultima generación, cuya principal virtud de estos sistemas, es la comunicación con otros lugares, o espacios públicos como privados y poder visualizar tanto en vivo como en diferido lo que este pasando en ese lugar y en ese momento o haya pasado a través del protocolo de comunicación-IP. Se explicara desde el más básico al más complejo sistema de videovigilancia-IP, también explicaremos su puesta en practica mediante los múltiples interconexiones que estos conlleven. Llegando a este punto, se nos plantea las siguientes cuestiones que da origen a este PFC. Estos sistemas de Vídeovigilancia-IP, captan las imágenes por medio de las cámaras-IP, proporcionando su facilidad tanto de visionado/grabacion, como de control, ya que no es necesario estar presente e interactuando con otros sistemas digitales de diverso índole actuales, gracias al protocolo-IP. Estos sistemas-IP, tienen su puesta en práctica mediante las instalaciones requeridas ,estas podrán ser sencillas o muy complejas de todos los sistemas-IP. Debido al gran aumento masivo, las tecnologías actuales de diverso índole de cámaras-IP en materia de la vídeovigilancia en lugares públicos, y privados en nuestra sociedad actual, lo hace un medio particularmente invasivo y por ello resulta necesario tanto la concurrencia de condiciones que legitimen los tratamientos de datos de personas identificables, como la definición de los principios y garantías que deban aplicarse ya que estas, repercutirán sobre los derechos de las personas, lo que obligara a fijar ciertas garantías. Se nos plantea los casos en los que la captación y/o tratamiento de imágenes con fines de Vídeovigilancia que pertenezcan a personas identificadas o identificables, ha obligado a España, y según dispuesto por la Directiva 95/46/CE del Parlamento Europeo, a regularizar esta situación mediante la Ley Orgánica de Protección de Datos (LOPD) 15/1999 de 13 de diciembre, bajo los procedimientos del Estado español en materia sociopolítica, y dando vigor a esta ley, mediante la aprobación de la Instrucción 1/2006 de 8 de noviembre de 2006, cuyo máximo organismo es la Agencia española de Protección de Datos (AGPD). Una vez planteada la motivación y justificación del proyecto, se derivan unos objetivos a cumplir con la realización del mismo. Los objetivos del proyecto se pueden diferenciar en dos clases principalmente. Los objetivos principales y objetivos secundarios. Los objetivos principales de este PFC, nacen directamente de las necesidades planteadas originalmente en materia de Vídeovigilancia, tanto tecnológicamente basado en las cámaras-IP en la captación y/o tratamiento de imágenes, así como sociopolíticamente donde trataremos de describirlo mediante las indicaciones y criterios con casos prácticos y de cómo deben de aplicarse según la instrucción 1/2006 mediante la LOPD en materia de Vídeovigilancia, en cuanto a la protección de datos que puedan repercutir sobre el derecho de las personas. Por otra parte los objetivos secundarios, son la extensión del objetivo primario y son de orden cuantificador en este PFC, dando una explicación más exhaustiva del objetivo principal. ABSTRACT In this final year project, entitled: THE VIDEOSURVEILLANCE: CURRENT TECHNOLOGIES AND POLITICALSOCIALS ASPECTS, aims to make a study of video surveillance systems based on IP cameras, for security, control or supervision. We will rely on to expose the camera based video surveillance systems IP-current last generation, whose main virtue of these systems, is communication with other places, or public and private spaces and to view both live and time so this happening in that place and at that time or passed through-IP communication protocol. He explained from the most basic to the most complex-IP video surveillance system, also explain its implementation into practice through multiple interconnections that these entail. Arriving at this point, we face the following issues which gave rise to this PFC. These IP-video surveillance systems, captured images through IP-cameras, providing both ease of viewing / recording, as a control, since it is not necessary to be present and interacting with other digital systems such diverse today, thanks IP-protocol. These systems-IP, have their implementation through the facilities required, these can be simple or very complex all-IP video surveillance systems. Due to the large increase in mass, current technologies of different kinds of IP cameras for video surveillance in public places, and private in our society, it makes a particularly invasive and therefore attendance is necessary both conditions that legitimize data processing of identifiable people, as the definition of the principles and safeguards to be applied as these will impact on the rights of the people, which forced to set certain guarantees. We face those cases in which the uptake and / or image processing video surveillance purposes belonging to identified or identifiable, has forced Spain, and as required by Directive 95/46/EC of the European Parliament, to regularize this situation by the Organic Law on Data Protection (LOPD) 15/1999 of December 13, under the procedures of the Spanish State in sociopolitical, and giving effect to this Act, with the approval of the Instruction 1/2006 of 8 November 2006, the governing body is the Spanish Agency for Data Protection (AGPD). Once raised the motivation and justification for the project, resulting in meeting targets to achieve the same. Project objectives can be differentiated into two main classes, the main objectives and secondary objectives: The main objectives of this PFC, born directly from requirements originally raised for capturing both technologically imaging me and try to describe where sociopolitically, the details and criteria as case studies and should be applied according to the instruction 1 / 2006 by the LOPD on video surveillance system in terms of data protection that could impact on the right people. Moreover the secondary objectives are the extension of the primary and are of a quantifier in this PFC, giving a fuller explanation of the main objective.

Modelado en alto nivel con SystemC

El presente proyecto final de carrera titulado “Modelado de alto nivel con SystemC” tiene como objetivo principal el modelado de algunos módulos de un codificador de vídeo MPEG-2 utilizando el lenguaje de descripción de sistemas igitales SystemC con un nivel de abstracción TLM o Transaction Level Modeling. SystemC es un lenguaje de descripción de sistemas digitales basado en C++. En él hay un conjunto de rutinas y librerías que implementan tipos de datos, estructuras y procesos especiales para el modelado de sistemas digitales. Su descripción se puede consultar en [GLMS02] El nivel de abstracción TLM se caracteriza por separar la comunicación entre los módulos de su funcionalidad. Este nivel de abstracción hace un mayor énfasis en la funcionalidad de la comunicación entre los módulos (de donde a donde van datos) que la implementación exacta de la misma. En los documentos [RSPF] y [HG] se describen el TLM y un ejemplo de implementación. La arquitectura del modelo se basa en el codificador MVIP-2 descrito en [Gar04], de dicho modelo, los módulos implementados son: · IVIDEOH: módulo que realiza un filtrado del vídeo de entrada en la dimensión horizontal y guarda en memoria el video filtrado. · IVIDEOV: módulo que lee de la memoria el vídeo filtrado por IVIDEOH, realiza el filtrado en la dimensión horizontal y escribe el video filtrado en memoria. · DCT: módulo que lee el video filtrado por IVIDEOV, hace la transformada discreta del coseno y guarda el vídeo transformado en la memoria. · QUANT: módulo que lee el video transformado por DCT, lo cuantifica y guarda el resultado en la memoria. · IQUANT: módulo que lee el video cuantificado por QUANT, realiza la cuantificación inversa y guarda el resultado en memoria. · IDCT: módulo que lee el video procesado por IQUANT, realiza la transformada inversa del coseno y guarda el resultado en memoria. · IMEM: módulo que hace de interfaz entre los módulos anteriores y la memoria. Gestiona las peticiones simultáneas de acceso a la memoria y asegura el acceso exclusivo a la memoria en cada instante de tiempo. Todos estos módulos aparecen en gris en la siguiente figura en la que se muestra la arquitectura del modelo: Figura 1. Arquitectura del modelo (VER PDF DEL PFC) En figura también aparecen unos módulos en blanco, dichos módulos son de pruebas y se han añadido para realizar simulaciones y probar los módulos del modelo: · CAMARA: módulo que simula una cámara en blanco y negro, lee la luminancia de un fichero de vídeo y lo envía al modelo a través de una FIFO. · FIFO: hace de interfaz entre la cámara y el modelo, guarda los datos que envía la cámara hasta que IVIDEOH los lee. · CONTROL: módulo que se encarga de controlar los módulos que procesan el vídeo, estos le indican cuando terminan de procesar un frame de vídeo y este módulo se encarga de iniciar los módulos que sean necesarios para seguir con la codificación. Este módulo se encarga del correcto secuenciamiento de los módulos procesadores de vídeo. · RAM: módulo que simula una memoria RAM, incluye un retardo programable en el acceso. Para las pruebas también se han generado ficheros de vídeo con el resultado de cada módulo procesador de vídeo, ficheros con mensajes y un fichero de trazas en el que se muestra el secuenciamiento de los procesadores. Como resultado del trabajo en el presente PFC se puede concluir que SystemC permite el modelado de sistemas digitales con bastante sencillez (hace falta conocimientos previos de C++ y programación orientada objetos) y permite la realización de modelos con un nivel de abstracción mayor a RTL, el habitual en Verilog y VHDL, en el caso del presente PFC, el TLM. ABSTRACT This final career project titled “High level modeling with SystemC” have as main objective the modeling of some of the modules of an MPEG-2 video coder using the SystemC digital systems description language at the TLM or Transaction Level Modeling abstraction level. SystemC is a digital systems description language based in C++. It contains routines and libraries that define special data types, structures and process to model digital systems. There is a complete description of the SystemC language in the document [GLMS02]. The main characteristic of TLM abstraction level is that it separates the communication among modules of their functionality. This abstraction level puts a higher emphasis in the functionality of the communication (from where to where the data go) than the exact implementation of it. The TLM and an example are described in the documents [RSPF] and [HG]. The architecture of the model is based in the MVIP-2 video coder (described in the document [Gar04]) The modeled modules are: · IVIDEOH: module that filter the video input in the horizontal dimension. It saves the filtered video in the memory. · IVIDEOV: module that read the IVIDEOH filtered video, filter it in the vertical dimension and save the filtered video in the memory. · DCT: module that read the IVIDEOV filtered video, do the discrete cosine transform and save the transformed video in the memory. · QUANT: module that read the DCT transformed video, quantify it and save the quantified video in the memory. · IQUANT: module that read the QUANT processed video, do the inverse quantification and save the result in the memory. · IDCT: module that read the IQUANT processed video, do the inverse cosine transform and save the result in the memory. · IMEM: this module is the interface between the modules described previously and the memory. It manage the simultaneous accesses to the memory and ensure an unique access at each instant of time All this modules are included in grey in the following figure (SEE PDF OF PFC). This figure shows the architecture of the model: Figure 1. Architecture of the model This figure also includes other modules in white, these modules have been added to the model in order to simulate and prove the modules of the model: · CAMARA: simulates a black and white video camera, it reads the luminance of a video file and sends it to the model through a FIFO. · FIFO: is the interface between the camera and the model, it saves the video data sent by the camera until the IVIDEOH module reads it. · CONTROL: controls the modules that process the video. These modules indicate the CONTROL module when they have finished the processing of a video frame. The CONTROL module, then, init the necessary modules to continue with the video coding. This module is responsible of the right sequence of the video processing modules. · RAM: it simulates a RAM memory; it also simulates a programmable delay in the access to the memory. It has been generated video files, text files and a trace file to check the correct function of the model. The trace file shows the sequence of the video processing modules. As a result of the present final career project, it can be deduced that it is quite easy to model digital systems with SystemC (it is only needed previous knowledge of C++ and object oriented programming) and it also allow the modeling with a level of abstraction higher than the RTL used in Verilog and VHDL, in the case of the present final career project, the TLM.

Desarrollo de una guía de aprendizaje para el manejo del entorno de CAD IspLEVER

En este proyecto se analizan las características y el ciclo de diseño asociado al entorno de CAD IspLEVER, de Lattice Semiconductor, con la finalidad de evaluar su adecuación a la docencia relacionada con la ingeniería de sistemas digitales cableados. En base a este estudio se realiza una guía del manejo de las diferentes herramientas que se integran en el entorno. Además, se realiza la caracterización de una serie de familias de dispositivos del fabricante Lattice Semiconductor que pudiera servir de apoyo a la hora de elegir un dispositivo de este fabricante para la realización de un determinado diseño. Para dar comienzo a la realización del estudio del entorno y de las herramientas que integra IspLEVER, se procedió a la familiarización con el marco de trabajo. Esta familiarización se realizó, en un principio, a través de la lectura de la documentación ofrecida por el fabricante en su página web, http://www.latticesemi.com. Tras esta lectura, que sirvió para tener una primera visión de las características de la herramienta, se procedió a la descarga del paquete de instalación; el fabricante ofrece una versión de evaluación que expira a los 12 meses. Una vez descargado, se instaló y para terminar con los preparativos, se pasó el procedimiento de obtención de la licencia. Con ello se consiguió tener el software preparado para su utilización. A continuación se emplearon horas de trabajo para, sin documentación alguna, tratar de crear diseños; con este trabajo se pretendía detectar lo intuitivo que resulta el entorno cuando se tienen conocimientos de herramientas de CAD electrónico. Tras esta primera toma de contacto con el entorno real, se procedió al estudio de las diferentes opciones que ofrece para la realización de diseños, ya sean lógicos o físicos. Además del estudio de todas las posibilidades que ofrece el entorno, el trabajo se focalizó en la detección y comparación de las distintas opciones que ofrece para realizar una misma tarea, como ocurre con la asignación de pines o con la revisión de los resultados de una simulación, entre otras. Entrelazado con el estudio de las opciones que ofrece el entorno, se realizó el estudio de las distintas herramientas de trabajo integradas en el mismo. Una vez estudiado el entorno y las herramientas, se procedió a la realización del tutorial. Se capturaron todas las imágenes que se consideraron apropiadas para que al alumno le resultase cómodo y fácil seguir todas las indicaciones que el tutorial ofrece, para la realización de un ciclo de diseño lógico completo. Tras la realización del tutorial, se procedió a revisar la amplia documentación que el fabricante ofrece de cada una de las distintas familias de dispositivos que fabrica. El fin de esta revisión no fue otro que realizar una caracterización de las distintas familias, que pudiera servir de apoyo a la hora de elegir un dispositivo de este fabricante para la realización de un determinado diseño. Este estudio de las familias de dispositivos del fabricante, también se realizó para detectar qué familia de dispositivos era la más idónea para incluir uno de sus miembros en una hipotética placa de prototipado, para la realización de prácticas de laboratorio. ABSTRACT. This project consists in the analysis of the characteristics and the design cycle associated with the IspLEVER environment of CAD, by Lattice Semiconductor. The objective of that analysis is to evaluate their suitability for teaching engineering related to wired digital systems. Based on this analysis a guide was made for managing the different tools that are integrated into the environment. In addition, the characterization of several families by the manufacturer Lattice Semiconductor was made, with the objective that it could be used to support the choice of a Lattice’s device to perform a certain design. To start the IspLEVER environment and tools study, I began with a familiarization with the environment. This familiarization consisted in a study of the manufacturer documentation offered in their web page, http://www.latticesemi.com. After that, I had a general view about the characteristics of the environment and environment tools. Then I continued downloading the installation package. The manufacturer offers an evaluation version that expires in the period of one year. After that download, the environment was installed. Finally, the licensing procedure was followed to finish with the preparations. Then, the software was prepared for its utilization. Following, several work hours were wasted without documentation, trying to create designs. This work has been to identify how intuitive the environment is when you have knowledge of electronic CAD tools. After this first point of contact with the real environment, I proceeded to study different offered options, by the manufacturer, for the realization of either logical or physical designs. In addition to studying all the possibilities offered by the environment, the work is focused on the detection and comparison of the various options offered to perform the same task, as with the pin assignment or reviewing the results of a simulation… At the same time, the environment tools were studied. At this point, I began creating the tutorial. I captured all the figures that I consider important to make it easy to the students. The tutorial contains a complete logical design cycle. When the tutorial was finished, I started to review the manufacturer documentation about each devices family. The purpose of this review was to characterize the different families to support the device selection in future designs. Another purpose of that characterization was focused on the detection of the best family to include one of its members in a prototyping board for conducting laboratory practices.

Implementación y configuración de un receptor de radio definido por software (SDR) para estudios de propagación

The constant development of digital systems in radio communications demands the adaptation of the current receiving equipment to the new technologies. In this context, a new Software Defined Radio based receiver is being implemented with the aim of carrying out different experiments to analyze the propagation of signals through the atmosphere from a satellite beacon. The receiver selected for this task is the PERSEUS SDR from the Italian company Microtelecom s.r.l. It is a software defined VLF-LF-MF-HF receiver based on an outstanding direct sampling digital architecture which features a 14 bit 80 MSamples/s analog-to-digital converter, a high-performance FPGA-based digital down-converter and a high-speed 480 Mbit/s USB2.0 PC interface. The main goal is to implement the related software and adapt the new receiver to the current working environment. In this paper, SDR technology guidelines are given and PERSEUS receiver digital signal processing is presented with the most remarkable results.

Transformer-coupled converter for voltage modulation techniques

In high performance digital systems as well as in RF systems, voltage scaling and modulation techniques have been adopted to achieve a more efficient processing of the energy. The implementation of such techniques relies on a power supply that is capable of rapidly adjusting the system supply voltage. In this paper, a pulsewidth modulation multiphase topology with magnetic coupling is proposed for its use in voltage modulation techniques. Since the magnetic coupling in this topology is done with transformers instead of coupled inductors, the energy storage is reduced and very fast voltage changes are achieved. Advantages and drawbacks of this topology have been previously presented in the literature and in this paper, the design criteria for implementing a power supply for the envelope elimination and restoration technique in an RF system are presented along with an implementation of the power supply.

Unidad de efectos de audio en Simulink

La tecnología moderna de computación ha permitido cambiar radicalmente la investigación tecnológica en todos los ámbitos. El proceso general utilizado previamente consistía en el desarrollo de prototipos analógicos, creando múltiples versiones del mismo hasta llegar al resultado adecuado. Este es un proceso costoso a nivel económico y de carga de trabajo. Es por ello por lo que el proceso de investigación actual aprovecha las nuevas tecnologías para lograr el objetivo final mediante la simulación. Gracias al desarrollo de software para la simulación de distintas áreas se ha incrementado el ritmo de crecimiento de los avances tecnológicos y reducido el coste de los proyectos en investigación y desarrollo. La simulación, por tanto, permite desarrollar previamente prototipos simulados con un coste mucho menor para así lograr un producto final, el cual será llevado a cabo en su ámbito correspondiente. Este proceso no sólo se aplica en el caso de productos con circuitería, si bien es utilizado también en productos programados. Muchos de los programas actuales trabajan con algoritmos concretos cuyo funcionamiento debe ser comprobado previamente, para después centrarse en la codificación del mismo. Es en este punto donde se encuentra el objetivo de este proyecto, simular algoritmos de procesado digital de la señal antes de la codificación del programa final. Los sistemas de audio están basados en su totalidad en algoritmos de procesado de la señal, tanto analógicos como digitales, siendo estos últimos los que están sustituyendo al mundo analógico mediante los procesadores y los ordenadores. Estos algoritmos son la parte más compleja del sistema, y es la creación de nuevos algoritmos la base para lograr sistemas de audio novedosos y funcionales. Se debe destacar que los grupos de desarrollo de sistemas de audio presentan un amplio número de miembros con cometidos diferentes, separando las funciones de programadores e ingenieros de la señal de audio. Es por ello por lo que la simulación de estos algoritmos es fundamental a la hora de desarrollar nuevos y más potentes sistemas de audio. Matlab es una de las herramientas fundamentales para la simulación por ordenador, la cual presenta utilidades para desarrollar proyectos en distintos ámbitos. Sin embargo, en creciente uso actualmente se encuentra el software Simulink, herramienta especializada en la simulación de alto nivel que simplifica la dificultad de la programación en Matlab y permite desarrollar modelos de forma más rápida. Simulink presenta una completa funcionalidad para el desarrollo de algoritmos de procesado digital de audio. Por ello, el objetivo de este proyecto es el estudio de las capacidades de Simulink para generar sistemas de audio funcionales. A su vez, este proyecto pretende profundizar en los métodos de procesado digital de la señal de audio, logrando al final un paquete de sistemas de audio compatible con los programas de edición de audio actuales. ABSTRACT. Modern computer technology has dramatically changed the technological research in multiple areas. The overall process previously used consisted of the development of analog prototypes, creating multiple versions to reach the proper result. This is an expensive process in terms of an economically level and workload. For this reason actual investigation process take advantage of the new technologies to achieve the final objective through simulation. Thanks to the software development for simulation in different areas the growth rate of technological progress has been increased and the cost of research and development projects has been decreased. Hence, simulation allows previously the development of simulated protoypes with a much lower cost to obtain a final product, which will be held in its respective field. This process is not only applied in the case of circuitry products, but is also used in programmed products. Many current programs work with specific algorithms whose performance should be tested beforehand, which allows focusing on the codification of the program. This is the main point of this project, to simulate digital signal processing algorithms before the codification of the final program. Audio systems are entirely based on signal processing, both analog and digital systems, being the digital systems which are replacing the analog world thanks to the processors and computers. This algorithms are the most complex part of every system, and the creation of new algorithms is the most important step to achieve innovative and functional new audio systems. It should be noted that development groups of audio systems have a large number of members with different roles, separating them into programmers and audio signal engineers. For this reason, the simulation of this algorithms is essential when developing new and more powerful audio systems. Matlab is one of the most important tools for computer simulation, which has utilities to develop projects in different areas. However, the use of the Simulink software is constantly growing. It is a simulation tool specialized in high-level simulations which simplifies the difficulty of programming in Matlab and allows the developing of models faster. Simulink presents a full functionality for the development of algorithms for digital audio processing. Therefore, the objective of this project is to study the posibilities of Simulink to generate funcional audio systems. In turn, this projects aims to get deeper into the methods of digital audio signal processing, making at the end a software package of audio systems compatible with the current audio editing software.

Transmission of digital chaotic and information-bearing signals in optical communication systems

A new proposal to have secure communications in a system is reported. The basis is the use of a synchronized digital chaotic systems, sending the information signal added to an initial chaos. The received signal is analyzed by another chaos generator located at the receiver and, by a logic boolean function of the chaotic and the received signals, the original information is recovered. One of the most important facts of this system is that the bandwidth needed by the system remain the same with and without chaos.

Digital Coherent Receivers and Advanced Optical Modulation Formats in 100 and 200 Gb/s DWDM Systems

Recent advances in coherent optical receivers is reviewed. Digital-Signal-Processing (DSP) based phase and polarization management techniques make coherent detection robust and feasible. With coherent detection, the complex field of the received optical signal is fully recovered, allowing compensation of linear and nonlinear optical impairments including chromatic dispersion (CD) and polarization-mode dispersion (PMD) using digital filters. Coherent detection and advanced optical modulation formats have become a key ingredient to the design of modern dense wavelength-division multiplexed (DWDM) optical broadband networks. In this paper, firstly we present the different subsystems of a digital coherent optical receiver, and secondly, we will compare the performance of some multi-level and multi-dimensional modulation formats in some physical impairments and in high spectral-efficiency (SE) and high-capacity DWDM transmissions, simulating the DSP with Matlab and the optical network performance with OptiSystem software.

Structure function and Multifractal spectrum applied to Digital Elevation Model

A Digital Elevation Model (DEM) provides the information basis used for many geographic applications such as topographic and geomorphologic studies, landscape through GIS (Geographic Information Systems) among others. The DEM capacity to represent Earth?s surface depends on the surface roughness and the resolution used. Each DEM pixel depends on the scale used characterized by two variables: resolution and extension of the area studied. DEMs can vary in resolution and accuracy by the production method, although there are statistical characteristics that keep constant or very similar in a wide range of scales. Based on this property, several techniques have been applied to characterize DEM through multiscale analysis directly related to fractal geometry: multifractal spectrum and the structure function. The comparison of the results by both methods is discussed. The study area is represented by a 1024 x 1024 data matrix obtained from a DEM with a resolution of 10 x 10 m each point, which correspond with a region known as ?Monte de El Pardo? a property of Spanish National Heritage (Patrimonio Nacional Español) of 15820 Ha located to a short distance from the center of Madrid. Manzanares River goes through this area from North to South. In the southern area a reservoir is found with a capacity of 43 hm3, with an altitude of 603.3 m till 632 m when it is at the highest capacity. In the middle of the reservoir the minimum altitude of this area is achieved.

Soil fragmentation study applying different tillage systems

Runoff generation depends on rainfall, infiltration, interception, and surface depressional storage. Surface depressional storage depends on surface microtopography, usually quantified trough soil surface roughness (SSR). SSR is subject to spatial and temporal changes that create a high variability. In an agricultural environment, tillage operations produce abrupt changes in roughness. Subsequent rainfall gradually decreases roughness. Beside it, local variation in soil properties and hydrology cause its SSR to vary spatially at different scales. The methods commonly used to measure it involve collecting point elevations in regular grids using laser profilers or scanners, digital close range stereo-photogrammetry and terrestrial laser scanning or LIDAR systems. In this case, a laser-scanning instrument was used to obtain representative digital elevation models (DEMs) at a grid resolution of 7.2x7.2mm that cover an area of 0.9x0.9m. The DEMs were obtained from two study sites with different soils. The first study site was an experimental field on which five conventional tillage methods were applied. The second study site was a large olive orchard with trees planted at 7.5x5.0m and bare soils between rows. Here, three tillage treatments were applied. In this work we have evaluated the spatial variability of SSR at several scales studying differences in height calculated from points separated by incremental distances h were raised to power values q (from 0 to 4 in steps of 0.1). The q = 2 data were studied as a semivariogram model. The logarithm of average differences plotted vs. log h were characterized by their slope, ?(q). Structure functions [?(q) vs. q] were fitted showing that data had nonlinear structure functions typical of multiscale phenomena. Comparisson of the two types of soil in their respective structure functions are shown.

Current Trends in Pan-European Identity Management Systems

The demand for electronic identity has grown as a result of governments? promotion of e-Government, in which the citizen-public administration relationship often has a strictly personal nature and requires digital identification systems that are univocal, secure, and global. The management of this identity by public administrations is an important challenge, accentuated when interoperability among public administrations of different countries become necessary. In this paper current trends in pan-euroean identity management systems are analysized and a outlook of the future European scenary is shown.

Digital chaos synchronization in optical networks

A new method to obtain digital chaos synchronization between two systems is reported. It is based on the use of Optically Programmable Logic Cells as chaos generators. When these cells are feedbacked, periodic and chaotic behaviours are obtained. They depend on the ratio between internal and external delay times. Chaos synchronization is obtained if a common driving signal feeds both systems. A control to impose the same boundary conditions to both systems is added to the emitter. New techniques to analyse digital chaos are presented. The main application of these structures is to obtain secure communications in optical networks.

Synchronizing chaotic optically-programmable digital circuits

In this paper an approach to the synchronization of chaotic circuits has been reported. It is based on an optically programmable logic cell and the signals involved are fully digital. It is based on the reception of the same input signal on sender and receiver and from this approach, with a posterior correlation between both outputs, an identical chaotic output is obtained in both systems. No conversion from analog to digital signals is needed. The model here presented is based on a computer simulation.