Non-linear gain - look-up table based approach for modeling a family of DC to DC converters based on transient response analysis

The purpose of this work is to propose a structure for simulating power systems using behavioral models of nonlinear DC to DC converters implemented through a look-up table of gains. This structure is specially designed for converters whose output impedance depends on the load current level, e.g. quasi-resonant converters. The proposed model is a generic one whose parameters can be obtained by direct measuring the transient response at different operating points. It also includes optional functionalities for modeling converters with current limitation and current sharing in paralleling characteristics. The pusposed structured also allows including aditional characteristics of the DC to DC converter as the efficency as a function of the input voltage and the output current or overvoltage and undervoltage protections. In addition, this proposed model is valid for overdamped and underdamped situations.

An overview of fast DC-DC converters for envelope amplifier in RF transmitters

In the last years, RF power amplifiers are taking advantage of the switched dc-dc converters to use them in several architectures that may improve the efficiency of the amplifier, keeping a good linearity. The use of linearization techniques such as Envelope Elimination and Restoration (EER) and Envelope Tracking (ET) requires a very fast dc-dc power converter to provide variable voltage supply to the power amplifier but theoretically the efficiency can be much higher than using the classical amplifiers belonging to classes A, B or AB. The purpose of this paper is to analyze the state of the art of the power converters used as envelope amplifiers in this application where a fast output voltage variation is required. The power topologies will be explored and several important parameters such as efficiency, bandwidth and output voltage range will be discussed.

Advanced Control for Very Fast DC-DC Converters Based on Hysteresis of the C-out Current

The bandwidth achievable by using voltage mode control or current mode control in switch-mode power supply is limited by the switching frequency. Fast transient response requires high switching frequency, although lower switching frequencies could be more suitable for higher efficiency. This paper proposes the use of hysteretic control of the output capacitor $(C_{out})$ current to improve the dynamic response of the buck converter. An external voltage loop is required to accurately regulate the output voltage. The design of the hysteretic loop and the voltage loop are presented. Besides, it is presented a non-invasive current sensor that allows measuring the current in the capacitor. This strategy has been applied for DVS (dynamic voltage scaling) on a 5 MHz buck converter. Experimental results validate the proposed control technique and show fast transient response from 1.5 V to 2.5 V in 2 $mu{rm s}$.

Output Impedance Correction Circuit (OICC): A New Concept to Improve the Dynamic Response of DC/DC Converters with Additional Energy Path

El desarrollo da las nuevas tecnolog��as permite a los ingenieros llevar al l��mite el funcionamiento de los circuitos integrados (Integrated Circuits, IC). Las nuevas generaciones de procesadores, DSPs o FPGAs son capaces de procesar la informaci��n a una alta velocidad, con un alto consumo de energ��a, o esperar en modo de baja potencia con el m��nimo consumo posible. Esta gran variaci��n en el consumo de potencia y el corto tiempo necesario para cambiar de un nivel al otro, afecta a las especificaciones del M��dulo de Regulador de Tensi��n (Voltage Regulated Module, VRM) que alimenta al IC. Adem��s, las caracter��sticas adicionales obligatorias, tales como adaptaci��n del nivel de tensi��n (Adaptive Voltage Positioning, AVP) y escalado din��mico de la tensi��n (Dynamic Voltage Scaling, DVS), imponen requisitos opuestas en el dise��o de la etapa de potencia del VRM. Para poder soportar las altas variaciones de los escalones de carga, el condensador de filtro de salida del VRM se ha de sobredimensionar, penalizando la densidad de energ��a y el rendimiento durante la operaci��n de DVS. Por tanto, las actuales tendencias de investigaci��n se centran en mejorar la respuesta din��mica del VRM, mientras se reduce el tama��o del condensador de salida. La reducci��n del condensador de salida lleva a menor coste y una prolongaci��n de la vida del sistema ya que se podr��a evitar el uso de condensadores voluminosos, normalmente implementados con condensadores OSCON. Una ventaja adicional es que reduciendo el condensador de salida, el DVS se puede realizar m��s r��pido y con menor estr��s de la etapa de potencia, ya que la cantidad de carga necesaria para cambiar la tensi��n de salida es menor. El comportamiento din��mico del sistema con un control lineal (Control Modo Tensi��n, VMC, o Control Corriente de Pico, Peak Current Mode Control, PCMC,���) est�� limitado por la frecuencia de conmutaci��n del convertidor y por el tama��o del filtro de salida. La reducci��n del condensador de salida se puede lograr incrementando la frecuencia de conmutaci��n, as�� como incrementando el ancho de banda del sistema, y/o aplicando controles avanzados no-lineales. Usando esos controles, las variables del estado se saturan para conseguir el nuevo r��gimen permanente en un tiempo m��nimo, as�� como el filtro de salida, m��s espec��ficamente la pendiente de la corriente de la bobina, define la respuesta de la tensi��n de salida. Por tanto, reduciendo la inductancia de la bobina de salida, la corriente de bobina llega m��s r��pido al nuevo r��gimen permanente, por lo que una menor cantidad de carga es tomada del condensador de salida durante el tr��nsito. El inconveniente de esa propuesta es que el rendimiento del sistema es penalizado debido al incremento de p��rdidas de conmutaci��n y las corrientes RMS. Para conseguir tanto la reducci��n del condensador de salida como el alto rendimiento del sistema, mientras se satisfacen las estrictas especificaciones din��micas, un convertidor multifase es adoptado como est��ndar para aplicaciones VRM. Para asegurar el reparto de las corrientes entre fases, el convertidor multifase se suele implementar con control de modo de corriente. Para superar la limitaci��n impuesta por el filtro de salida, la segunda posibilidad para reducir el condensador de salida es aplicar alguna modificaci��n topol��gica (Topologic modifications) de la etapa b��sica de potencia para incrementar la pendiente de la corriente de bobina y as�� reducir la duraci��n de tr��nsito. Como el transitorio se ha reducido, una menor cantidad de carga es tomada del condensador de salida bajo el mismo escal��n de la corriente de salida, con lo cual, el condensador de salida se puede reducir para lograr la misma desviaci��n de la tensi��n de salida. La tercera posibilidad para reducir el condensador de salida del convertidor es introducir un camino auxiliar de energ��a (additional energy path, AEP) para compensar el desequilibrio de la carga del condensador de salida reduciendo consecuentemente la duraci��n del transitorio y la desviaci��n de la tensi��n de salida. De esta manera, durante el r��gimen permanente, el sistema tiene un alto rendimiento debido a que el convertidor principal con bajo ancho de banda es dise��ado para trabajar con una frecuencia de conmutaci��n moderada para conseguir requisitos est��ticos. Por otro lado, el comportamiento din��mico durante los transitorios es determinado por el AEP con un alto ancho de banda. El AEP puede ser implementado como un camino resistivo, como regulador lineal (Linear regulator, LR) o como un convertidor conmutado. Las dos primeras implementaciones proveen un mayor ancho de banda, acosta del incremento de p��rdidas durante el transitorio. Por otro lado, la implementaci��n del convertidor computado presenta menor ancho de banda, limitado por la frecuencia de conmutaci��n, aunque produce menores p��rdidas comparado con las dos anteriores implementaciones. Dependiendo de la aplicaci��n, la implementaci��n y la estrategia de control del sistema, hay una variedad de soluciones propuestas en el Estado del Arte (State-of-the-Art, SoA), teniendo diferentes propiedades donde una soluci��n ofrece m��s ventajas que las otras, pero tambi��n unas desventajas. En general, un sistema con AEP ideal deber��a tener las siguientes propiedades: 1. El impacto del AEP a las p��rdidas del sistema deber��a ser m��nimo. A lo largo de la operaci��n, el AEP genera p��rdidas adicionales, con lo cual, en el caso ideal, el AEP deber��a trabajar por un peque��o intervalo de tiempo, solo durante los tr��nsitos; la otra opci��n es tener el AEP constantemente activo pero, por la compensaci��n del rizado de la corriente de bobina, se generan p��rdidas innecesarias. 2. El AEP deber��a ser activado inmediatamente para minimizar la desviaci��n de la tensi��n de salida. Para conseguir una activaci��n casi instant��nea, el sistema puede ser informado por la carga antes del escal��n o el sistema puede observar la corriente del condensador de salida, debido a que es la primera variable del estado que act��a a la perturbaci��n de la corriente de salida. De esa manera, el AEP es activado con casi cero error de la tensi��n de salida, logrando una menor desviaci��n de la tensi��n de salida. 3. El AEP deber��a ser desactivado una vez que el nuevo r��gimen permanente es detectado para evitar los transitorios adicionales de establecimiento. La mayor��a de las soluciones de SoA estiman la duraci��n del transitorio, que puede provocar un transitorio adicional si la estimaci��n no se ha hecho correctamente (por ejemplo, si la corriente de bobina del convertidor principal tiene un nivel superior o inferior al necesitado, el regulador lento del convertidor principal tiene que compensar esa diferencia una vez que el AEP es desactivado). Otras soluciones de SoA observan las variables de estado, asegurando que el sistema llegue al nuevo r��gimen permanente, o pueden ser informadas por la carga. 4. Durante el transitorio, como m��nimo un subsistema, o bien el convertidor principal o el AEP, deber��a operar en el lazo cerrado. Implementando un sistema en el lazo cerrado, preferiblemente el subsistema AEP por su ancho de banda elevado, se incrementa la robustez del sistema a los par��sitos. Adem��s, el AEP puede operar con cualquier tipo de corriente de carga. Las soluciones que funcionan en el lazo abierto suelen preformar el control de balance de carga con m��nimo tiempo, as�� reducen la duraci��n del transitorio y tienen un impacto menor a las p��rdidas del sistema. Por otro lado, esas soluciones demuestran una alta sensibilidad a las tolerancias y par��sitos de los componentes. 5. El AEP deber��a inyectar la corriente a la salida en una manera controlada, as�� se reduce el riesgo de unas corrientes elevadas y potencialmente peligrosas y se incrementa la robustez del sistema bajo las perturbaciones de la tensi��n de entrada. Ese problema suele ser relacionado con los sistemas donde el AEP es implementado como un convertidor auxiliar. El convertidor auxiliar es dise��ado para una potencia baja, con lo cual, los dispositivos elegidos son de baja corriente/potencia. Si la corriente no es controlada, bajo un pico de tensi��n de entrada provocada por otro parte del sistema (por ejemplo, otro convertidor conectado al mismo bus), se puede llegar a un pico en la corriente auxiliar que puede causar la perturbaci��n de tensi��n de salida e incluso el fallo de los dispositivos del convertidor auxiliar. Sin embargo, cuando la corriente es controlada, usando control del pico de corriente o control con hist��resis, la corriente auxiliar tiene el control con prealimentaci��n (feed-forward) de tensi��n de entrada y la corriente es definida y limitada. Por otro lado, si la soluci��n utiliza el control de balance de carga, el sistema puede actuar de forma deficiente si la tensi��n de entrada tiene un valor diferente del nominal, provocando que el AEP inyecta/toma m��s/menos carga que necesitada. 6. Escalabilidad del sistema a convertidores multifase. Como ya ha sido comentado anteriormente, para las aplicaciones VRM por la corriente de carga elevada, el convertidor principal suele ser implementado como multifase para distribuir las perdidas entre las fases y bajar el estr��s t��rmico de los dispositivos. Para asegurar el reparto de las corrientes, normalmente un control de modo corriente es usado. Las soluciones de SoA que usan VMC son limitadas a la implementaci��n con solo una fase. Esta tesis propone un nuevo m��todo de control del flujo de energ��a por el AEP y el convertidor principal. El concepto propuesto se basa en la inyecci��n controlada de la corriente auxiliar al nodo de salida donde la amplitud de la corriente es n-1 veces mayor que la corriente del condensador de salida con las direcciones apropiadas. De esta manera, el AEP genera un condensador virtual cuya capacidad es n veces mayor que el condensador f��sico y reduce la impedancia de salida. Como el concepto propuesto reduce la impedancia de salida usando el AEP, el concepto es llamado Output Impedance Correction Circuit (OICC) concept. El concepto se desarrolla para un convertidor tipo reductor s��ncrono multifase con control modo de corriente CMC (incluyendo e implementaci��n con una fase) y puede operar con la tensi��n de salida constante o con AVP. Adem��s, el concepto es extendido a un convertidor de una fase con control modo de tensi��n VMC. Durante la operaci��n, el control de tensi��n de salida de convertidor principal y control de corriente del subsistema OICC est��n siempre cerrados, incrementando la robustez a las tolerancias de componentes y a los par��sitos del cirquito y permitiendo que el sistema se pueda enfrentar a cualquier tipo de la corriente de carga. Seg��n el m��todo de control propuesto, el sistema se puede encontrar en dos estados: durante el r��gimen permanente, el sistema se encuentra en el estado Idle y el subsistema OICC esta desactivado. Por otro lado, durante el transitorio, el sistema se encuentra en estado Activo y el subsistema OICC est�� activado para reducir la impedancia de salida. El cambio entre los estados se hace de forma aut��noma: el sistema entra en el estado Activo observando la corriente de condensador de salida y vuelve al estado Idle cunado el nuevo r��gimen permanente es detectado, observando las variables del estado. La validaci��n del concepto OICC es hecha aplic��ndolo a un convertidor tipo reductor s��ncrono con dos fases y de 30W cuyo condensador de salida tiene capacidad de 140��F, mientras el factor de multiplicaci��n n es 15, generando en el estado Activo el condensador virtual de 2.1mF. El subsistema OICC es implementado como un convertidor tipo reductor s��ncrono con PCMC. Comparando el funcionamiento del convertidor con y sin el OICC, los resultados demuestran que se ha logrado una reducci��n de la desviaci��n de tensi��n de salida con factor 12, tanto con funcionamiento b��sico como con funcionamiento AVP. Adem��s, los resultados son comparados con un prototipo de referencia que tiene la misma etapa de potencia y un condensador de salida f��sico de 2.1mF. Los resultados demuestran que los dos sistemas tienen el mismo comportamiento din��mico. M��s aun, se ha cuantificado el impacto en las p��rdidas del sistema operando bajo una corriente de carga pulsante y bajo DVS. Se demuestra que el sistema con OICC mejora el rendimiento del sistema, considerando las p��rdidas cuando el sistema trabaja con la carga pulsante y con DVS. Por lo ��ltimo, el condensador de salida de sistema con OICC es mucho m��s peque��o que el condensador de salida del convertidor de referencia, con lo cual, por usar el concepto OICC, la densidad de energ��a se incrementa. En resumen, las contribuciones principales de la tesis son: ��� El concepto propuesto de Output Impedance Correction Circuit (OICC), ��� El control a nivel de sistema basado en el m��todo usado para cambiar los estados de operaci��n, ��� La implementaci��n del subsistema OICC en lazo cerrado conjunto con la implementaci��n del convertidor principal, ��� La cuantificaci��n de las perdidas din��micas bajo la carga pulsante y bajo la operaci��n DVS, y ��� La robustez del sistema bajo la variaci��n del condensador de salida y bajo los escalones de carga consecutiva. ABSTRACT Development of new technologies allows engineers to push the performance of the integrated circuits to its limits. New generations of processors, DSPs or FPGAs are able to process information with high speed and high consumption or to wait in low power mode with minimum possible consumption. This huge variation in power consumption and the short time needed to change from one level to another, affect the specifications of the Voltage Regulated Module (VRM) that supplies the IC. Furthermore, additional mandatory features, such as Adaptive Voltage Positioning (AVP) and Dynamic Voltage Scaling (DVS), impose opposite trends on the design of the VRM power stage. In order to cope with high load-step amplitudes, the output capacitor of the VRM power stage output filter is drastically oversized, penalizing power density and the efficiency during the DVS operation. Therefore, the ongoing research trend is directed to improve the dynamic response of the VRM while reducing the size of the output capacitor. The output capacitor reduction leads to a smaller cost and longer life-time of the system since the big bulk capacitors, usually implemented with OSCON capacitors, may not be needed to achieve the desired dynamic behavior. An additional advantage is that, by reducing the output capacitance, dynamic voltage scaling (DVS) can be performed faster and with smaller stress on the power stage, since the needed amount of charge to change the output voltage is smaller. The dynamic behavior of the system with a linear control (Voltage mode control, VMC, Peak Current Mode Control, PCMC,���) is limited by the converter switching frequency and filter size. The reduction of the output capacitor can be achieved by increasing the switching frequency of the converter, thus increasing the bandwidth of the system, and/or by applying advanced non-linear controls. Applying nonlinear control, the system variables get saturated in order to reach the new steady-state in a minimum time, thus the output filter, more specifically the output inductor current slew-rate, determines the output voltage response. Therefore, by reducing the output inductor value, the inductor current reaches faster the new steady state, so a smaller amount of charge is taken from the output capacitor during the transient. The drawback of this approach is that the system efficiency is penalized due to increased switching losses and RMS currents. In order to achieve both the output capacitor reduction and high system efficiency, while satisfying strict dynamic specifications, a Multiphase converter system is adopted as a standard for VRM applications. In order to ensure the current sharing among the phases, the multiphase converter is usually implemented with current mode control. In order to overcome the limitation imposed by the output filter, the second possibility to reduce the output capacitor is to apply Topologic modifications of the basic power stage topology in order to increase the slew-rate of the inductor current and, therefore, reduce the transient duration. Since the transient is reduced, smaller amount of charge is taken from the output capacitor under the same load current, thus, the output capacitor can be reduced to achieve the same output voltage deviation. The third possibility to reduce the output capacitor of the converter is to introduce an additional energy path (AEP) to compensate the charge unbalance of the output capacitor, consequently reducing the transient time and output voltage deviation. Doing so, during the steady-state operation the system has high efficiency because the main low-bandwidth converter is designed to operate at moderate switching frequency, to meet the static requirements, whereas the dynamic behavior during the transients is determined by the high-bandwidth auxiliary energy path. The auxiliary energy path can be implemented as a resistive path, as a Linear regulator, LR, or as a switching converter. The first two implementations provide higher bandwidth, at the expense of increasing losses during the transient. On the other hand, the switching converter implementation presents lower bandwidth, limited by the auxiliary converter switching frequency, though it produces smaller losses compared to the two previous implementations. Depending on the application, the implementation and the control strategy of the system, there is a variety of proposed solutions in the State-of-the-Art (SoA), having different features where one solution offers some advantages over the others, but also some disadvantages. In general, an ideal additional energy path system should have the following features: 1. The impact on the system losses should be minimal. During its operation, the AEP generates additional losses, thus ideally, the AEP should operate for a short period of time, only when the transient is occurring; the other option is to have the AEP constantly on, but due to the inductor current ripple compensation at the output, unnecessary losses are generated. 2. The AEP should be activated nearly instantaneously to prevent bigger output voltage deviation. To achieve near instantaneous activation, the converter system can be informed by the load prior to the load-step or the system can observe the output capacitor current, which is the first system state variable that reacts on the load current perturbation. In this manner, the AEP is turned on with near zero output voltage error, providing smaller output voltage deviation. 3. The AEP should be deactivated once the new steady state is reached to avoid additional settling transients. Most of the SoA solutions estimate duration of the transient which may cause additional transient if the estimation is not performed correctly (e.g. if the main converter inductor current has higher or lower value than needed, the slow regulator of the main converter needs to compensate the difference after the AEP is deactivated). Other SoA solutions are observing state variables, ensuring that the system reaches the new steady state or they are informed by the load. 4. During the transient, at least one subsystem, either the main converter or the AEP, should be in closed-loop. Implementing a closed loop system, preferably the AEP subsystem, due its higher bandwidth, increases the robustness under system tolerances and circuit parasitic. In addition, the AEP can operate with any type of load. The solutions that operate in open loop usually perform minimum time charge balance control, thus reducing the transient length and minimizing the impact on the losses, however they are very sensitive to tolerances and parasitics. 5. The AEP should inject current at the output in a controlled manner, thus reducing the risk of high and potentially damaging currents and increasing robustness on the input voltage deviation. This issue is mainly related to the systems where AEP is implemented as auxiliary converter. The auxiliary converter is designed for small power and, as such, the MOSFETs are rated for small power/currents. If the current is not controlled, due to the some unpredicted spike in input voltage caused by some other part of the system (e.g. different converter), it may lead to a current spike in auxiliary current which will cause the perturbation of the output voltage and even failure of the switching components of auxiliary converter. In the case when the current is controlled, using peak CMC or Hysteretic Window CMC, the auxiliary converter has inherent feed-forwarding of the input voltage in current control and the current is defined and limited. Furthermore, if the solution employs charge balance control, the system may perform poorly if the input voltage has different value than the nominal, causing that AEP injects/extracts more/less charge than needed. 6. Scalability of the system to multiphase converters. As commented previously, in VRM applications, due to the high load currents, the main converters are implemented as multiphase to redistribute losses among the modules, lowering temperature stress of the components. To ensure the current sharing, usually a Current Mode Control (CMC) is employed. The SoA solutions that are implemented with VMC are limited to a single stage implementation. This thesis proposes a novel control method of the energy flow through the AEP and the main converter system. The proposed concept relays on a controlled injection of the auxiliary current at the output node where the instantaneous current value is n-1 times bigger than the output capacitor current with appropriate directions. Doing so, the AEP creates an equivalent n times bigger virtual capacitor at the output, thus reducing the output impedance. Due to the fact that the proposed concept reduces the output impedance using the AEP, it has been named the Output Impedance Correction Circuit (OICC) concept. The concept is developed for a multiphase CMC synchronous buck converter (including a single phase implementation), operating with a constant output voltage and with AVP feature. Further, it is extended to a single phase VMC synchronous buck converter. During the operation, the main converter voltage loop and the OICC subsystem capacitor current loop is constantly closed, increasing the robustness under system tolerances and circuit parasitic and allowing the system to operate with any load-current shape or pattern. According to the proposed control method, the system operates in two states: during the steady-state the system is in the Idle state and the OICC subsystem is deactivated, while during the load-step transient the system is in the Active state and the OICC subsystem is activated in order to reduce the output impedance. The state changes are performed autonomously: the system enters in the Active state by observing the output capacitor current and it returns back to the Idle state when the steady-state operation is detected by observing the state variables. The validation of the OICC concept has been done by applying it to a 30W two phase synchronous buck converter with 140��F output capacitor and with the multiplication factor n equal to 15, generating during the Active state equivalent output capacitor of 2.1mF. The OICC subsystem is implemented as single phase PCMC synchronous buck converter. Comparing the converter operation with and without the OICC the results demonstrate that the 12 times reduction of the output voltage deviation is achieved, for both basic operation and for the AVP operation. Furthermore, the results have been compared to a reference prototype which has the same power stage and a fiscal output capacitor of 2.1mF. The results show that the two systems have the same dynamic behavior. Moreover, an impact on the system losses under the pulsating load and DVS operation has been quantified and it has been demonstrated that the OICC system has improved the system efficiency, considering the losses when the system operates with the pulsating load and the DVS operation. Lastly, the output capacitor of the OICC system is much smaller than the reference design output capacitor, therefore, by applying the OICC concept the power density can be increased. In summary, the main contributions of the thesis are: ��� The proposed Output Impedance Correction Circuit (OICC) concept, ��� The system level control based on the used approach to change the states of operation, ��� The OICC subsystem closed-loop implementation, together with the main converter implementation, ��� The dynamic losses under the pulsating load and the DVS operation quantification, and ��� The system robustness on the capacitor impedance variation and consecutive load-steps.

Novel Inductor���less Conversion Strategy Based on Multiphase Transformer���Coupled Converters: Analysis, Design and Applications

There are many the requirements that modern power converters should fulfill. Most of the applications where these converters are used, demand smaller converters with high efficiency, improved power density and a fast dynamic response. For instance, loads like microprocessors demand aggressive current steps with very high slew rates (100A/mus and higher); besides, during these load steps, the supply voltage of the microprocessor should be kept within tight limits in order to ensure its correct performance. The accomplishment of these requirements is not an easy task; complex solutions like advanced topologies - such as multiphase converters- as well as advanced control strategies are often needed. Besides, it is also necessary to operate the converter at high switching frequencies and to use capacitors with high capacitance and low ESR. Improving the dynamic response of power converters does not rely only on the control strategy but also the power topology should be suited to enable a fast dynamic response. Moreover, in later years, a fast dynamic response does not only mean accomplishing fast load steps but output voltage steps are gaining importance as well. At least, two applications that require fast voltage changes can be named: Low power microprocessors. In these devices, the voltage supply is changed according to the workload and the operating frequency of the microprocessor is changed at the same time. An important reduction in voltage dependent losses can be achieved with such changes. This technique is known as Dynamic Voltage Scaling (DVS). Another application where important energy savings can be achieved by means of changing the supply voltage are Radio Frequency Power Amplifiers. For example, RF architectures based on ���Envelope Tracking��� and ���Envelope Elimination and Restoration��� techniques can take advantage of voltage supply modulation and accomplish important energy savings in the power amplifier. However, in order to achieve these efficiency improvements, a power converter with high efficiency and high enough bandwidth (hundreds of kHz or even tens of MHz) is necessary in order to ensure an adequate supply voltage. The main objective of this Thesis is to improve the dynamic response of DC-DC converters from the point of view of the power topology. And the term dynamic response refers both to the load steps and the voltage steps; it is also interesting to modulate the output voltage of the converter with a specific bandwidth. In order to accomplish this, the question of what is it that limits the dynamic response of power converters should be answered. Analyzing this question leads to the conclusion that the dynamic response is limited by the power topology and specifically, by the filter inductance of the converter which is found in series between the input and the output of the converter. The series inductance is the one that determines the gain of the converter and provides the regulation capability. Although the energy stored in the filter inductance enables the regulation and the capability of filtering the output voltage, it imposes a limitation which is the concern of this Thesis. The series inductance stores energy and prevents the current from changing in a fast way, limiting the slew rate of the current through this inductor. Different solutions are proposed in the literature in order to reduce the limit imposed by the filter inductor. Many publications proposing new topologies and improvements to known topologies can be found in the literature. Also, complex control strategies are proposed with the objective of improving the dynamic response in power converters. In the proposed topologies, the energy stored in the series inductor is reduced; examples of these topologies are Multiphase converters, Buck converter operating at very high frequency or adding a low impedance path in parallel with the series inductance. Control techniques proposed in the literature, focus on adjusting the output voltage as fast as allowed by the power stage; examples of these control techniques are: hysteresis control, V 2 control, and minimum time control. In some of the proposed topologies, a reduction in the value of the series inductance is achieved and with this, the energy stored in this magnetic element is reduced; less stored energy means a faster dynamic response. However, in some cases (as in the high frequency Buck converter), the dynamic response is improved at the cost of worsening the efficiency. In this Thesis, a drastic solution is proposed: to completely eliminate the series inductance of the converter. This is a more radical solution when compared to those proposed in the literature. If the series inductance is eliminated, the regulation capability of the converter is limited which can make it difficult to use the topology in one-converter solutions; however, this topology is suitable for power architectures where the energy conversion is done by more than one converter. When the series inductor is eliminated from the converter, the current slew rate is no longer limited and it can be said that the dynamic response of the converter is independent from the switching frequency. This is the main advantage of eliminating the series inductor. The main objective, is to propose an energy conversion strategy that is done without series inductance. Without series inductance, no energy is stored between the input and the output of the converter and the dynamic response would be instantaneous if all the devices were ideal. If the energy transfer from the input to the output of the converter is done instantaneously when a load step occurs, conceptually it would not be necessary to store energy at the output of the converter (no output capacitor COUT would be needed) and if the input source is ideal, the input capacitor CIN would not be necessary. This last feature (no CIN with ideal VIN) is common to all power converters. However, when the concept is actually implemented, parasitic inductances such as leakage inductance of the transformer and the parasitic inductance of the PCB, cannot be avoided because they are inherent to the implementation of the converter. These parasitic elements do not affect significantly to the proposed concept. In this Thesis, it is proposed to operate the converter without series inductance in order to improve the dynamic response of the converter; however, on the other side, the continuous regulation capability of the converter is lost. It is said continuous because, as it will be explained throughout the Thesis, it is indeed possible to achieve discrete regulation; a converter without filter inductance and without energy stored in the magnetic element, is capable to achieve a limited number of output voltages. The changes between these output voltage levels are achieved in a fast way. The proposed energy conversion strategy is implemented by means of a multiphase converter where the coupling of the phases is done by discrete two-winding transformers instead of coupledinductors since transformers are, ideally, no energy storing elements. This idea is the main contribution of this Thesis. The feasibility of this energy conversion strategy is first analyzed and then verified by simulation and by the implementation of experimental prototypes. Once the strategy is proved valid, different options to implement the magnetic structure are analyzed. Three different discrete transformer arrangements are studied and implemented. A converter based on this energy conversion strategy would be designed with a different approach than the one used to design classic converters since an additional design degree of freedom is available. The switching frequency can be chosen according to the design specifications without penalizing the dynamic response or the efficiency. Low operating frequencies can be chosen in order to favor the efficiency; on the other hand, high operating frequencies (MHz) can be chosen in order to favor the size of the converter. For this reason, a particular design procedure is proposed for the ���inductorless��� conversion strategy. Finally, applications where the features of the proposed conversion strategy (high efficiency with fast dynamic response) are advantageus, are proposed. For example, in two-stage power architectures where a high efficiency converter is needed as the first stage and there is a second stage that provides the fine regulation. Another example are RF power amplifiers where the voltage is modulated following an envelope reference in order to save power; in this application, a high efficiency converter, capable of achieving fast voltage steps is required. The main contributions of this Thesis are the following: The proposal of a conversion strategy that is done, ideally, without storing energy in the magnetic element. The validation and the implementation of the proposed energy conversion strategy. The study of different magnetic structures based on discrete transformers for the implementation of the proposed energy conversion strategy. To elaborate and validate a design procedure. To identify and validate applications for the proposed energy conversion strategy. It is important to remark that this work is done in collaboration with Intel. The particular features of the proposed conversion strategy enable the possibility of solving the problems related to microprocessor powering in a different way. For example, the high efficiency achieved with the proposed conversion strategy enables it as a good candidate to be used for power conditioning, as a first stage in a two-stage power architecture for powering microprocessors.

A methodology to analyze, design and implement very fast and robust controls of Buck-type converters

La electr��nica digital moderna presenta un desaf��o a los dise��adores de sistemas de potencia. El creciente alto rendimiento de microprocesadores, FPGAs y ASICs necesitan sistemas de alimentaci��n que cumplan con requirimientos din��micos y est��ticos muy estrictos. Espec��ficamente, estas alimentaciones son convertidores DC-DC de baja tensi��n y alta corriente que necesitan ser dise��ados para tener un peque��o rizado de tensi��n y una peque��a desviaci��n de tensi��n de salida bajo transitorios de carga de una alta pendiente. Adem��s, dependiendo de la aplicaci��n, se necesita cumplir con otros requerimientos tal y como proveer a la carga con ���Escalado din��mico de tensi��n���, donde el convertidor necesitar cambiar su tensi��n de salida tan r��pidamente posible sin sobreoscilaciones, o ���Posicionado Adaptativo de la Tensi��n��� donde la tensi��n de salida se reduce ligeramente cuanto m��s grande sea la potencia de salida. Por supuesto, desde el punto de vista de la industria, las figuras de m��rito de estos convertidores son el coste, la eficiencia y el tama��o/peso. Idealmente, la industria necesita un convertidor que es m��s barato, m��s eficiente, m��s peque��o y que a��n as�� cumpla con los requerimienos din��micos de la aplicaci��n. En este contexto, varios enfoques para mejorar la figuras de m��rito de estos convertidores se han seguido por la industria y la academia tales como mejorar la topolog��a del convertidor, mejorar la tecnolog��a de semiconducores y mejorar el control. En efecto, el control es una parte fundamental en estas aplicaciones ya que un control muy r��pido hace que sea m��s f��cil que una determinada topolog��a cumpla con los estrictos requerimientos din��micos y, consecuentemente, le da al dise��ador un margen de libertar m��s amplio para mejorar el coste, la eficiencia y/o el tama��o del sistema de potencia. En esta tesis, se investiga c��mo dise��ar e implementar controles muy r��pidos para el convertidor tipo Buck. En esta tesis se demuestra que medir la tensi��n de salida es todo lo que se necesita para lograr una respuesta casi ��ptima y se propone una gu��a de dise��o unificada para controles que s��lo miden la tensi��n de salida Luego, para asegurar robustez en controles muy r��pidos, se proponen un modelado y un an��lisis de estabilidad muy precisos de convertidores DC-DC que tienen en cuenta circuiter��a para sensado y elementos par��sitos cr��ticos. Tambi��n, usando este modelado, se propone una algoritmo de optimizaci��n que tiene en cuenta las tolerancias de los componentes y sensados distorsionados. Us ando este algoritmo, se comparan controles muy r��pidos del estado del arte y su capacidad para lograr una r��pida respuesta din��mica se posiciona seg��n el condensador de salida utilizado. Adem��s, se propone una t��cnica para mejorar la respuesta din��mica de los controladores. Todas las propuestas se han corroborado por extensas simulaciones y prototipos experimentales. Con todo, esta tesis sirve como una metodolog��a para ingenieros para dise��ar e implementar controles r��pidos y robustos de convertidores tipo Buck. ABSTRACT Modern digital electronics present a challenge to designers of power systems. The increasingly high-performance of microprocessors, FPGAs (Field Programmable Gate Array) and ASICs (Application-Specific Integrated Circuit) require power supplies to comply with very demanding static and dynamic requirements. Specifically, these power supplies are low-voltage/high-current DC-DC converters that need to be designed to exhibit low voltage ripple and low voltage deviation under high slew-rate load transients. Additionally, depending on the application, other requirements need to be met such as to provide to the load ���Dynamic Voltage Scaling��� (DVS), where the converter needs to change the output voltage as fast as possible without underdamping, or ���Adaptive Voltage Positioning��� (AVP) where the output voltage is slightly reduced the greater the output power. Of course, from the point of view of the industry, the figures of merit of these converters are the cost, efficiency and size/weight. Ideally, the industry needs a converter that is cheaper, more efficient, smaller and that can still meet the dynamic requirements of the application. In this context, several approaches to improve the figures of merit of these power supplies are followed in the industry and academia such as improving the topology of the converter, improving the semiconductor technology and improving the control. Indeed, the control is a fundamental part in these applications as a very fast control makes it easier for the topology to comply with the strict dynamic requirements and, consequently, gives the designer a larger margin of freedom to improve the cost, efficiency and/or size of the power supply. In this thesis, how to design and implement very fast controls for the Buck converter is investigated. This thesis proves that sensing the output voltage is all that is needed to achieve an almost time-optimal response and a unified design guideline for controls that only sense the output voltage is proposed. Then, in order to assure robustness in very fast controls, a very accurate modeling and stability analysis of DC-DC converters is proposed that takes into account sensing networks and critical parasitic elements. Also, using this modeling approach, an optimization algorithm that takes into account tolerances of components and distorted measurements is proposed. With the use of the algorithm, very fast analog controls of the state-of-the-art are compared and their capabilities to achieve a fast dynamic response are positioned de pending on the output capacitor. Additionally, a technique to improve the dynamic response of controllers is also proposed. All the proposals are corroborated by extensive simulations and experimental prototypes. Overall, this thesis serves as a methodology for engineers to design and implement fast and robust controls for Buck-type converters.

Survey of architectures and optimizations for wide bandwidth envelope amplifier

In the last years, RF power amplifiers are taking advantage of the switched dc-dc converters to use them in several architectures that may improve the efficiency of the amplifier, keeping a good linearity. The use of linearization techniques such as Envelope Elimination and Restoration(EER) and Envelope Tracking (ET) requires a very fast dc-dc power converter to provide variable voltage supply to the power amplifier but theoretically the efficiency can be much higher than using the classical amplifiers belonging to classes A, B or AB. The purpose of this paper is to analyze the state of the art of the power converters used as envelope amplifiers in this application. The power topologies will be explored and several important parameters such as efficiency, bandwidth will be discussed.

Comparison of V2IC control with voltage mode and current mode controls for high frequency (MHz) and very fast response applications

High switching frequencies (several MHz) allow the integration of low power DC/DC converters. Although, in theory, a high switching frequency would make possible to implement a conventional Voltage Mode control (VMC) or Peak Current Mode control (PCMC) with very high bandwidth, in practice, parasitic effects and robustness limits the applicability of these control techniques. This paper compares VMC and CMC techniques with the V2IC control. This control is based on two loops. The fast internal loop has information of the output capacitor current and the error voltage, providing fast dynamic response under load and voltage reference steps, while the slow external voltage loop provides accurate steady state regulation. This paper shows the fast dynamic response of the V2IC control under load and output voltage reference steps and its robustness operating with additional output capacitors added by the customer.

Minimum time control for multiphase buck converter: analysis and application

The combination of minimum time control and multiphase converter is a favorable option for dc-dc converters in applications where output voltage variation is required, such as RF amplifiers and dynamic voltage scaling in microprocessors, due to their advantage of fast dynamic response. In this paper, an improved minimum time control approach for multiphase buck converter that is based on charge balance technique, aiming at fast output voltage transition is presented. Compared with the traditional method, the proposed control takes into account the phase delay and current ripple in each phase. Therefore, by investigating the behavior of multiphase converter during voltage transition, it resolves the problem of current unbalance after the transient, which can lead to long settling time of the output voltage. The restriction of this control is that the output voltage that the converter can provide is related to the number of the phases, because only the duty cycles at which the multiphase converter has total ripple cancellation are used in this approach. The model of the proposed control is introduced, and the design constraints of the buck converters filter for this control are discussed. In order to prove the concept, a four-phase buck converter is implemented and the experimental results that validate the proposed control method are presented. The application of this control to RF envelope tracking is also presented in this paper.

Mission profile based optimization of a wearable power system

A Wearable Power System (WPS) is a portable power source utilized primarily to power the modern soldier���s electronic equipment. Such a system has to satisfy output power demands in the range of 20 W...200 W, specified as a 4-day mission profile and has a weight limit of 4 kg. To meet these demands, an optimization of a WPS, comprising an internal combustion (IC) engine, permanent magnetic three-phase electrical motor/generator, inverter, Li-batteries, DC-DC converters, and controller, is performed in this paper. The mechanical energy extracted from the fuel by IC engine is transferred to the generator that is used to recharge the battery and provide the power to the electrical output load. The main objectives are to select the engine, fuel and battery type, to match the weight of fuel and the number of battery cells, to find the optimal working point of engine and to minimize the system weight. To provide the second output voltage level of 14 VDC, a separate DC-DC converter is connected between the battery and the load, and optimized for the specified mission profile. A prototype of the WPS based on the optimization presented in the paper results in a total system weight of 3.9 kg and fulfils the mission profile.

Design of a Two-Phase buck converter with fourth-order output filter for envelope amplifiers of limited bandwidth

The use of techniques such as envelope tracking (ET) and envelope elimination and restoration (EER) can improve the efficiency of radio frequency power amplifiers (RFPA). In both cases, high-bandwidth DC/DC converters called envelope amplifiers (EA) are used to modulate the supply voltage of the RFPA. This paper addresses the analysis and design of a modified two-phase Buck converter optimized to operate as EA. The effects of multiphase operation on the tracking capabilities are analyzed. The use of a fourth-order output filter is proposed to increase the attenuation of the harmonics generated by the PWM operation, thus allowing a reduction of the ratio between the switching frequency and the converter bandwidth. The design of the output filter is addressed considering envelope tracking accuracy and distortion caused by the side bands arising from the nonlinear modulation process. Finally, the proposed analysis and design methods are supported by simulation results, as well as demonstrated by experiments obtained using two 100-W, 10-MHz, two-phase Buck EAs capable of accurately tracking a 1.5-MHz bandwidth OFDM signal.

Stability and Transient Performance Assessment in a COTS-Module-Based Distributed DC/DC System

This paper introduces a method to analyze and predict stability and transient performance of a distributed system where COTS (Commercial-off-the-shelf) modules share an input filter. The presented procedure is based on the measured data from the input and output terminals of the power modules. The required information for the analysis is obtained by performing frequency response measurements for each converter. This attained data is utilized to compute special transfer functions, which partly determine the source and load interactions within the converters. The system level dynamic description is constructed based on the measured and computed transfer functions introducing cross-coupling mechanisms within the system. System stability can be studied based on the well-known impedance- related minor-loop gain at an arbitrary interface within the system.

Methodology for Dynamic Stability and Robustness Analysis of Commercial-Power-Module-Based DC-Distributed Systems

El prop��sito de esta tesis es presentar una metodolog��a para realizar an��lisis de la din��mica en peque��a se��al y el comportamiento de sistemas de alimentaci��n distribuidos de corriente continua (CC), formados por m��dulos comerciales. Para ello se hace uso de un m��todo sencillo que indica los m��rgenes de estabilidad menos conservadores posibles mediante un solo n��mero. Este ��ndice es calculado en cada una de las interfaces que componen el sistema y puede usarse para obtener un ��ndice global que indica la estabilidad del sistema global. De esta manera se posibilita la comparaci��n de sistemas de alimentaci��n distribuidos en t��rminos de robustez. La interconexi��n de convertidores CC-CC entre ellos y con los filtros EMI necesarios puede originar interacciones no deseadas que dan lugar a la degradaci��n del comportamiento de los convertidores, haciendo el sistema m��s propenso a inestabilidades. Esta diferencia en el comportamiento se debe a interacciones entre las impedancias de los diversos elementos del sistema. En la mayor��a de los casos, los sistemas de alimentaci��n distribuida est��n formados por m��dulos comerciales cuya estructura interna es desconocida. Por ello los an��lisis presentados en esta tesis se basan en medidas de la respuesta en frecuencia del convertidor que pueden realizarse desde los terminales de entrada y salida del mismo. Utilizando las medidas de las impedancias de entrada y salida de los elementos del sistema, se puede construir una funci��n de sensibilidad que proporciona los m��rgenes de estabilidad de las diferentes interfaces. En esta tesis se utiliza el concepto del valor m��ximo de la funci��n de sensibilidad (MPC por sus siglas en ingl��s) para indicar los m��rgenes de estabilidad como un ��nico n��mero. Una vez que la estabilidad de todas las interfaces del sistema se han evaluado individualmente, los ��ndices obtenidos pueden combinarse para obtener un ��nico n��mero con el que comparar la estabilidad de diferentes sistemas. Igualmente se han analizado las posibles interacciones en la entrada y la salida de los convertidores CC-CC, obteni��ndose expresiones anal��ticas con las que describir en detalle los acoplamientos generados en el sistema. Los estudios anal��ticos realizados se han validado experimentalmente a lo largo de la tesis. El an��lisis presentado en esta tesis se culmina con la obtenci��n de un ��ndice que condensa los m��rgenes de estabilidad menos conservativos. Tambi��n se demuestra que la robustez del sistema est�� asegurada si las impedancias utilizadas en la funci��n de sensibilidad se obtienen justamente en la entrada o la salida del subsistema que est�� siendo analizado. Por otra parte, la tesis presenta un conjunto de par��metros internos asimilados a impedancias, junto con sus expresiones anal��ticas, que permiten una explicaci��n detallada de las interacciones en el sistema. Dichas expresiones anal��ticas pueden obtenerse bien mediante las funciones de transferencia anal��ticas si se conoce la estructura interna, o utilizando medidas en frecuencia o identificaci��n de las mismas a trav��s de la respuesta temporal del convertidor. De acuerdo a las metodolog��as presentadas en esta tesis se puede predecir la estabilidad y el comportamiento de sistemas compuestos b��sicamente por convertidores CC-CC y filtros, cuya estructura interna es desconocida. La predicci��n se basa en un ��ndice que condensa la informaci��n de los m��rgenes de estabilidad y que permite la obtenci��n de un indicador de la estabilidad global de todo el sistema, permitiendo la comparaci��n de la estabilidad de diferentes arquitecturas de sistemas de alimentaci��n distribuidos. ABSTRACT The purpose of this thesis is to present dynamic small-signal stability and performance analysis methodology for dc-distributed systems consisting of commercial power modules. Furthermore, the objective is to introduce simple method to state the least conservative margins for robust stability as a single number. In addition, an index characterizing the overall system stability is obtained, based on which different dc-distributed systems can be compared in terms of robustness. The interconnected systems are prone to impedance-based interactions which might lead to transient-performance degradation or even instability. These systems typically are constructed using commercial converters with unknown internal structure. Therefore, the analysis presented throughout this thesis is based on frequency responses measurable from the input and output terminals. The stability margins are stated utilizing a concept of maximum peak criteria, derived from the behavior of impedance-based sensitivity function that provides a single number to state robust stability. Using this concept, the stability information at every system interface is combined to a meaningful number to state the average robustness of the system. In addition, theoretical formulas are extracted to assess source and load side interactions in order to describe detailed couplings within the system. The presented theoretical analysis methodologies are experimentally validated throughout the thesis. In this thesis, according to the presented analysis, the least conservative stability margins are provided as a single number guaranteeing robustness. It is also shown that within the interconnected system the robust stability is ensured only if the impedance-based minor-loop gain is determined at the very input or output of each subsystem. Moreover, a complete set of impedance-type internal parameters as well as the formulas according to which the interaction sensitivity can be fully explained and analyzed, is provided. The given formulation can be utilized equally either based on measured frequency responses, time-domain identified internal parameters or extracted analytic transfer functions. Based on the analysis methodologies presented in this thesis, the stability and performance of interconnected systems consisting of converters with unknown internal structure, can be predicted. Moreover, the provided concept to assess the least conservative stability margins enables to obtain an index to state the overall robust stability of distributed power architecture and thus to compare different systems in terms of stability.

Pinus uncinata Ramond ex DC.: Conservation and proposal of management at its southwestern limit of distribution (Castillo de Vinuesa, Soria, Spain)

Pinus uncinata forms forests in the centre and southwest of the Alps and in the subalpine Pyrenees (at around 1700 ��� 2600 m) (Costa Tenorio et al., 1997). The species reaches the southwestern limit of its distribution at the top of Mount Castillo de Vinuesa (Soria, Spain). The small population on this mountain occupies just 66 ha, but is very important from a geobotanical viewpoint since it is just one of two populations (the other being in the Sierra de G��dar range in Teruel, Spain) isolated from the main area where the species is found in the Iberian Peninsula (The Pyrenees)

Series combination of a switched dc-dc converter and a linear regulator for high frequency RF envelope amplifier

Classical linear amplifiers such as A, AB and B offer very good linearity suitable for RF power amplifiers. However, its inherent low efficiency limits its use especially in base-stations that manage tens or hundreds of Watts. The use of linearization techniques such as Envelope Elimination and Restoration (EER) allow an increase of efficiency keeping good linearity. This technique requires a very fast dc-dc power converter to provide variable voltage supply to the power amplifier. In this paper, several alternatives are analyzed to implement the envelope amplifier based on a cascade association of a switched dc-dc converter and a linear regulator. A simplified version of this approach is also suitable to operate with Envelope Tracking technique.