Role of the wetting layer in the enhanced responsivity of InAs/GaAsSb quantum dot infrared photodetectors

InAs/GaAs1−xSbx Quantum Dot (QD) infrared photodetectors are analyzed by photocurrent spectroscopy. We observe that the integrated responsivity of the devices is improved with the increasing Sb mole fraction in the capping layer, up to 4.2 times for x = 17%. Since the QD layers are not vertically aligned, the vertical transport of the carriers photogenerated within the QDs takes place mainly through the bulk material and the wetting layer of the additional QD regions. The lower thickness of the wetting layer for high Sb contents results in a reduced capture probability of the photocarriers, thus increasing the photoconductive gain and hence, the responsivity of the device. The growth of not vertically aligned consecutive QD layers with a thinner wetting layer opens a possibility to improve the performance of quantum dot infrared photodetectors.

Near infrared high efficiency InAs/GaAsSb QDLEDs: band alignment and carrier recombination mechanisms

The development of high efficiency laser diodes (LD) and light emitting diodes (LED) covering the 1.0 to 1.55 μm region of the spectra using GaAs heteroepitaxy has been long pursued. Due to the lack of materials that can be grown lattice-macthed to GaAs with bandgaps in the 1.0 to 1.55 μm region, quantum wells (QW) or quantum dots (QD) need be used. The most successful approach with QWs has been to use InGaAs, but one needs to add another element, such as N, to be able to reach 1.3/1.5μm. Even though LDs have been successfully demonstrated with the QW approach, using N leads to problems with compositional homogeneity across the wafer, and limited efficiency due to strong non-radiative recombination. The alternative approach of using InAs QDs is an attractive option, but once again, to reach the longest wavelengths one needs very large QDs and control over the size distribution and band alignment. In this work we demonstrate InAs/GaAsSb QDLEDs with high efficiencies, emitting from 1.1 to 1.52 μm, and we analyze the band alignment and carrier loss mechanisms that result from the presence of Sb in the capping layer.

Gas sensor based on room temperature optical properties of Surface QDs

Self-organized InGaAs QDs are intensively studied for optoelectronic applications. Several approaches are in study to reach the emission wavelengths needed for these applications. The use of antimony (Sb) in either the capping layer or into the dots is one example. However, these studies are normally focused on buried QD (BQD) where there are still different controversial theories concerning the role of Sb. Ones suggest that Sb incorporates into the dot [1], while others support the hypothesis that the Sb occupies positions surrounding the dot [2] thus helping to keep their shape during the capping growth.

Size, strain, and band offset engineering in GaAs(Sb)(N)-capped InAs quantum dots for 1.3 - 1.55 µm LEDs and LDs

The optical and structural properties of InAs/GaAs quantum dots (QD) are strongly modified through the use of a thin (~ 5 nm) GaAsSb(N) capping layer. In the case of GaAsSb-capped QDs, cross-sectional scanning tunnelling microscopy measurements show that the QD height can be controllably tuned through the Sb content up to ~ 14 % Sb. The increased QD height (together with the reduced strain) gives rise to a strong red shift and a large enhancement of the photoluminescence (PL) characteristics. This is due to improved carrier confinement and reduced sensitivity of the excitonic bandgap to QD size fluctuations within the ensemble. Moreover, the PL degradation with temperature is strongly reduced in the presence of Sb. Despite this, emission in the 1.5 !lm region with these structures is only achieved for high Sb contents and a type-II band alignment that degrades the PL. Adding small amounts of N to the GaAsSb capping layer allows to progressively reduce the QD-barrier conduction band offset. This different strategy to red shift the PL allows reaching 1.5 !lm with moderate Sb contents, keeping therefore a type-I alignment. Nevertheless, the PL emission is progressively degraded when the N content in the capping layer is increased

Synthesis and characterization of GaAsSb-capped InAs-based QDIPs

Quantum dot infrared photodetectors (QDIPs) are very attractive for infrared imaging applications due to its promising features such as high temperature operation, normal incidence response and low dark current [1]. However, the key issue is to obtain a high quality active region which requires a structural optimization of the nanostructures. With using GaAsSb capping layer, the optical properties, such as the PL intensity and its full width at half maximum (FWHM), of InAs QDs have been improved in the range between 1.15 and 1.5 m, because of the reduction of the compressive strain in QDs and the increment of QD height [2]. In this work, we have demonstrated strong and narrow intraband photoresponse spectra from GaAsSb-capped InAs-based QDIPs

Mid-infrared photodetectors based on GaAsSb-capped InAs quantum dots

Quantum dot infrared photodetectors (QDIPs) are very attractive for many applications such as infrared imaging, remote sensing and gas sensing, thanks to its promising features such as high temperature operation, normal incidence response and low dark current [1]. However, the key issue is to obtain a high-quality active region which requires an optimization of the nanostructure. By using GaAsSb capping layer, InAs QDs have improved their optical emission in the range between 1.15 and 1.3 m (at Sb composition of 14 %), due to a reduction of a compressive strain in QD and an increment of a QD height [2]. In this work, we have demonstrated strong and narrow intraband photoresponses at ~ 5 m from GaAsSb-capped InAs/GaAs QDIPs under normal light-incidence.

High efficient luminescence in type-II GaAsSb-capped InAs quantum dots upon annealing

The photoluminescence efficiency of GaAsSb-capped InAs/GaAs type II quantum dots (QDs) can be greatly enhanced by rapid thermal annealing while preserving long radiative lifetimes which are ∼20 times larger than in standard GaAs-capped InAs/GaAs QDs. Despite the reduced electron-hole wavefunction overlap, the type-II samples are more efficient than the type-I counterparts in terms of luminescence, showing a great potential for device applications. Strain-driven In-Ga intermixing during annealing is found to modify the QD shape and composition, while As-Sb exchange is inhibited, allowing to keep the type-II structure. Sb is only redistributed within the capping layer giving rise to a more homogeneous composition.

Analysis of the modified optical properties and band structure of GaAs12xSbx-capped InAs/GaAs quantum dots

The origin of the modified optical properties of InAs/GaAs quantum dots (QD) capped with a thin GaAs1−xSbx layer is analyzed in terms of the band structure. To do so, the size, shape, and composition of the QDs and capping layer are determined through cross-sectional scanning tunnelling microscopy and used as input parameters in an 8 × 8 k·p model. As the Sb content is increased, there are two competing effects determining carrier confinement and the oscillator strength: the increased QD height and reduced strain on one side and the reduced QD-capping layer valence band offset on the other. Nevertheless, the observed evolution of the photoluminescence (PL) intensity with Sb cannot be explained in terms of the oscillator strength between ground states, which decreases dramatically for Sb > 16%, where the band alignment becomes type II with the hole wavefunction localized outside the QD in the capping layer. Contrary to this behaviour, the PL intensity in the type II QDs is similar (at 15 K) or even larger (at room temperature) than in the type I Sb-free reference QDs. This indicates that the PL efficiency is dominated by carrier dynamics, which is altered by the presence of the GaAsSb capping layer. In particular, the presence of Sb leads to an enhanced PL thermal stability. From the comparison between the activation energies for thermal quenching of the PL and the modelled band structure, the main carrier escape mechanisms are suggested. In standard GaAs-capped QDs, escape of both electrons and holes to the GaAs barrier is the main PL quenching mechanism. For small-moderate Sb (<16%) for which the type I band alignment is kept, electrons escape to the GaAs barrier and holes escape to the GaAsSb capping layer, where redistribution and retraping processes can take place. For Sb contents above 16% (type-II region), holes remain in the GaAsSb layer and the escape of electrons from the QD to the GaAs barrier is most likely the dominant PL quenching mechanism. This means that electrons and holes behave dynamically as uncorrelated pairs in both the type-I and type-II structures.

InAs/AlGaAs quantum dot intermediate band solar cells with enlarged sub-bandgaps

In the last decade several prototypes of intermediate band solar cells (IBSCs) have been manufactured. So far, most of these prototypes have been based on InAs/GaAs quantum dots (QDs) in order to implement the IB material. The key operation principles of the IB theory are two photon sub-bandgap (SBG) photocurrent, and output voltage preservation, and both have been experimentally demonstrated at low temperature. At room temperature (RT), however, thermal escape/relaxation between the conduction band (CB) and the IB prevents voltage preservation. To improve this situation, we have produced and characterized the first reported InAs/AlGaAs QD-based IBSCs. For an Al content of 25% in the host material, we have measured an activation energy of 361 meV for the thermal carrier escape. This energy is about 250 meV higher than the energies found in the literature for InAs/GaAs QD, and almost 140 meV higher than the activation energy obtained in our previous InAs/GaAs QD-IBSC prototypes including a specifically designed QD capping layer. This high value is responsible for the suppression of the SBG quantum efficiency under monochromatic illumination at around 220 K. We suggest that, if the energy split between the CB and the IB is large enough, activation energies as high as to suppress thermal carrier escape at room temperature (RT) can be achieved. In this respect, the InAs/AlGaAs system offers new possibilities to overcome some of the problems encountered in InAs/GaAs and opens the path for QD-IBSC devices capable of achieving high efficiency at RT.

Thermal, stress, and traps effects in AlGaN/GaN HEMTs

GaN y AlN son materiales semiconductores piezoeléctricos del grupo III-V. La heterounión AlGaN/GaN presenta una elevada carga de polarización tanto piezoeléctrica como espontánea en la intercara, lo que genera en su cercanía un 2DEG de grandes concentración y movilidad. Este 2DEG produce una muy alta potencia de salida, que a su vez genera una elevada temperatura de red. Las tensiones de puerta y drenador provocan un stress piezoeléctrico inverso, que puede afectar a la carga de polarización piezoeléctrica y así influir la densidad 2DEG y las características de salida. Por tanto, la física del dispositivo es relevante para todos sus aspectos eléctricos, térmicos y mecánicos. En esta tesis se utiliza el software comercial COMSOL, basado en el método de elementos finitos (FEM), para simular el comportamiento integral electro-térmico, electro-mecánico y electro-térmico-mecánico de los HEMTs de GaN. Las partes de acoplamiento incluyen el modelo de deriva y difusión para el transporte electrónico, la conducción térmica y el efecto piezoeléctrico. Mediante simulaciones y algunas caracterizaciones experimentales de los dispositivos, hemos analizado los efectos térmicos, de deformación y de trampas. Se ha estudiado el impacto de la geometría del dispositivo en su auto-calentamiento mediante simulaciones electro-térmicas y algunas caracterizaciones eléctricas. Entre los resultados más sobresalientes, encontramos que para la misma potencia de salida la distancia entre los contactos de puerta y drenador influye en generación de calor en el canal, y así en su temperatura. El diamante posee une elevada conductividad térmica. Integrando el diamante en el dispositivo se puede dispersar el calor producido y así reducir el auto-calentamiento, al respecto de lo cual se han realizado diversas simulaciones electro-térmicas. Si la integración del diamante es en la parte superior del transistor, los factores determinantes para la capacidad disipadora son el espesor de la capa de diamante, su conductividad térmica y su distancia a la fuente de calor. Este procedimiento de disipación superior también puede reducir el impacto de la barrera térmica de intercara entre la capa adaptadora (buffer) y el substrato. La muy reducida conductividad eléctrica del diamante permite que pueda contactar directamente el metal de puerta (muy cercano a la fuente de calor), lo que resulta muy conveniente para reducir el auto-calentamiento del dispositivo con polarización pulsada. Por otra parte se simuló el dispositivo con diamante depositado en surcos atacados sobre el sustrato como caminos de disipación de calor (disipador posterior). Aquí aparece una competencia de factores que influyen en la capacidad de disipación, a saber, el surco atacado contribuye a aumentar la temperatura del dispositivo debido al pequeño tamaño del disipador, mientras que el diamante disminuiría esa temperatura gracias a su elevada conductividad térmica. Por tanto, se precisan capas de diamante relativamente gruesas para reducer ele efecto de auto-calentamiento. Se comparó la simulación de la deformación local en el borde de la puerta del lado cercano al drenador con estructuras de puerta estándar y con field plate, que podrían ser muy relevantes respecto a fallos mecánicos del dispositivo. Otras simulaciones se enfocaron al efecto de la deformación intrínseca de la capa de diamante en el comportamiento eléctrico del dispositivo. Se han comparado los resultados de las simulaciones de la deformación y las características eléctricas de salida con datos experimentales obtenidos por espectroscopía micro-Raman y medidas eléctricas, respectivamente. Los resultados muestran el stress intrínseco en la capa producido por la distribución no uniforme del 2DEG en el canal y la región de acceso. Además de aumentar la potencia de salida del dispositivo, la deformación intrínseca en la capa de diamante podría mejorar la fiabilidad del dispositivo modulando la deformación local en el borde de la puerta del lado del drenador. Finalmente, también se han simulado en este trabajo los efectos de trampas localizados en la superficie, el buffer y la barrera. Las medidas pulsadas muestran que tanto las puertas largas como las grandes separaciones entre los contactos de puerta y drenador aumentan el cociente entre la corriente pulsada frente a la corriente continua (lag ratio), es decir, disminuir el colapse de corriente (current collapse). Este efecto ha sido explicado mediante las simulaciones de los efectos de trampa de superficie. Por su parte, las referidas a trampas en el buffer se enfocaron en los efectos de atrapamiento dinámico, y su impacto en el auto-calentamiento del dispositivo. Se presenta también un modelo que describe el atrapamiento y liberación de trampas en la barrera: mientras que el atrapamiento se debe a un túnel directo del electrón desde el metal de puerta, el desatrapamiento consiste en la emisión del electrón en la banda de conducción mediante túnel asistido por fonones. El modelo también simula la corriente de puerta, debida a la emisión electrónica dependiente de la temperatura y el campo eléctrico. Además, también se ilustra la corriente de drenador dependiente de la temperatura y el campo eléctrico. ABSTRACT GaN and AlN are group III-V piezoelectric semiconductor materials. The AlGaN/GaN heterojunction presents large piezoelectric and spontaneous polarization charge at the interface, leading to high 2DEG density close to the interface. A high power output would be obtained due to the high 2DEG density and mobility, which leads to elevated lattice temperature. The gate and drain biases induce converse piezoelectric stress that can influence the piezoelectric polarization charge and further influence the 2DEG density and output characteristics. Therefore, the device physics is relevant to all the electrical, thermal, and mechanical aspects. In this dissertation, by using the commercial finite-element-method (FEM) software COMSOL, we achieved the GaN HEMTs simulation with electro-thermal, electro-mechanical, and electro-thermo-mechanical full coupling. The coupling parts include the drift-diffusion model for the electron transport, the thermal conduction, and the piezoelectric effect. By simulations and some experimental characterizations, we have studied the device thermal, stress, and traps effects described in the following. The device geometry impact on the self-heating was studied by electro-thermal simulations and electrical characterizations. Among the obtained interesting results, we found that, for same power output, the distance between the gate and drain contact can influence distribution of the heat generation in the channel and thus influence the channel temperature. Diamond possesses high thermal conductivity. Integrated diamond with the device can spread the generated heat and thus potentially reduce the device self-heating effect. Electro-thermal simulations on this topic were performed. For the diamond integration on top of the device (top-side heat spreading), the determinant factors for the heat spreading ability are the diamond thickness, its thermal conductivity, and its distance to the heat source. The top-side heat spreading can also reduce the impact of thermal boundary resistance between the buffer and the substrate on the device thermal behavior. The very low electrical conductivity of diamond allows that it can directly contact the gate metal (which is very close to the heat source), being quite convenient to reduce the self-heating for the device under pulsed bias. Also, the diamond coated in vias etched in the substrate as heat spreading path (back-side heat spreading) was simulated. A competing mechanism influences the heat spreading ability, i.e., the etched vias would increase the device temperature due to the reduced heat sink while the coated diamond would decrease the device temperature due to its higher thermal conductivity. Therefore, relative thick coated diamond is needed in order to reduce the self-heating effect. The simulated local stress at the gate edge of the drain side for the device with standard and field plate gate structure were compared, which would be relevant to the device mechanical failure. Other stress simulations focused on the intrinsic stress in the diamond capping layer impact on the device electrical behaviors. The simulated stress and electrical output characteristics were compared to experimental data obtained by micro-Raman spectroscopy and electrical characterization, respectively. Results showed that the intrinsic stress in the capping layer caused the non-uniform distribution of 2DEG in the channel and the access region. Besides the enhancement of the device power output, intrinsic stress in the capping layer can potentially improve the device reliability by modulating the local stress at the gate edge of the drain side. Finally, the surface, buffer, and barrier traps effects were simulated in this work. Pulsed measurements showed that long gates and distances between gate and drain contact can increase the gate lag ratio (decrease the current collapse). This was explained by simulations on the surface traps effect. The simulations on buffer traps effects focused on illustrating the dynamic trapping/detrapping in the buffer and the self-heating impact on the device transient drain current. A model was presented to describe the trapping and detrapping in the barrier. The trapping was the electron direct tunneling from the gate metal while the detrapping was the electron emission into the conduction band described by phonon-assisted tunneling. The reverse gate current was simulated based on this model, whose mechanism can be attributed to the temperature and electric field dependent electron emission in the barrier. Furthermore, the mechanism of the device bias via the self-heating and electric field impact on the electron emission and the transient drain current were also illustrated.

Stacked GaAs(Sb)(N)-capped InAs/GaAs quantum dots for enhanced solar cell efficiency

Different approaches have arisen aiming to exceed the Shockley-Queisser efficiency limit of solar cells. Particularly, stacking QD layers allows exploiting their unique properties, not only for intermediate-band solar cells or multiple exciton generation, but also for tandem cells in which the tunability of QD properties through the capping layer (CL) could be very useful.

Stacked GaAsSbN-capped InAs/GaAs quantum dots for enhanced solar cell efficiency

Different approaches have recently arisen aiming to exceed the Shockley-Queisser efficiency limit. Particularly, the use of self-organized quantum dots (QD) has been recently proposed in order to introduce new states within the barrier material, which enhances the subband gap absorption yielding a photocurrent increase. Stacking QD layers allows exploiting their unique properties for intermediate-band solar cells (SC) or tandem cells.In all these cases, tuning the QD properties by modifying the capping layer (CL) can be very useful.

Investigation of AlInN barrier ISFET structures with GaN capping for pH detection

The pH response of GaN/AlInN/AlN/GaN ion-sensitive field effect transistor (ISFET) on Si substrates has been characterized. We analyzed the variation of the surface potential (ΔVsp/ΔpH) and current (ΔIds/ΔpH) with solution pH in devices with the same indium content (17%, in-plane lattice-matched to GaN) and different AlInN thickness (6 nm and 10 nm), and compared with the literature. The shrinkage of the barrier, that has the effect to increase the transconductance of the device, makes the 2-dimensional electron density (2DEG) at the interface very sensitive to changes in the surface. Although the surface potential sensitivity to pH is similar in the two devices, the current change with pH (ΔIds/ΔpH), when biasing the ISFET by a Ag/AgCl reference electrode, is almost 50% higher in the device with 6 nm AlInN barrier, compared to the device with 10 nm barrier. When measuring the current response (ΔIds/ΔpH) without reference electrode, the device with thinner AlInN layer has a larger response than the thicker one, of a factor of 140%, and that current response without reference electrode is only 22% lower than its maximum response obtained using reference electrode.