Optimum Design of an Envelope Tracking Buck Converter for RF PA using GaN HEMTs

In this paper, filter design methodology and application of GaN HEMTs for high efficiency Envelope Amplifier in RF transmitters are proposed. The main objectives of the filter design are generation of the envelope reference with the minimum possible distortion and high efficiency of the amplifier obtained by the optimum trade-off between conduction and switching losses. This optimum point was determined using power losses model for synchronous buck with sinusoidal output voltage and experimental results showed good correspondence with the model and verified the proposed methodology. On the other hand, comparing to Si MOSFETs, GaN HEMTs can provide higher efficiency of the envelope amplifier, due to superior conductivity and switching characteristics. Experimental results verified benefits of GaN devices comparing to the appliance of Si switching devices with very good Figure Of Merit, for this particular application

An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation

Early propagation effect (EPE) is a critical problem in conventional dual-rail logic implementations against Side Channel Attacks (SCAs). Among previous EPE-resistant architectures, PA-DPL logic offers EPE-free capability at relatively low cost. However, its separate dual core structure is a weakness when facing concentrated EM attacks where a tiny EM probe can be precisely positioned closer to one of the two cores. In this paper, we present an PA-DPL dual-core interleaved structure to strengthen resistance against sophisticated EM attacks on Xilinx FPGA implementations. The main merit of the proposed structure is that every two routing in each signal pair are kept identical even the dual cores are interleaved together. By minimizing the distance between the complementary routings and instances of both cores, even the concentrated EM measurement cannot easily distinguish the minor EM field unbalance. In PA- DPL, EPE is avoided by compressing the evaluation phase to a small portion of the clock period, therefore, the speed is inevitably limited. Regarding this, we made an improvement to extend the duty cycle of evaluation phase to more than 40 percent, yielding a larger maximum working frequency. The detailed design flow is also presented. We validate the security improvement against EM attack by implementing a simplified AES co-processor in Virtex-5 FPGA.