About the origin of low wafer performance and crystal defect generation on seed-cast growth of industrial mono-like silicon ingots

The era of the seed-cast grown monocrystalline-based silicon ingots is coming. Mono-like, pseudomono or quasimono wafers are product labels that can be nowadays found in the market, as a critical innovation for the photovoltaic industry. They integrate some of the most favorable features of the conventional silicon substrates for solar cells, so far, such as the high solar cell efficiency offered by the monocrystalline Czochralski-Si (Cz-Si) wafers and the lower cost, high productivity and full square-shape that characterize the well-known multicrystalline casting growth method. Nevertheless, this innovative crystal growth approach still faces a number of mass scale problems that need to be resolved, in order to gain a deep, 100% reliable and worldwide market: (i) extended defects formation during the growth process; (ii) optimization of the seed recycling; and (iii) parts of the ingots giving low solar cells performance, which directly affect the production costs and yield of this approach. Therefore, this paper presents a series of casting crystal growth experiments and characterization studies from ingots, wafers and cells manufactured in an industrial approach, showing the main sources of crystal defect formation, impurity enrichment and potential consequences at solar cell level. The previously mentioned technological drawbacks are directly addressed, proposing industrial actions to pave the way of this new wafer technology to high efficiency solar cells.

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

Silicon wafers comprise approximately 40% of crystalline silicon module cost, and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled to effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. To accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.

Silicon Photomultipliers (SiPM) as novel photodetectors for PET

Next generation PET scanners should fulfill very high requirements in terms of spatial, energy and timing resolution. Modern scanner performances are inherently limited by the use of standard photomultiplier tubes. The use of Silicon Photomultipliers (SiPMs) is proposed for the construction of a 4D-PET module of 4.8×4.8 cm2 aimed to replace the standard PMT based PET block detector. The module will be based on a LYSO continuous crystal read on two faces by Silicon Photomultipliers. A high granularity detection surface made by SiPM matrices of 1.5 mm pitch will be used for the x–y photon hit position determination with submillimetric accuracy, while a low granularity surface constituted by 16 mm2 SiPM pixels will provide the fast timing information (t) that will be used to implement the Time of Flight technique (TOF). The spatial information collected by the two detector layers will be combined in order to measure the Depth of Interaction (DOI) of each event (z). The use of large area multi-pixel Silicon Photomultiplier (SiPM) detectors requires the development of a multichannel Data Acquisition system (DAQ) as well as of a dedicated front-end in order not to degrade the intrinsic detector capabilities and to manage many channels. The paper describes the progress made on the development of the proof of principle module under construction at the University of Pisa.

Adaptive liquid-crystal phase-only passive devices

This PhD work is focused on liquid crystal based tunable phase devices with special emphasis on their design and manufacturing. In the course of the work a number of new manufacturing technologies have been implemented in the UPM clean room facilities, leading to an important improvement in the range of devices being manufactured in the laboratory. Furthermore, a number of novel phase devices have been developed, all of them including novel electrodes, and/or alignment layers. The most important manufacturing progress has been the introduction of reactive ion etching as a tool for achieving high resolution photolithography on indium-tin-oxide (ITO) coated glass and quartz substrates. Another important manufacturing result is the successful elaboration of a binding protocol of anisotropic conduction adhesives. These have been employed in high density interconnections between ITO-glass and flexible printed circuits. Regarding material characterization, the comparative study of nonstoichiometric silicon oxide (SiOx) and silica (SiO2) inorganic alignment layers, as well as the relationship between surface layer deposition, layer morphology and liquid crystal electrooptical response must be highlighted, together with the characterization of the degradation of liquid crystal devices in simulated space mission environment. A wide variety of phase devices have been developed, with special emphasis on beam steerers. One of these was developed within the framework of an ESA project, and consisted of a high density reconfigurable 1D blaze grating, with a spatial separation of the controlling microelectronics and the active, radiation exposed, area. The developed devices confirmed the assumption that liquid crystal devices with such a separation of components, are radiation hard, and can be designed to be both vibration and temperature sturdy. In parallel to the above, an evenly variable analog beam steering device was designed, manufactured and characterized, providing a narrow cone diffraction free beam steering. This steering device is characterized by a very limited number of electrodes necessary for the redirection of a light beam. As few as 4 different voltage levels were needed in order to redirect a light beam. Finally at the Wojskowa Akademia Techniczna (Military University of Technology) in Warsaw, Poland, a wedged analog tunable beam steering device was designed, manufactured and characterized. This beam steerer, like the former one, was designed to resist the harsh conditions both in space and in the context of the shuttle launch. Apart from the beam steering devices, reconfigurable vortices and modal lens devices have been manufactured and characterized. In summary, during this work a large number of liquid crystal devices and liquid crystal device manufacturing technologies have been developed. Besides their relevance in scientific publications and technical achievements, most of these new devices have demonstrated their usefulness in the actual work of the research group where this PhD has been completed. El presente trabajo de Tesis se ha centrado en el diseño, fabricación y caracterización de nuevos dispositivos de fase basados en cristal líquido. Actualmente se están desarrollando dispositivos basados en cristal líquido para aplicaciones diferentes a su uso habitual como displays. Poseen la ventaja de que los dispositivos pueden ser controlados por bajas tensiones y no necesitan elementos mecánicos para su funcionamiento. La fabricación de todos los dispositivos del presente trabajo se ha realizado en la cámara limpia del grupo. La cámara limpia ha sido diseñada por el grupo de investigación, es de dimensiones reducidas pero muy versátil. Está dividida en distintas áreas de trabajo dependiendo del tipo de proceso que se lleva a cabo. La cámara limpia está completamente cubierta de un material libre de polvo. Todas las entradas de suministro de gas y agua están selladas. El aire filtrado es constantemente bombeado dentro de la zona limpia, a fin de crear una sobrepresión evitando así la entrada de aire sin filtrar. Las personas que trabajan en esta zona siempre deben de estar protegidas con un traje especial. Se utilizan trajes especiales que constan de: mono, máscara, guantes de látex, gorro, patucos y gafas de protección UV, cuando sea necesario. Para introducir material dentro de la cámara limpia se debe limpiar con alcohol y paños especiales y posteriormente secarlos con nitrógeno a presión. La fabricación debe seguir estrictamente unos pasos determinados, que pueden cambiar dependiendo de los requerimientos de cada dispositivo. Por ello, la fabricación de dispositivos requiere la formulación de varios protocolos de fabricación. Estos protocolos deben ser estrictamente respetados a fin de obtener repetitividad en los experimentos, lo que lleva siempre asociado un proceso de fabricación fiable. Una célula de cristal líquido está compuesta (de forma general) por dos vidrios ensamblados (sándwich) y colocados a una distancia determinada. Los vidrios se han sometido a una serie de procesos para acondicionar las superficies internas. La célula se llena con cristal líquido. De forma resumida, el proceso de fabricación general es el siguiente: inicialmente, se cortan los vidrios (cuya cara interna es conductora) y se limpian. Después se imprimen las pistas sobre el vidrio formando los píxeles. Estas pistas conductoras provienen del vidrio con la capa conductora de ITO (óxido de indio y estaño). Esto se hace a través de un proceso de fotolitografía con una resina fotosensible, y un desarrollo y ataque posterior del ITO sin protección. Más tarde, las caras internas de los vidrios se acondicionan depositando una capa, que puede ser orgánica o inorgánica (un polímero o un óxido). Esta etapa es crucial para el funcionamiento del dispositivo: induce la orientación de las moléculas de cristal líquido. Una vez que las superficies están acondicionadas, se depositan espaciadores en las mismas: son pequeñas esferas o cilindros de tamaño calibrado (pocos micrómetros) para garantizar un espesor homogéneo del dispositivo. Después en uno de los sustratos se deposita un adhesivo (gasket). A continuación, los sustratos se ensamblan teniendo en cuenta que el gasket debe dejar una boca libre para que el cristal líquido se introduzca posteriormente dentro de la célula. El llenado de la célula se realiza en una cámara de vacío y después la boca se sella. Por último, la conexión de los cables a la célula y el montaje de los polarizadores se realizan fuera de la sala limpia (Figura 1). Dependiendo de la aplicación, el cristal líquido empleado y los demás componentes de la célula tendrán unas características particulares. Para el diseño de los dispositivos de este trabajo se ha realizado un estudio de superficies inorgánicas de alineamiento del cristal líquido, que será de gran importancia para la preparación de los dispositivos de fase, dependiendo de las condiciones ambientales en las que vayan a trabajar. Los materiales inorgánicos que se han estudiado han sido en este caso SiOx y SiO2. El estudio ha comprendido tanto los factores de preparación influyentes en el alineamiento, el comportamiento del cristal líquido al variar estos factores y un estudio de la morfología de las superficies obtenidas.

Polarization properties of polymer-based photonic crystal fibers

Selectively filled photonic crystal fibers with polydimethylsiloxane (PDMS), a silicon-type material, have been studied. Is has been demonstrated that polarization properties of these hybrid devices and the properties of the guided light in relation with the temperature changes, finding that the state of polarization (SOP) change with the increasing temperature but remains constant for a wide spectrum of wavelengths for a determinate temperature.

MOVPE growth of III-V semiconductors on silicon for third generation solar cells

Esta Tesis trata sobre el desarrollo y crecimiento -mediante tecnología MOVPE (del inglés: MetalOrganic Vapor Phase Epitaxy)- de células solares híbridas de semiconductores III-V sobre substratos de silicio. Esta integración pretende ofrecer una alternativa a las células actuales de III-V, que, si bien ostentan el récord de eficiencia en dispositivos fotovoltaicos, su coste es, a día de hoy, demasiado elevado para ser económicamente competitivo frente a las células convencionales de silicio. De este modo, este proyecto trata de conjugar el potencial de alta eficiencia ya demostrado por los semiconductores III-V en arquitecturas de células fotovoltaicas multiunión con el bajo coste, la disponibilidad y la abundancia del silicio. La integración de semiconductores III-V sobre substratos de silicio puede afrontarse a través de diferentes aproximaciones. En esta Tesis se ha optado por el desarrollo de células solares metamórficas de doble unión de GaAsP/Si. Mediante esta técnica, la transición entre los parámetros de red de ambos materiales se consigue por medio de la formación de defectos cristalográficos (mayoritariamente dislocaciones). La idea es confinar estos defectos durante el crecimiento de sucesivas capas graduales en composición para que la superficie final tenga, por un lado, una buena calidad estructural, y por otro, un parámetro de red adecuado. Numerosos grupos de investigación han dirigido sus esfuerzos en los últimos años en desarrollar una estructura similar a la que aquí proponemos. La mayoría de éstos se han centrado en entender los retos asociados al crecimiento de materiales III-V, con el fin de conseguir un material de alta calidad cristalográfica. Sin embargo, prácticamente ninguno de estos grupos ha prestado especial atención al desarrollo y optimización de la célula inferior de silicio, cuyo papel va a ser de gran relevancia en el funcionamiento de la célula completa. De esta forma, y con el fin de completar el trabajo hecho hasta el momento en el desarrollo de células de III-V sobre silicio, la presente Tesis se centra, fundamentalmente, en el diseño y optimización de la célula inferior de silicio, para extraer su máximo potencial. Este trabajo se ha estructurado en seis capítulos, ordenados de acuerdo al desarrollo natural de la célula inferior. Tras un capítulo de introducción al crecimiento de semiconductores III-V sobre Si, en el que se describen las diferentes alternativas para su integración; nos ocupamos de la parte experimental, comenzando con una extensa descripción y caracterización de los substratos de silicio. De este modo, en el Capítulo 2 se analizan con exhaustividad los diferentes tratamientos (tanto químicos como térmicos) que deben seguir éstos para garantizar una superficie óptima sobre la que crecer epitaxialmente el resto de la estructura. Ya centrados en el diseño de la célula inferior, el Capítulo 3 aborda la formación de la unión p-n. En primer lugar se analiza qué configuración de emisor (en términos de dopaje y espesor) es la más adecuada para sacar el máximo rendimiento de la célula inferior. En este primer estudio se compara entre las diferentes alternativas existentes para la creación del emisor, evaluando las ventajas e inconvenientes que cada aproximación ofrece frente al resto. Tras ello, se presenta un modelo teórico capaz de simular el proceso de difusión de fosforo en silicio en un entorno MOVPE por medio del software Silvaco. Mediante este modelo teórico podemos determinar qué condiciones experimentales son necesarias para conseguir un emisor con el diseño seleccionado. Finalmente, estos modelos serán validados y constatados experimentalmente mediante la caracterización por técnicas analíticas (i.e. ECV o SIMS) de uniones p-n con emisores difundidos. Uno de los principales problemas asociados a la formación del emisor por difusión de fósforo, es la degradación superficial del substrato como consecuencia de su exposición a grandes concentraciones de fosfina (fuente de fósforo). En efecto, la rugosidad del silicio debe ser minuciosamente controlada, puesto que éste servirá de base para el posterior crecimiento epitaxial y por tanto debe presentar una superficie prístina para evitar una degradación morfológica y cristalográfica de las capas superiores. En este sentido, el Capítulo 4 incluye un análisis exhaustivo sobre la degradación morfológica de los substratos de silicio durante la formación del emisor. Además, se proponen diferentes alternativas para la recuperación de la superficie con el fin de conseguir rugosidades sub-nanométricas, que no comprometan la calidad del crecimiento epitaxial. Finalmente, a través de desarrollos teóricos, se establecerá una correlación entre la degradación morfológica (observada experimentalmente) con el perfil de difusión del fósforo en el silicio y por tanto, con las características del emisor. Una vez concluida la formación de la unión p-n propiamente dicha, se abordan los problemas relacionados con el crecimiento de la capa de nucleación de GaP. Por un lado, esta capa será la encargada de pasivar la subcélula de silicio, por lo que su crecimiento debe ser regular y homogéneo para que la superficie de silicio quede totalmente pasivada, de tal forma que la velocidad de recombinación superficial en la interfaz GaP/Si sea mínima. Por otro lado, su crecimiento debe ser tal que minimice la aparición de los defectos típicos de una heteroepitaxia de una capa polar sobre un substrato no polar -denominados dominios de antifase-. En el Capítulo 5 se exploran diferentes rutinas de nucleación, dentro del gran abanico de posibilidades existentes, para conseguir una capa de GaP con una buena calidad morfológica y estructural, que será analizada mediante diversas técnicas de caracterización microscópicas. La última parte de esta Tesis está dedicada al estudio de las propiedades fotovoltaicas de la célula inferior. En ella se analiza la evolución de los tiempos de vida de portadores minoritarios de la base durante dos etapas claves en el desarrollo de la estructura Ill-V/Si: la formación de la célula inferior y el crecimiento de las capas III-V. Este estudio se ha llevado a cabo en colaboración con la Universidad de Ohio, que cuentan con una gran experiencia en el crecimiento de materiales III-V sobre silicio. Esta tesis concluye destacando las conclusiones globales del trabajo realizado y proponiendo diversas líneas de trabajo a emprender en el futuro. ABSTRACT This thesis pursues the development and growth of hybrid solar cells -through Metal Organic Vapor Phase Epitaxy (MOVPE)- formed by III-V semiconductors on silicon substrates. This integration aims to provide an alternative to current III-V cells, which, despite hold the efficiency record for photovoltaic devices, their cost is, today, too high to be economically competitive to conventional silicon cells. Accordingly, the target of this project is to link the already demonstrated efficiency potential of III-V semiconductor multijunction solar cell architectures with the low cost and unconstrained availability of silicon substrates. Within the existing alternatives for the integration of III-V semiconductors on silicon substrates, this thesis is based on the metamorphic approach for the development of GaAsP/Si dual-junction solar cells. In this approach, the accommodation of the lattice mismatch is handle through the appearance of crystallographic defects (namely dislocations), which will be confined through the incorporation of a graded buffer layer. The resulting surface will have, on the one hand a good structural quality; and on the other hand the desired lattice parameter. Different research groups have been working in the last years in a structure similar to the one here described, being most of their efforts directed towards the optimization of the heteroepitaxial growth of III-V compounds on Si, with the primary goal of minimizing the appearance of crystal defects. However, none of these groups has paid much attention to the development and optimization of the bottom silicon cell, which, indeed, will play an important role on the overall solar cell performance. In this respect, the idea of this thesis is to complete the work done so far in this field by focusing on the design and optimization of the bottom silicon cell, to harness its efficiency. This work is divided into six chapters, organized according to the natural progress of the bottom cell development. After a brief introduction to the growth of III-V semiconductors on Si substrates, pointing out the different alternatives for their integration; we move to the experimental part, which is initiated by an extensive description and characterization of silicon substrates -the base of the III-V structure-. In this chapter, a comprehensive analysis of the different treatments (chemical and thermal) required for preparing silicon surfaces for subsequent epitaxial growth is presented. Next step on the development of the bottom cell is the formation of the p-n junction itself, which is faced in Chapter 3. Firstly, the optimization of the emitter configuration (in terms of doping and thickness) is handling by analytic models. This study includes a comparison between the different alternatives for the emitter formation, evaluating the advantages and disadvantages of each approach. After the theoretical design of the emitter, it is defined (through the modeling of the P-in-Si diffusion process) a practical parameter space for the experimental implementation of this emitter configuration. The characterization of these emitters through different analytical tools (i.e. ECV or SIMS) will validate and provide experimental support for the theoretical models. A side effect of the formation of the emitter by P diffusion is the roughening of the Si surface. Accordingly, once the p-n junction is formed, it is necessary to ensure that the Si surface is smooth enough and clean for subsequent phases. Indeed, the roughness of the Si must be carefully controlled since it will be the basis for the epitaxial growth. Accordingly, after quantifying (experimentally and by theoretical models) the impact of the phosphorus on the silicon surface morphology, different alternatives for the recovery of the surface are proposed in order to achieve a sub-nanometer roughness which does not endanger the quality of the incoming III-V layers. Moving a step further in the development of the Ill-V/Si structure implies to address the challenges associated to the GaP on Si nucleation. On the one hand, this layer will provide surface passivation to the emitter. In this sense, the growth of the III-V layer must be homogeneous and continuous so the Si emitter gets fully passivated, providing a minimal surface recombination velocity at the interface. On the other hand, the growth should be such that the appearance of typical defects related to the growth of a polar layer on a non-polar substrate is minimized. Chapter 5 includes an exhaustive study of the GaP on Si nucleation process, exploring different nucleation routines for achieving a high morphological and structural quality, which will be characterized by means of different microscopy techniques. Finally, an extensive study of the photovoltaic properties of the bottom cell and its evolution during key phases in the fabrication of a MOCVD-grown III-V-on-Si epitaxial structure (i.e. the formation of the bottom cell; and the growth of III-V layers) will be presented in the last part of this thesis. This study was conducted in collaboration with The Ohio State University, who has extensive experience in the growth of III-V materials on silicon. This thesis concludes by highlighting the overall conclusions of the presented work and proposing different lines of work to be undertaken in the future.

Ellipsometric study of nematic alignment on silicon oxides for display

Vertical Alignment Nematics (VANs) displays are a form of LCDs in which the liquid crystals naturally align vertically to the glass substrates. In spite of their name, the liquid crystal (LC) director is never exactly vertical, rather it always show a small angle with the normal to the sample plane called tilt that may vary throughout the cell bulk. Its values are ultimately determined by the pretilt, defined as the tilt angle on the surfaces in the absence of voltage.

Silicon oxides as alignment surfaces for vertically-aligned nematics in photonic devices

A comparative study on alignment performance and microstructure of inorganic layers used for liquid crystal cell conditioning has been carried out. The study has focused on two specific materials, SiOx and SiO2, deposited under different conditions. The purpose was to establish a relationship between layer microstructure and liquid crystal alignment. The surface morphology has been studied by FESEM and AFM. An analysis on liquid crystal alignment, pretilt angle, response time, contrast ratio and the conditions to develop backflow effect (significant rise time increase due to pure homeotropic alignment) on vertically-aligned nematic cells has been carried out. A technique to overcome the presence of backflow has been identified. The full comparative study of SiOx and SiO2 layer properties and their influence over liquid crystal alignment and electrooptic response is presented.

A novel high-sensitivity, low-power, liquid crystal temperature sensor

A novel temperature sensor based on nematic liquid crystal permittivity as a sensing magnitude, is presented. This sensor consists of a specific micrometric structure that gives considerable advantages from other previous related liquid crystal (LC) sensors. The analytical study reveals that permittivity change with temperature is introduced in a hyperbolic cosine function, increasing the sensitivity term considerably. The experimental data has been obtained for ranges from −6 °C to 100 °C. Despite this, following the LC datasheet, theoretical ranges from −40 °C to 109 °C could be achieved. These results have revealed maximum sensitivities of 33 mVrms/°C for certain temperature ranges; three times more than of most silicon temperature sensors. As it was predicted by the analytical study, the micrometric size of the proposed structure produces a high output voltage. Moreover the voltage’s sensitivity to temperature response can be controlled by the applied voltage. This response allows temperature measurements to be carried out without any amplification or conditioning circuitry, with very low power consumption.

Impact of metal-organic vapor phase epitaxy environment on silicon bulk lifetime for III–V-on-Si multijunction solar cells

With the final goal of integrating III-V materials on silicon substrates for tandem solar cells, the influence of the Metal-Organic Vapor Phase Epitaxy (MOVPE) environment on the minority carrier properties of silicon wafers has been evaluated. These properties will essentially determine the photovoltaic performance of the bottom cell in a III-V-on-Si tandem solar cell. A comparison of the base minority carrier lifetimes obtained for different thermal processes carried out in a MOVPE reactor on Czochralski silicon wafers has been carried out. An important degradation of minority carrier lifetime during the surface preparation (i.e. H2 anneal) has been observed. Three different mechanisms have been proposed for explaining this behavior: 1) the introduction of extrinsic impurities coming from the reactor; 2) the activation of intrinsic lifetime killing impurities coming from the wafer itself; and finally, 3) the formation of crystal defects, which eventually become recombination centers. The effect of the emitter formation by phosphorus diffusion has also been evaluated. In this sense, it has been reported that lifetime can be recovered during the emitter formation either by the effect of the P on extracting impurities, or by the role of the atomic hydrogen on passivating the defects.

Deposition reactors for solar grade silicon: a comparative thermal analysis of a Siemens reactor and a fluidized bed reactor

Polysilicon production costs contribute approximately to 25-33% of the overall cost of the solar panels and a similar fraction of the total energy invested in their fabrication. Understanding the energy losses and the behaviour of process temperature is an essential requirement as one moves forward to design and build large scale polysilicon manufacturing plants. In this paper we present thermal models for two processes for poly production, viz., the Siemens process using trichlorosilane (TCS) as precursor and the fluid bed process using silane (monosilane, MS).We validate the models with some experimental measurements on prototype laboratory reactors relating the temperature profiles to product quality. A model sensitivity analysis is also performed, and the efects of some key parameters such as reactor wall emissivity, gas distributor temperature, etc., on temperature distribution and product quality are examined. The information presented in this paper is useful for further understanding of the strengths and weaknesses of both deposition technologies, and will help in optimal temperature profiling of these systems aiming at lowering production costs without compromising the solar cell quality.