Comparison of Boost-Based MPPT Topologies for Space Applications

Several boost-derived topologies are analyzed and compared for an aerospace application that uses a 100 V voltage bus. All these topologies have been designed and optimized considering the electrical requirements and the reduced number of space-qualified components. The comparison evaluates the power losses, mass, and dynamic response. Special attention has been paid to those topologies that may cancel the inherent right half plane zero (RHP) zero of the boost topology. Experimental results of the less common topologies are presented.

3-Phase Rectifier System with very demanding dynamic load: Architecture analysis and control strategy

A distributed power architecture for aerospace application with very restrictive specifications is analyzed. Parameters as volume, weight and losses are analyzed for the considered power architectures. In order to protect the 3 phase generator against high load steps, an intermediate bus (based in a high capacitance) to provide energy to the loads during the high load steps is included. Prototypes of the selected architecture for the rectifier and EMI filter are built and the energy control is validated.

Performance metrics for small-signal stability assessment of DC-distributed power-system-architecture comparisons

The objective of this paper is to provide performance metrics for small-signal stability assessment of a given system architecture. The stability margins are stated utilizing a concept of maximum peak criteria (MPC) derived from the behavior of an impedance-based sensitivity function. For each minor-loop gain defined at every system interface, a single number to state the robustness of stability is provided based on the computed maximum value of the corresponding sensitivity function. In order to compare various power-architecture solutions in terms of stability, a parameter providing an overall measure of the whole system stability is required. The selected figure of merit is geometric average of each maximum peak value within the system. It provides a meaningful metrics for system comparisons: the best system in terms of robust stability is the one that minimizes this index. In addition, the largest peak value within the system interfaces is given thus detecting the weakest point of the system in terms of robustness.

Interleaved multi-cell isolated three-phase PWM rectifier system for aircraft applications

Recently there has been an important increase in electric equipment, as well as, electric power demand in aircrafts applications. This prompts to the necessity of efficient, reliable, and low-weight converters, especially rectifiers from 115VAC to 270VDC because these voltages are used in power distribution. In order to obtain a high efficiency, in aircraft application where the derating in semiconductors is high, normally several semiconductors are used in parallel to decrease the conduction losses. However, this is in conflict with high reliability. To match both goals of high efficiency and reliability, this work proposes an interleaved multi-cell rectifier system, employing several converter cells in parallel instead of parallel-connected semiconductors. In this work a 10kW multi-cell isolated rectifier system has been designed where each cell is composed of a buck type rectifier and a full bridge DC-DC converter. The implemented system exhibits 91% of efficiency, high power density (10kW/10kg), low THD (2.5%), and n−1 fault tolerance which complies, with military aircraft standards.

Simplified small-signal stability analysis for optimized power system architecture

The optimization of power architectures is a complex problem due to the plethora of different ways to connect various system components. This issue has been addressed by developing a methodology to design and optimize power architectures in terms of the most fundamental system features: size, cost and efficiency. The process assumes various simplifications regarding the utilized DC/DC converter models in order to prevent the simulation time to become excessive and, therefore, stability is not considered. The objective of this paper is to present a simplified method to analyze small-signal stability of a system in order to integrate it into the optimization methodology. A black-box modeling approach, applicable to commercial converters with unknown topology and components, is based on frequency response measurements enabling the system small-signal stability assessment. The applicability of passivity-based stability criterion is assessed. The stability margins are stated utilizing a concept of maximum peak criteria derived from the behavior of the impedance-based sensitivity function that provides a single number to state the robustness of the stability of a well-defined minor-loop gain.

Limits of the frequency response for the analysis of ripple-based controllers

Advanced control techniques like V2, Vout hysteresis or V2Ic can strongly reduce the required output capacitance in PowerSoC converters. Techniques to analyze power converters based on the analysis of the frequency response are not suitable for ripple-based controllers that use fast-scale dynamics to control the power stage. This paper proves that the use of discrete modeling together with Floquet theory is a very powerful tool to model the system and derive stable region diagrams for sensitivity analysis. It is applied to V 2Ic control, validating experimentally that Floquet theory predicts accurately subharmonic oscillations. This method is applied to several ripplebased controllers, providing higher accuracy when it is compared with other techniques based on the frequency response. The paper experimentally validates the usefulness of the discrete modeling and the Floquet theory on a 5 MHz Buck converter with a V 2Ic control.

Improvement of the Dynamic Performance of a Multiphase Current Controlled Buck Converter using an Auxiliary Synchronous Buck Converter as an Additional Energy Path

This work is related to the output impedance improvement of a Multiphase Buck converter with Peak Current Mode Control (PCMC) by means of introducing an additional power path that virtually increases the output capacitance during transients. Various solutions that can be employed to improve the dynamic behavior of the converter system exist, but nearly all solutions are developed for a Single Phase Buck converter with Voltage Mode Control (VMC), while in the VRM applications, due to the high currents, the system is usually implemented as a Multiphase Buck Converter with Current Mode Control. The additional energy path, as presented here, is introduced with the Output Impedance Correction Circuit (OICC) based on the Controlled Current Source (CCS). The OICC is used to inject or extract a current n-1 times larger than the output capacitor current, thus virtually increasing n times the value of the output capacitance during the transients. Furthermore, this work extends the OICC concept to a Multiphase Buck Converter system while comparing proposed solution with the system that has n times bigger output capacitor. In addition, the OICC is implemented as a Synchronous Buck Converter with PCMC, thus reducing its influence on the system efficiency.

Forward micro-inverter with primary-parallel secondary-series multicore transformer

This paper presents a primary-parallel secondary-series multicore forward micro-inverter for photovoltaic AC-module application. The proposed solution changes the number of active phases depending on the grid voltage, thus enabling the usage of low-profile unitary turns ratio transformers. Therefore, the transformers are well coupled and the overall performance of the inverter is improved. Due to the multiphase solution the number of devices increases but, the current stress and losses per device are reduced contributing to an easier thermal management. Furthermore, the decoupling capacitor is split between the phases, contributing to a low-profile solution without electrolytic capacitors suitable to be mounted in the frame of a PV module.

Design and Multi-Objective Optimization of EMI Input Filters

An EMI filter design procedure for power converters is proposed. Based on a given noise spectrum, information about the converter noise source impedance and design constraints, the design space of the input filter is defined. The design is based on component databases and detailed models of the filter components, including high frequency parasitics, losses, weight, volume, etc.. The design space is mapped onto a performance space in which different filter implementations are evaluated and compared. A multi-objective optimization approach is used to obtain optimal designs w.r.t. a given performance function.

Design and analysis of ripple-based controls based on the discrete modeling and Floquet theory

Ripple-based controls can strongly reduce the required output capacitance in PowerSoC converter thanks to a very fast dynamic response. Unfortunately, these controls are prone to sub-harmonic oscillations and several parameters affect the stability of these systems. This paper derives and validates a simulation-based modeling and stability analysis of a closed-loop V 2Ic control applied to a 5 MHz Buck converter using discrete modeling and Floquet theory to predict stability. This allows the derivation of sensitivity analysis to design robust systems. The work is extended to different V 2 architectures using the same methodology.

Convertidor Cc-Cc Reductor Síncrono con Red de Cancelación de Rizado para un Amplificador de Envolvente de Alto Ancho de Banda y Alto Rendimiento

En este artículo se presenta un convertidor CC-CC de una etapa para un amplificador de envolvente de alto rendimiento y alto ancho de banda. Se ha aplicado la técnica de cancelación de rizado a un convertidor reductor síncrono para cancelar el rizado de corriente de salida y así poder disminuir la frecuencia de conmutación sin una reducción en el ancho de banda de gran señal. Se ha modelado el convertidor reductor con red de cancelación de rizado y se detalla el nuevo diseño del mismo, presentándose las ventajas del diseño propuesto así como la validación experimental. La función de transferencia del filtro de salida del convertidor reductor con red de cancelación de rizado se ha modelado y comparado con medidas experimentales, mostrando una buena correspondencia. Se ha validado experimentalmente el diseño propuesto para una frecuencia de conmutación de 4MHz para tensión de salida continua y con una referencia inusoidal. Asimismo, se incluye una validación experimental adicional, donde se compara el rendimiento de esta solución con el del diseño equivalente (mismo ancho de banda y rizado de tensión de salida) del convertidor reductor síncrono convencional.

Bidirectional multiple port dc/dc transformer based on a series resonant converter

In this paper a novel bidirectional multiple port dc/dc transformer topology is presented. The novel concept for dc/dc transformer is based on the Series Resonant Converter (SRC)topology operated at its resonant frequency point. This allows for higher switching frequency to be adopted and enables high efficiency/high power density operation. The feasibility of the proposed concept is verified on a 300W, 700 kHz three port prototype with 390V input voltage and 48V and 12V output voltages. A peak overall efficiency of 93% is measured at full load. A very good load and cross regulation characteristic of the converter is observed in the whole load range, from full load to open circuit. The sensitivity analysis of the resonant capacitance is also performed showing very slight deterioration in the converter performances when a resonant capacitor is changed ±30% of its nominal value.

Analysis and validation of a multiple output series resonant converter

In this paper a novel bidirectional multiple port dc/dc transformer topology is presented. The novel concept for dc/dc transformer is based on the Series Resonant Converter (SRC) topology operated at its resonant frequency point. This allows for higher switching frequency to be adopted and enables high efficiency/high power density operation. The feasibility of the proposed concept is verified on a 300W, 700 kHz three port prototype with 390V input voltage and 48V and 12V output voltages. A peak overall efficiency of 93% is measured at full load. A very good load and cross regulation characteristic of the converter is observed in the whole load range, from full load to open circuit. The sensitivity analysis of the resonant capacitance is also performed showing very slight deterioration in the converter performances when a resonant capacitor is changed ±30% of its nominal value.

Ripple cancellation technique applied to a synchronous buck converter to achieve very high bandwidth and very high efficiency envelope amplifier

This work presents a single stage converter for a high bandwidth and a high efficiency envelope amplifier. The current ripple cancellation technique is applied to a synchronous buck converter to cancel the output current ripple and to decrease the switching frequency without a reduction in the large signal bandwidth. The converter is modeled and the new design with ripple cancellation circuit is detailed. The advantages of the proposed design are presented and validated experimentally. The transfer function of the output filter of the buck converter with ripple cancellation circuit has been modeled and compared to measurements, showing a good correspondence. Experimental validation is provided at 4MHz of switching frequency for DC and variable output voltage for a sinusoidal and a 64QAM signal. Additional experimental validation of the efficiency improvement is provided, compared to the equivalent design (same bandwidth and output voltage ripple) of the conventional buck converter.

Multiphase Current Controlled Buck Converter with energy recycling Output Impedance Correction Circuit (OICC)

This work is related to the output impedance improvement of a Multiphase Buck converter with Peak Current Mode Control (PCMC) by means of introducing an additional power path that virtually increases the output capacitance during transients. Various solutions that can be employed to improve the dynamic behavior of the converter system exist, but nearly all solutions are developed for a Single Phase Buck converter with Voltage Mode Control (VMC), while in the VRM applications, due to the high currents, the system is usually implemented as a Multiphase Buck Converter with Current Mode Control. The Output Impedance Correction Circuit (OICC) is used to inject or extract a current n-1 times larger than the output capacitor current, thus virtually increasing n times the value of the output capacitance during the transients. Furthermore, this work extends the OICC concept to a Multiphase Buck Converter system while comparing proposed solution with the system that has n times bigger output capacitor. In addition, the OICC is implemented as a Synchronous Buck Converter with PCMC, thus reducing its influence on the system efficiency