Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform

One of the main concerns of evolvable and adaptive systems is the need of a training mechanism, which is normally done by using a training reference and a test input. The fitness function to be optimized during the evolution (training) phase is obtained by comparing the output of the candidate systems against the reference. The adaptivity that this type of systems may provide by re-evolving during operation is especially important for applications with runtime variable conditions. However, fully automated self-adaptivity poses additional problems. For instance, in some cases, it is not possible to have such reference, because the changes in the environment conditions are unknown, so it becomes difficult to autonomously identify which problem requires to be solved, and hence, what conditions should be representative for an adequate re-evolution. In this paper, a solution to solve this dependency is presented and analyzed. The system consists of an image filter application mapped on an evolvable hardware platform, able to evolve using two consecutive frames from a camera as both test and reference images. The system is entirely mapped in an FPGA, and native dynamic and partial reconfiguration is used for evolution. It is also shown that using such images, both of them being noisy, as input and reference images in the evolution phase of the system is equivalent or even better than evolving the filter with offline images. The combination of both techniques results in the completely autonomous, noise type/level agnostic filtering system without reference image requirement described along the paper.

Floating-point exponentiation units for reconfigurable computing

The high performance and capacity of current FPGAs makes them suitable as acceleration co-processors. This article studies the implementation, for such accelerators, of the floating-point power function xy as defined by the C99 and IEEE 754-2008 standards, generalized here to arbitrary exponent and mantissa sizes. Last-bit accuracy at the smallest possible cost is obtained thanks to a careful study of the various subcomponents: a floating-point logarithm, a modified floating-point exponential, and a truncated floating-point multiplier. A parameterized architecture generator in the open-source FloPoCo project is presented in details and evaluated.

A novel FPGA-based evolvable hardware system based on multiple processing arrays

In this paper, an architecture based on a scalable and flexible set of Evolvable Processing arrays is presented. FPGA-native Dynamic Partial Reconfiguration (DPR) is used for evolution, which is done intrinsically, letting the system to adapt autonomously to variable run-time conditions, including the presence of transient and permanent faults. The architecture supports different modes of operation, namely: independent, parallel, cascaded or bypass mode. These modes of operation can be used during evolution time or during normal operation. The evolvability of the architecture is combined with fault-tolerance techniques, to enhance the platform with self-healing features, making it suitable for applications which require both high adaptability and reliability. Experimental results show that such a system may benefit from accelerated evolution times, increased performance and improved dependability, mainly by increasing fault tolerance for transient and permanent faults, as well as providing some fault identification possibilities. The evolvable HW array shown is tailored for window-based image processing applications.

Contribution to active multi-beam reconfigurable antennas for L and S bands

La presente tesis doctoral con título "Contribution to Active Multi-Beam Reconfigurable Antennas for L and S Bands" ha sido desarrollada por el investigador ingeniero de telecomunicación estudiante de doctorado Javier García-Gasco Trujillo en el Grupo de Radiación del Departamento de Señales, Sistemas y Radiocomunicaciones de la ETSI de Telecomunicación de la Universidad Politécnica de Madrid bajo la dirección de los doctores Manuel Sierra Pérez y José Manuel Fernández González. Durante décadas, el desarrollo de antenas de apuntamiento electrónico ha estado limitado al área militar. Su alto coste y su gran complejidad eran los mayores obstáculos que frenaban la introducción de esta tecnología en aplicaciones comerciales de gran escala. La reciente aparición de componentes de estado sólido prácticos, fiables, y de bajo coste ha roto la barrera del coste y ha reducido la complejidad, haciendo que las antenas reconfigurables de apuntamiento electrónico sean una opción viable en un futuro cercano. De esta manera, las antenas phased array podrían llegar a ser la joya de la corona que permitan alcanzar los futuros retos presentes en los sistemas de comunicaciones tanto civiles como militares. Así pues, ahora es el momento de investigar en el desarrollo de antenas de apuntamiento electrónico de bajo coste, donde los nuevos componentes de estado sólido comerciales forman el núcleo duro de la arquitectura. De esta forma, el estudio e implementación de estos arrays de antenas activas de apuntamiento electrónico capaces de controlar la fase y amplitud de las distintas señales implicadas es uno de los grandes retos de nuestro tiempo. Esta tesis se enfrenta a este desafío, proponiendo novedosas redes de apuntamiento electrónico e innovadores módulos de transmisión/recepción (T/R) utilizando componentes de estado sólido de bajo coste, que podrán integrar asequibles antenas activas reconfigurables multihaz en bandas L y S. En la primera parte de la tesis se realiza una descripción del estado del arte de las antenas phased array, incluyendo su base teórica y sus ventajas competitivas. Debido a que las contribuciones obtenidas en la presente tesis han sido realizadas dentro de distintos proyectos de investigación, donde se han manejada antenas de simple/doble polarización circular y simple/doble banda de trabajo, se describen detenidamente los dos proyectos más relevantes de la investigación: el radar de basura espacial de la Agencia Espacial Europea (ESA), Space Situational Awareness (SSA); y la estación base de seguimiento y control de satélites de órbita baja, GEOdesic Dome Array (GEODA). Sin lugar a dudas, los dispositivos desfasadores son uno de los componentes clave en el diseño de antenas phased arrays. Recientemente se ha observado una gran variación en el precio final de estos dispositivos, llegando en ocasiones a límites inasequibles. Así pues, se han propuesto distintas técnicas de conformación de haz alternativas a la utilización de componentes desfasadores comerciales: el desfasador de líneas conmutadas, la red de haz conmutado, y una novedosa red desfasadora divisora/combinadora de potencia. Para mostrar un uso práctico de las mismas, se ha propuesto el uso de las tres alternativas para el caso práctico del subarray de cinco elementos de la celda GEODA-SARAS. Tras dicho estudio se obtiene que la novedosa red desfasadora divisora/combinadora de potencia propuesta es la que mejor relación comportamiento/coste presenta. Para verificar su correcto funcionamiento se construye y mide los dos bloques principales de los que está compuesta la red total, comprobando que en efecto la red responde según lo esperado. La estructura más simple que permite realizar un barrido plano es el array triangular de tres elementos. Se ha realizado el diseño de una nueva red multihaz que es capaz de proporcionar tres haces ortogonales en un ángulo de elevación _0 y un haz adicional en la dirección broadside utilizando el mencionado array triangular de tres elementos como antena. En primer lugar se realizar una breve introducción al estado del arte de las redes clásicas multihaz. Así mismo se comentan innovadores diseños de redes multihaz sin pérdidas. El estudio da paso a las redes disipativas, de tal forma que se analiza su base matemática y se muestran distintas aplicaciones en arrays triangulares de tres elementos. Finalmente, la novedosa red básica propuesta se presenta, mostrando simulaciones y medidas de la misma para el caso prácticoo de GEODA. También se ha diseñado, construido y medido una red compuesta por dos redes básicas complementarias capaz de proporcionar seis haces cuasi-ortogonales en una dirección _0 con dos haces superpuestos en broadside. La red propuesta queda totalmente validada con la fabricación y medida de estos con prototipos. Las cadenas de RF de los módulos T/R de la nueva antena GEODA-SARAS no son algo trivial. Con el fin de mostrar el desarrollo de una cadena compleja con una gran densidad de componentes de estado sólido, se presenta una descripción detallada de los distintos componentes que integran las cadenas de RF tanto en transmisión como en recepción de la nueva antena GEODA-SARAS. Tras presentar las especificaciones de la antena GEODA-SARA y su diagrama de bloques esquemático se describen los dos bloques principales de las cadenas de RF: la celda de cinco elementos, y el módulo de conversión de panel. De la misma manera también se presentará el módulo de calibración integrado dentro de los dos bloques principales. Para comprobar que el funcionamiento esperado de la placa es el adecuado, se realizará un análisis que tratará entre otros datos: la potencia máxima en la entrada del transmisor (comprobando la saturación de la cadena), señal de recepción mínima y máxima (verificando el rango de sensibilidad requerido), y el factor G/T (cumpliendo la especificación necesaria). Así mismo se mostrará un breve estudio del efecto de la cuantificación de la fase en el conformado de haz de RF. Los estudios muestran que la composición de las cadenas de RF permite el cumplimiento de las especificaciones necesarias. Finalmente la tesis muestra las conclusiones globales del trabajo realizado y las líneas futuras a seguir para continuar con esta línea de investigación. ABSTRACT This PhD thesis named "Contribution to Active Multi-Beam Reconfigurable Antennas for L and S Bands", has been written by the Electrical Engineer MSc. researcher Javier García-Gasco Trujillo in the Grupo de Radiación of the Departamento de Señales, Sistemas y Radiocomunicaciones from the ETSI de Telecomunicación of the Universidad Politécnica de Madrid. For decades, the implementation of electronically steerable phased array antennas was confined to the military area. Their high cost and complexity were the major obstacles to introduce this technology in large scale commercial applications. The recent emergence of new practical, low-cost, and highly reliable solid state devices; breaks the barrier of cost and reduces the complexity, making active phased arrays a viable future option. Thus, phased array antennas could be the crown jewel that allow to meet the future challenges in military and civilian communication systems. Now is time to deploy low-cost phased array antennas, where newly commercial components form the core of the architecture. Therefore, the study and implementation of these novel low-cost and highly efficient solid state phased array blocks capable of controlling signal phase/amplitude accurately is one of the great challenges of our time. This thesis faces this challenge, proposing innovative electronic beam steering networks and transmitter/ receiver (T/R) modules using affordable solid state components, which could integrate fair reconfigurable phased array antennas working in L and S bands. In the first part of the thesis, a description of the state of art of phased array antennas, including their fundamentals and their competitive advantages, is presented. Since thesis contributions have been carried out for different research projects, where antennas with single/double circular polarization and single/double working frequency bands have been examined, frameworks of the two more important projects are detailed: the Space Situational Awareness (SSA) programme from the European Space Agency (ESA), and the GEOdesic Dome Array (GEODA) project from ISDEFE-INSA and the ESA. Undoubtedly, phase shifter devices are one of the key components of phased array antennas. Recent years have witnessed wide fluctuations in commercial phase shifter prices, which sometimes led to unaffordable limit. Several RF steering technique alternatives to the commercial phase shifters are proposed, summarized, and compared: the switched line phase shifter, the switched-beam network, and the novel phase shifter power splitter/combiner network. In order to show a practical use of the three different techniques, the five element GEODA-SARAS subarray is proposed as a real case of study. Finally, a practical study of a newly phase shifter power splitter/combiner network for a subarray of five radiating elements with triangular distribution is shown. Measurements of the two different phase shifter power splitter/combiner prototypes integrating the whole network are also depicted, demonstrating their proper performance. A triangular cell of three radiating elements is the simplest way to obtain a planar scanner. A new multibeam network configuration that provides three orthogonal beams in a desired _0 elevation angle and an extra one in the broadside steering direction for a triangular array of three radiating elements is introduced. Firstly, a short introduction to the state of art of classical multi-beam networks is presented. Lossless network analysis, including original lossless network designs, are also commented. General dissipative network theory as well as applications for array antennas of three radiating elements are depicted. The proposed final basic multi-beam network are simulated, built and measured to the GEODA cell practical case. A combined network that provides six orthogonal beams in a desired _0 elevation angle and a double seventh one in the broadside direction by using two complementary proposed basic networks will be shown. Measurements of the whole system will be also depicted, verifying the expected behavior. GEODA-SARAS T/R module RF chains are not a trivial design. A thorough description of all the components compounding GEODA-SARAS T/R module RF chains is presented. After presenting the general specifications of the GEODA-SARAS antenna and its block diagrams; two main blocks of the RF chains, the five element cell and the panel conversion module, are depicted and analyzed. Calibration module integrated within the two main blocks are also depicted. Signal flow throw the system analyzing critical situations such as maximum transmitted power (testing the chain unsaturation), minimum and maximum receiving signal (verifying sensitivity range), maximum receiver interference signals (assuring a proper reception), and G/T factor (fulfilling the technical specification) are evaluated. Phase quantization error effects are also listed. Finally, the manuscript contains the conclusions drawn of the present research and the future work.

Modelización e integración de sistemas de adquisición de datos inteligentes en sistemas de instrumentación para dispositivos de fusión

La obtención de energía a partir de la fusión nuclear por confinamiento magnético del plasma, es uno de los principales objetivos dentro de la comunidad científica dedicada a la energía nuclear. Desde la construcción del primer dispositivo de fusión, hasta la actualidad, se han llevado a cabo multitud de experimentos, que hoy en día, gran parte de ellos dan soporte al proyecto International Thermonuclear Experimental Reactor (ITER). El principal problema al que se enfrenta ITER, se basa en la monitorización y el control del plasma. Gracias a las nuevas tecnologías, los sistemas de instrumentación y control permiten acercarse más a la solución del problema, pero a su vez, es más complicado estandarizar los sistemas de adquisición de datos que se usan, no solo en ITER, sino en otros proyectos de igual complejidad. Desarrollar nuevas implementaciones hardware y software bajo los requisitos de los diagnósticos definidos por los científicos, supone una gran inversión de tiempo, retrasando la ejecución de nuevos experimentos. Por ello, la solución que plantea esta tesis, consiste en la definición de una metodología de diseño que permite implementar sistemas de adquisición de datos inteligentes y su fácil integración en entornos de fusión para la implementación de diagnósticos. Esta metodología requiere del uso de los dispositivos Reconfigurable Input/Output (RIO) y Flexible RIO (FlexRIO), que son sistemas embebidos basados en tecnología Field-Programmable Gate Array (FPGA). Para completar la metodología de diseño, estos dispositivos van a ser soportados por un software basado en EPICS Device Support utilizando la tecnología EPICS software asynDriver. Esta metodología se ha evaluado implementando prototipos para los controladores rápidos de planta de ITER, tanto para casos prácticos de ámbito general como adquisición de datos e imágenes, como para casos concretos como el diagnóstico del fission chamber, implementando pre-procesado en tiempo real. Además de casos prácticos, esta metodología se ha utilizado para implementar casos reales, como el Ion Source Hydrogen Positive (ISHP), desarrollada por el European Spallation Source (ESS Bilbao) y la Universidad del País Vasco. Finalmente, atendiendo a las necesidades que los experimentos en los entornos de fusión requieren, se ha diseñado un mecanismo mediante el cual los sistemas de adquisición de datos, que pueden ser implementados mediante la metodología de diseño propuesta, pueden integrar un reloj hardware capaz de sincronizarse con el protocolo IEEE1588-V2, permitiendo a estos, obtener los TimeStamps de las muestras adquiridas con una exactitud y precisión de decenas de nanosegundos y realizar streaming de datos con TimeStamps. ABSTRACT Fusion energy reaching by means of nuclear fusion plasma confinement is one of the main goals inside nuclear energy scientific community. Since the first fusion device was built, many experiments have been carried out and now, most of them give support to the International Thermonuclear Experimental Reactor (ITER) project. The main difficulty that ITER has to overcome is the plasma monitoring and control. Due to new technologies, the instrumentation and control systems allow an approaching to the solution, but in turn, the standardization of the used data acquisition systems, not only in ITER but also in other similar projects, is more complex. To develop new hardware and software implementations under scientific diagnostics requirements, entail time costs, delaying new experiments execution. Thus, this thesis presents a solution that consists in a design methodology definition, that permits the implementation of intelligent data acquisition systems and their easy integration into fusion environments for diagnostic purposes. This methodology requires the use of Reconfigurable Input/Output (RIO) and Flexible RIO (FlexRIO) devices, based on Field-Programmable Gate Array (FPGA) embedded technology. In order to complete the design methodology, these devices are going to be supported by an EPICS Device Support software, using asynDriver technology. This methodology has been evaluated implementing ITER PXIe fast controllers prototypes, as well as data and image acquisition, so as for concrete solutions like the fission chamber diagnostic use case, using real time preprocessing. Besides of these prototypes solutions, this methodology has been applied for the implementation of real experiments like the Ion Source Hydrogen Positive (ISHP), developed by the European Spallation Source and the Basque country University. Finally, a hardware mechanism has been designed to integrate a hardware clock into RIO/FlexRIO devices, to get synchronization with the IEEE1588-V2 precision time protocol. This implementation permits to data acquisition systems implemented under the defined methodology, to timestamp all data acquired with nanoseconds accuracy, permitting high throughput timestamped data streaming.

Desarrollo de un sistema hardware modular que implemente los instrumentos de un laboratorio de electrónica

El poder disponer de la instrumentación y los equipos electrónicos resulta vital en el diseño de circuitos analógicos. Permiten realizar las pruebas necesarias y el estudio para el buen funcionamiento de estos circuitos. Los equipos se pueden diferenciar en instrumentos de excitación, los que proporcionan las señales al circuito, y en instrumentos de medida, los que miden las señales generadas por el circuito. Estos equipos sirven de gran ayuda pero a su vez tienen un precio elevado lo que impide en muchos casos disponer de ellos. Por esta principal desventaja, se hace necesario conseguir un dispositivo de bajo coste que sustituya de alguna manera a los equipos reales. Si el instrumento es de medida, este sistema de bajo coste puede ser implementado mediante un equipo hardware encargado de adquirir los datos y una aplicación ejecutándose en un ordenador donde analizarlos y presentarlos en la pantalla. En el caso de que el instrumento sea de excitación, el único cometido del sistema hardware es el de proporcionar las señales cuya configuración ha enviado el ordenador. En un equipo real, es el propio equipo el que debe realizar todas esas acciones: adquisición, procesamiento y presentación de los datos. Además, la dificultad de realizar modificaciones o ampliaciones de las funcionalidades en un instrumento tradicional con respecto a una aplicación de queda patente. Debido a que un instrumento tradicional es un sistema cerrado y uno cuya configuración o procesamiento de datos es hecho por una aplicación, algunas de las modificaciones serían realizables modificando simplemente el software del programa de control, por lo que el coste de las modificaciones sería menor. En este proyecto se pretende implementar un sistema hardware que tenga las características y realice las funciones del equipamiento real que se pueda encontrar en un laboratorio de electrónica. También el desarrollo de una aplicación encargada del control y el análisis de las señales adquiridas, cuya interfaz gráfica se asemeje a la de los equipos reales para facilitar su uso. ABSTRACT. The instrumentation and electronic equipment are vital for the design of analogue circuits. They enable to perform the necessary testing and study for the proper functioning of these circuits. The devices can be classified into the following categories: excitation instruments, which transmit the signals to the circuit, and measuring instruments, those in charge of measuring the signals produced by the circuit. This equipment is considerably helpful, however, its high price often makes it hardly accessible. For this reason, low price equipment is needed in order to replace real devices. If the instrument is measuring, this low cost system can be implemented by hardware equipment to acquire the data and running on a computer where analyzing and present on the screen application. In case of an excitation the instrument, the only task of the hardware system is to provide signals which sent the computer configuration. In a real instrument, is the instrument itself that must perform all these actions: acquisition, processing and presentation of data. Moreover, the difficulty of making changes or additions to the features in traditional devices with respect to an application running on a computer is evident. This is due to the fact that a traditional instrument is a closed system and its configuration or data processing is made by an application. Therefore, certain changes can be made just by modifying the control program software. Consequently, the cost of these modifications is lower. This project aims to implement a hardware system with the same features and functions of any real device, available in an electronics laboratory. Besides, it aims to develop an application for the monitoring and analysis of acquired signals. This application is provided with a graphic interface resembling those of real devices in order to facilitate its use.

Reconfigurable video code (RVC) : aplicación para automatizar la asignación de procesos RUC a los núcleos de un sistema multiprocesador

El esquema actual que existe en el ámbito de la normalización y el diseño de nuevos estándares de codificación de vídeo se está convirtiendo en una tarea difícil de satisfacer la evolución y dinamismo de la comunidad de codificación de vídeo. El problema estaba centrado principalmente en poder explotar todas las características y similitudes entre los diferentes códecs y estándares de codificación. Esto ha obligado a tener que rediseñar algunas partes comunes a varios estándares de codificación. Este problema originó la aparición de una nueva iniciativa de normalización dentro del comité ISO/IEC MPEG, llamado Reconfigurable Video Coding (RVC). Su principal idea era desarrollar un estándar de codificación de vídeo que actualizase e incrementase progresivamente una biblioteca de los componentes, aportando flexibilidad y la capacidad de tener un código reconfigurable mediante el uso de un nuevo lenguaje orientado a flujo de Actores/datos denominado CAL. Este lenguaje se usa para la especificación de la biblioteca estándar y para la creación de instancias del modelo del decodificador. Más tarde, se desarrolló un nuevo estándar de codificación de vídeo denominado High Efficiency Video Coding (HEVC), que actualmente se encuentra en continuo proceso de actualización y desarrollo, que mejorase la eficiencia y compresión de la codificación de vídeo. Obviamente se ha desarrollado una visión de HEVC empleando la metodología de RVC. En este PFC, se emplean diferentes implementaciones de estándares empleando RVC. Por ejemplo mediante los decodificadores Mpeg 4 Part 2 SP y Mpeg 4 Part 10 CBP y PHP así como del nuevo estándar de codificación HEVC, resaltando las características y utilidad de cada uno de ellos. En RVC los algoritmos se describen mediante una clase de actores que intercambian flujos de datos (tokens) para realizar diferentes acciones. El objetivo de este proyecto es desarrollar un programa que, partiendo de los decodificadores anteriormente mencionados, una serie de secuencia de vídeo en diferentes formatos de compresión y una distribución estándar de los actores (para cada uno de los decodificadores), sea capaz de generar diferentes distribuciones de los actores del decodificador sobre uno o varios procesadores del sistema sobre el que se ejecuta, para conseguir la mayor eficiencia en la codificación del vídeo. La finalidad del programa desarrollado en este proyecto es la de facilitar la realización de las distribuciones de los actores sobre los núcleos del sistema, y obtener las mejores configuraciones posibles de una manera automática y eficiente. ABSTRACT. The current scheme that exists in the field of standardization and the design of new video coding standards is becoming a difficult task to meet the evolving and dynamic community of video encoding. The problem was centered mainly in order to exploit all the features and similarities between different codecs and encoding standards. This has forced redesigning some parts common to several coding standards. This problem led to the emergence of a new initiative for standardization within the ISO / IEC MPEG committee, called Reconfigurable Video Coding (RVC). His main idea was to develop a video coding standard and gradually incrementase to update a library of components, providing flexibility and the ability to have a reconfigurable code using a new flow -oriented language Actors / data called CAL. This language is used for the specification of the standard library and to the instantiation model decoder. Later, a new video coding standard called High Efficiency Video Coding (HEVC), which currently is in continuous process of updating and development, which would improve the compression efficiency and video coding is developed. Obviously has developed a vision of using the methodology HEVC RVC. In this PFC, different implementations using RVC standard are used. For example, using decoders MPEG 4 Part 2 SP and MPEG 4 Part 10 CBP and PHP and the new coding standard HEVC, highlighting the features and usefulness of each. In RVC, the algorithms are described by a class of actors that exchange streams of data (tokens) to perform different actions. The objective of this project is to develop a program that, based on the aforementioned decoders, a series of video stream in different compression formats and a standard distribution of actors (for each of the decoders), is capable of generating different distributions decoder actors on one or more processors of the system on which it runs, to achieve greater efficiency in video coding. The purpose of the program developed in this project is to facilitate the realization of the distributions of the actors on the cores of the system, and get the best possible settings automatically and efficiently.

Hardware timestamping for image acquisition system based on FlexRIO and IEEE 1588 v2 Standard

Current fusion devices consist of multiple diagnostics and hundreds or even thousands of signals. This situation forces on multiple occasions to use distributed data acquisition systems as the best approach. In this type of distributed systems, one of the most important issues is the synchronization between signals, so that it is possible to have a temporal correlation as accurate as possible between the acquired samples of all channels. In last decades, many fusion devices use different types of video cameras to provide inside views of the vessel during operations and to monitor plasma behavior. The synchronization between each video frame and the rest of the different signals acquired from any other diagnostics is essential in order to know correctly the plasma evolution, since it is possible to analyze jointly all the information having accurate knowledge of their temporal correlation. The developed system described in this paper allows timestamping image frames in a real-time acquisition and processing system using 1588 clock distribution. The system has been implemented using FPGA based devices together with a 1588 synchronized timing card (see Fig.1). The solution is based on a previous system [1] that allows image acquisition and real-time image processing based on PXIe technology. This architecture is fully compatible with the ITER Fast Controllers [2] and offers integration with EPICS to control and monitor the entire system. However, this set-up is not able to timestamp the frames acquired since the frame grabber module does not present any type of timing input (IRIG-B, GPS, PTP). To solve this lack, an IEEE1588 PXI timing device its used to provide an accurate way to synchronize distributed data acquisition systems using the Precision Time Protocol (PTP) IEEE 1588 2008 standard. This local timing device can be connected to a master clock device for global synchronization. The timing device has a buffer timestamp for each PXI trigger line and requires tha- a software application assigns each frame the corresponding timestamp. The previous action is critical and cannot be achieved if the frame rate is high. To solve this problem, it has been designed a solution that distributes the clock from the IEEE 1588 timing card to all FlexRIO devices [3]. This solution uses two PXI trigger lines that provide the capacity to assign timestamps to every frame acquired and register events by hardware in a deterministic way. The system provides a solution for timestamping frames to synchronize them with the rest of the different signals.

Elementos de sistemas operativos, de representación de la información y de procesadores hardware y software

Conceptos de representación binaria y de arquitecturas hardware y software con prácticas de laboratorio sobre Linux y ejercicios resueltos.

A proposal for an Internet of Things-based monitoring system composed by low capability, open source and open hardware devices

The Internet of Things makes use of a huge disparity of technologies at very different levels that help one to the other to accomplish goals that were previously regarded as unthinkable in terms of ubiquity or scalability. If the Internet of Things is expected to interconnect every day devices or appliances and enable communications between them, a broad range of new services, applications and products can be foreseen. For example, monitoring is a process where sensors have widespread use for measuring environmental parameters (temperature, light, chemical agents, etc.) but obtaining readings at the exact physical point they want to be obtained from, or about the exact wanted parameter can be a clumsy, time-consuming task that is not easily adaptable to new requirements. In order to tackle this challenge, a proposal on a system used to monitor any conceivable environment, which additionally is able to monitor the status of its own components and heal some of the most usual issues of a Wireless Sensor Network, is presented here in detail, covering all the layers that give it shape in terms of devices, communications or services.

Collaborative Evolution Strategies on Evolvable Hardware Networked Elements

Dynamic and Partial Reconfiguration allows systems to change some parts of their hardware at run time. This feature favours the inclusion of evolutionary strategies to provide optimised solutions to the same problem so that they can be mixed and compared in a way that only the best ones prevail. At the same time, distributed intelligence permits systems to work in a collaborative way to jointly improve their global capabilities. This work presents a combination of both approaches where hardware evolution is performed both at local and network level in order to improve an image filter application in terms of performance, robustness and providing the capacity of avoiding local minimums, which is the main drawback of some evolutionary approaches.

Development of Brain-Computer Interfaces using Evolvable Hardware

Brain-Computer Interfaces are usually tackled from a medical point of view, correlating observed phenomena to physical facts known about the brain. Existing methods of classification lie in the application of deterministic algorithms and depend on certain degree of knowledge about the underlying phenomena so as to process data. In this demo, different architectures for an evolvable hardware classifier implemented on an FPGA are proposed, in line with the objective of generalizing evolutionary algorithms regardless of the application.

Power-Aware Multi-Objective Evolvable Hardware System on an FPGA

Dynamic and Partial Reconfiguration (DPR) allows a system to be able to modify certain parts of itself during run-time. This feature gives rise to the capability of evolution: changing parts of the configuration according to the online evaluation of performance or other parameters. The evolution is achieved through a bio-inspired model in which the features of the system are identified as genes. The objective of the evolution may not be a single one; in this work, power consumption is taken into consideration, together with the quality of filtering, as the measure of performance, of a noisy image. Pareto optimality is applied to the evolutionary process, in order to find a representative set of optimal solutions as for performance and power consumption. The main contributions of this paper are: implementing an evolvable system on a low-power Spartan-6 FPGA included in a Wireless Sensor Network node and, by enabling the availability of a real measure of power consumption at run-time, achieving the capability of multi-objective evolution, that yields different optimal configurations, among which the selected one will depend on the relative “weights” of performance and power consumption.

Algorithms hardware implementation for ultrasonic data processing in SHM system

Nowadays, devices that monitor the health of structures consume a lot of power and need a lot of time to acquire, process, and send the information about the structure to the main processing unit. To decrease this time, fast electronic devices are starting to be used to accelerate this processing. In this paper some hardware algorithms implemented in an electronic logic programming device are described. The goal of this implementation is accelerate the process and diminish the information that has to be send. By reaching this goal, the time the processor needs for treating all the information is reduced and so the power consumption is reduced too.

Distribution of microservices for hardware interoperability in the Smart Grid

Due to the significant increase of population and their natural desire of improving their standard of living, usage of energy extracted from world commodities, especially shaped as electricity, has increased in an intense manner during the last decades. This fact brings up a challenge with a complicated solution, which is how to guarantee that there will be enough energy so as to satisfy the energy demand of the world population. Among all the possible solutions that can be adopted to mitigate this problem one of them is almost of mandatory adoption, which consists of rationalizing energy utilization, in a way that its wasteful usage is minimized and it can be leveraged during a longer period of time. One of the ways to achieve it is by means of the improvement of the power distribution grid, so that it will be able to react in a more efficient manner against common issues, such as energy demand peaks or inaccurate electricity consumption forecasts. However, in order to be able to implement this improvement it is necessary to use technologies from the ICT (Information and Communication Technologies) sphere that often present challenges in some key areas: advanced metering infrastructure integration, interoperability and interconnectivity of the devices, interfaces to offer the applications, security measures design, etc. All these challenges may imply slowing down the adoption of the smart grid as a system to prolong the lifespan and utilization of the available energy. A proposal for an intermediation architecture that will make possible solving these challenges is put forward in this Master Thesis. Besides, one implementation and the tests that have been carried out to know the performance of the presented concepts have been included as well, in a way that it can be proved that the challenges set out by the smart grid can be resolved. RESUMEN. Debido al incremento significativo de la población y su deseo natural de mejorar su nivel de vida, la utilización de la energía extraída de las materias primas mundiales, especialmente en forma de electricidad, ha aumentado de manera intensa durante las últimas décadas. Este hecho plantea un reto de solución complicada, el cual es cómo garantizar que se dispondrá de la energía suficiente como para satisfacer la demanda energética de la población mundial. De entre todas las soluciones posibles que se pueden adoptar para mitigar este problema una de ellas es de casi obligatoria adopción, la cual consiste en racionalizar la utilización de la energía, de tal forma que se minimice su malgasto y pueda aprovecharse durante más tiempo. Una de las maneras de conseguirlo es mediante la mejora de la red de distribución de electricidad para que ésta pueda reaccionar de manera más eficaz contra problemas comunes, tales como los picos de demanda de energía o previsiones imprecisas acerca del consumo de electricidad. Sin embargo, para poder implementar esta mejora es necesario utilizar tecnologías del ámbito de las TIC (Tecnologías de la Información y la Comunicación) que a menudo presentan problemas en algunas áreas clave: integración de infraestructura de medición avanzada, interoperabilidad e interconectividad de los dispositivos, interfaces que ofrecer a las aplicaciones, diseño de medidas de seguridad, etc. Todos estos retos pueden implicar una ralentización en la adopción de la red eléctrica inteligente como un sistema para alargar la vida y la utilización de la energía disponible. En este Trabajo Fin de Máster se sugiere una propuesta para una arquitectura de intermediación que posibilite la resolución de estos retos. Además, una implementación y las pruebas que se han llevado a cabo para conocer el rendimiento de los conceptos presentados también han sido incluidas, de tal forma que se demuestre que los retos que plantea la red eléctrica inteligente pueden ser solventados.