Analysis and Design Considerations of an Electric Vehicle Powertrain regarding Energy Efficiency and Magnetic Field Exposure

En esta tesis se analiza el sistema de tracción de un vehículo eléctrico de batería desde el punto de vista de la eficiencia energética y de la exposición a campos magnéticos por parte de los pasajeros (radiación electromagnética). Este estudio incluye tanto el sistema de almacenamiento de energía como la máquina eléctrica, junto con la electrónica de potencia y los sistemas de control asociados a ambos. Los análisis y los resultados presentados en este texto están basados en modelos matemáticos, simulaciones por ordenador y ensayos experimentales a escala de laboratorio. La investigación llevada a cabo durante esta tesis tuvo siempre un marcado enfoque industrial, a pesar de estar desarrollada en un entorno de considerable carácter universitario. Las líneas de investigación acometidas tuvieron como destinatario final al diseñador y al fabricante del vehículo, a pesar de lo cual algunos de los resultados obtenidos son preliminares y/o excesivamente académicos para resultar de interés industrial. En el ámbito de la eficiencia energética, esta tesis estudia sistemas híbridos de almacenamiento de energía basados en una combinación de baterías de litio y supercondensadores. Este tipo de sistemas son analizados desde el punto de vista de la eficiencia mediante modelos matemáticos y simulaciones, cuantificando el impacto de ésta en otros parámetros tales como el envejecimiento de las baterías. Respecto a la máquina eléctrica, el estudio se ha centrado en máquinas síncronas de imanes permanentes. El análisis de la eficiencia considera tanto el diseño de la máquina como la estrategia de control, dejando parcialmente de lado el inversor y la técnica de modulación (que son incluidos en el estudio como fuentes adicionales de pérdidas, pero no como potenciales fuentes de optimización de la eficiencia). En este sentido, tanto la topología del inversor (trifásico, basado en IGBTs) como la técnica de modulación (control de corriente en banda de histéresis) se establecen desde el principio. El segundo aspecto estudiado en esta tesis es la exposición a campos magnéticos por parte de los pasajeros. Este tema se enfoca desde un punto de vista predictivo, y no desde un punto de vista de diagnóstico, puesto que se ha desarrollado una metodología para estimar el campo magnético generado por los dispositivos de potencia de un vehículo eléctrico. Esta metodología ha sido validada mediante ensayos de laboratorio. Otros aspectos importantes de esta contribución, además de la metodología en sí misma, son las consecuencias que se derivan de ella (por ejemplo, recomendaciones de diseño) y la comprensión del problema proporcionada por esta. Las principales contribuciones de esta tesis se listan a continuación: una recopilación de modelos de pérdidas correspondientes a la mayoría de dispositivos de potencia presentes en un vehículo eléctrico de batería, una metodología para analizar el funcionamiento de un sistema híbrido de almacenamiento de energía para aplicaciones de tracción, una explicación de cómo ponderar energéticamente los puntos de operación par-velocidad de un vehículo eléctrico (de utilidad para evaluar el rendimiento de una máquina eléctrica, por ejemplo), una propuesta de incluir un convertidor DC-DC en el sistema de tracción para minimizar las pérdidas globales del accionamiento (a pesar de las nuevas pérdidas introducidas por el propio DC-DC), una breve comparación entre dos tipos distintos de algoritmos de minimización de pérdidas para máquinas síncronas de imanes permanentes, una metodología predictiva para estimar la exposición a campos magnéticos por parte de los pasajeros de un vehículo eléctrico (debida a los equipos de potencia), y finalmente algunas conclusiones y recomendaciones de diseño respecto a dicha exposición a campos magnéticos. ABSTRACT This dissertation analyzes the powertrain of a battery electric vehicle, focusing on energy efficiency and passenger exposure to electromagnetic fields (electromagnetic radiation). This study comprises the energy storage system as well as the electric machine, along with their associated power electronics and control systems. The analysis and conclusions presented in this dissertation are based on mathematical models, computer simulations and laboratory scale tests. The research performed during this thesis was intended to be of industrial nature, despite being developed in a university. In this sense, the work described in this document was carried out thinking of both the designer and the manufacturer of the vehicle. However, some of the results obtained lack industrial readiness, and therefore they remain utterly academic. Regarding energy efficiency, hybrid energy storage systems consisting in lithium batteries, supercapacitors and up to two DC-DC power converters are considered. These kind of systems are analyzed by means of mathematical models and simulations from the energy efficiency point of view, quantifying its impact on other relevant aspects such as battery aging. Concerning the electric machine, permanent magnet synchronous machines are studied in this work. The energy efficiency analysis comprises the machine design and the control strategy, while the inverter and its modulation technique are taken into account but only as sources of further power losses, and not as potential sources for further efficiency optimization. In this sense, both the inverter topology (3-phase IGBT-based inverter) and the switching technique (hysteresis current control) are fixed from the beginning. The second aspect studied in this work is passenger exposure to magnetic fields. This topic is approached from the prediction point of view, rather than from the diagnosis point of view. In other words, a methodology to estimate the magnetic field generated by the power devices of an electric vehicle is proposed and analyzed in this dissertation. This methodology has been validated by laboratory tests. The most important aspects of this contribution, apart from the methodology itself, are the consequences (for instance, design guidelines) and the understanding of the magnetic radiation issue provided by it. The main contributions of this dissertation are listed next: a compilation of loss models for most of the power devices found in a battery electric vehicle powertrain, a simulation-based methodology to analyze hybrid energy storage performance in traction applications, an explanation of how to assign energy-based weights to different operating points in traction drives (useful when assessing electrical machine performance, for instance), a proposal to include one DC-DC converter in electric powertrains to minimize overall power losses in the system (despite the new losses added by the DC-DC), a brief comparison between two kinds of loss-minimization algorithms for permanent magnet synchronous machines in terms of adaptability and energy efficiency, a predictive methodology to estimate passenger magnetic field exposure due to power devices in an electric vehicle, and finally some useful conclusions and design guidelines concerning magnetic field exposure.

Diffuse Soil Co2 Flux To Assess The Reliability Of Co2 Storage In The Mazarrón-Gañuelas Tertiary Basin (Spain)

Geological storage of CO2 is nowadays internationally considered as the most effective method for greenhouse gas emission mitigation, in order to minimize its effects on the global climatology. One of the main options is to store the CO2 in deep saline aquifers at more than 800 m depth, because it achieves its supercritical state. Among the most important aspects concerning the performance assessment of a deep CO2 geological repository is the evaluation of the CO2 leakage rate from the chosen storage geological formation. Therefore, it is absolutely necessary to increase the knowledge on the interaction among CO2, storage and sealing formations, as well as on the flow paths for CO2 and the physico-mechanical resistance of the sealing formation. Furthermore, the quantification of the CO2 leakage rate is essential to evaluate its effects on the environment. One way to achieve this objective is to study of CO2 leakage on natural analogue systems, because they can provide useful information about the natural performance of the CO2, which can be applied to an artificial CO2 geological storage. This work is focused on the retention capacity of the cap-rock by measuring the diffuse soil CO2 flux in a site selected based on: i) the presence of a natural and deep CO2 accumulation; ii) its structural geological characteristics; and iii) the nature of the cap-rocks. This site is located in the so-called Mazarrón-Gañuelas Tertiary Basin, in the Guadalentin Valley, province of Murcia (Spain) Therefore the main objective of this investigation has been to detect the possible leakages of CO2 from a deep saline aquifer to the surface in order to understand the capability of this area as a natural analogue for Carbon Capture and Sequestration (CCS). The results obtained allow to conclude that the geological sealing formation of the basin seems to be appropriate to avoid CO2 leakages from the storage formation.

Soil fragmentation study applying different tillage systems

Runoff generation depends on rainfall, infiltration, interception, and surface depressional storage. Surface depressional storage depends on surface microtopography, usually quantified trough soil surface roughness (SSR). SSR is subject to spatial and temporal changes that create a high variability. In an agricultural environment, tillage operations produce abrupt changes in roughness. Subsequent rainfall gradually decreases roughness. Beside it, local variation in soil properties and hydrology cause its SSR to vary spatially at different scales. The methods commonly used to measure it involve collecting point elevations in regular grids using laser profilers or scanners, digital close range stereo-photogrammetry and terrestrial laser scanning or LIDAR systems. In this case, a laser-scanning instrument was used to obtain representative digital elevation models (DEMs) at a grid resolution of 7.2x7.2mm that cover an area of 0.9x0.9m. The DEMs were obtained from two study sites with different soils. The first study site was an experimental field on which five conventional tillage methods were applied. The second study site was a large olive orchard with trees planted at 7.5x5.0m and bare soils between rows. Here, three tillage treatments were applied. In this work we have evaluated the spatial variability of SSR at several scales studying differences in height calculated from points separated by incremental distances h were raised to power values q (from 0 to 4 in steps of 0.1). The q = 2 data were studied as a semivariogram model. The logarithm of average differences plotted vs. log h were characterized by their slope, ?(q). Structure functions [?(q) vs. q] were fitted showing that data had nonlinear structure functions typical of multiscale phenomena. Comparisson of the two types of soil in their respective structure functions are shown.

A generic persistence model for CLP systems (and two useful implementations)

This paper describes a model of persistence in (C)LP languages and two different and practically very useful ways to implement this model in current systems. The fundamental idea is that persistence is a characteristic of certain dynamic predicates (Le., those which encapsulate state). The main effect of declaring a predicate persistent is that the dynamic changes made to such predicates persist from one execution to the next one. After proposing a syntax for declaring persistent predicates, a simple, file-based implementation of the concept is presented and some examples shown. An additional implementation is presented which stores persistent predicates in an external datábase. The abstraction of the concept of persistence from its implementation allows developing applications which can store their persistent predicates alternatively in files or databases with only a few simple changes to a declaration stating the location and modality used for persistent storage. The paper presents the model, the implementation approach in both the cases of using files and relational databases, a number of optimizations of the process (using information obtained from static global analysis and goal clustering), and performance results from an implementation of these ideas.

A generic persistence model for CLP systems

This paper describes a model of persistence in (C)LP languages and two different and practically very useful ways to implement this model in current systems. The fundamental idea is that persistence is a characteristic of certain dynamic predicates (i.e., those which encapsulate state). The main effect of declaring a predicate persistent is that the dynamic changes made to such predicates persist from one execution to the next one. After proposing a syntax for declaring persistent predicates, a simple, file-based implementation of the concept is presented and some examples shown. An additional implementation is presented which stores persistent predicates in an external database. The abstraction of the concept of persistence from its implementation allows developing applications which can store their persistent predicates alternatively in files or databases with only a few simple changes to a declaration stating the location and modality used for persistent storage. The paper presents the model, the implementation approach in both the cases of using files and relational databases, a number of optimizations of the process (using information obtained from static global analysis and goal clustering), and performance results from an implementation of these ideas.

Diagnosing Causes of Water Scarcity in Complex Water Resources Systems and Identifying Risk Management Actions

From the water management perspective, water scarcity is an unacceptable risk of facing water shortages to serve water demands in the near future. Water scarcity may be temporary and related to drought conditions or other accidental situation, or may be permanent and due to deeper causes such as excessive demand growth, lack of infrastructure for water storage or transport, or constraints in water management. Diagnosing the causes of water scarcity in complex water resources systems is a precondition to adopt effective drought risk management actions. In this paper we present four indices which have been developed to evaluate water scarcity. We propose a methodology for interpretation of index values that can lead to conclusions about the reliability and vulnerability of systems to water scarcity, as well as to diagnose their possible causes and to propose solutions. The described methodology was applied to the Ebro river basin, identifying existing and expected problems and possible solutions. System diagnostics, based exclusively on the analysis of index values, were compared with the known reality as perceived by system managers, validating the conclusions in all cases

Isozyme systems as markers of genetic deterioration in stored seeds of Brassicaceae species

The main objective of this study was to determine if isozyme systems can be used as markers of genetic deterioration in Brassicaceae seed accessions under different storage conditions. Seed samples of Brassica oleracea, Cardaria draba, Erysimum cheiri, Iberis sempervirens and Rapistrum rugosum were stored for periods of 9 to 30 years at -10°C and 3-4% seed moisture content (long-term or LT conditions) and at 5°C and uncontrolled relative humidity (RH) (short-term or ST conditions). Starch Gel Electrophoresis (SGE) was used to analyse six enzyme systems oriented to determine the genetic deterioration of the accessions studied. The results obtained show that long-term storage conditions (LT) were extremely effective in maintaining the viability of seeds of the five Brassicaceae species studied. The final germination percentages reached by seeds from LT samples ranged from 75 to 100%, while the germination percentages of ST samples (except for B. oleracea) were very low (from 0 to 10%). Similar conclusions were obtained studying the integrity of electrophoretic bands for several isozymes. Two enzyme systems were of special interest: malate dehydrogenase and alcohol dehydrogenase.

Power system stability of a small sized isolated network supplied by a combined wind-pumped storage generation system: a case study in the Canary Islands

Massive integration of renewable energy sources in electrical power systems of remote islands is a subject of current interest. The increasing cost of fossil fuels, transport costs to isolated sites and environmental concerns constitute a serious drawback to the use of conventional fossil fuel plants. In a weak electrical grid, as it is typical on an island, if a large amount of conventional generation is substituted by renewable energy sources, power system safety and stability can be compromised, in the case of large grid disturbances. In this work, a model for transient stability analysis of an isolated electrical grid exclusively fed from a combination of renewable energy sources has been studied. This new generation model will be installed in El Hierro Island, in Spain. Additionally, an operation strategy to coordinate the generation units (wind, hydro) is also established. Attention is given to the assessment of inertial energy and reactive current to guarantee power system stability against large disturbances. The effectiveness of the proposed strategy is shown by means of simulation results.

Scalable Raid Storage Based on the Structure of Multimedia File.

In professional video production, users have to access to huge multimedia files simultaneously in an error-free environment, this restriction force the use of expensive disk architectures for video servers. Previous researches proposed different RAID systems for each specific task (ingest, editing, file, play-out, etc.). Video production companies have to acquire different servers with different RAIDs systems in order to support each task in the production workflow. The solution has multiples disadvantages, duplicated material in several RAIDs, duplicated material for different qualities, transfer and transcoding processes, etc. In this work, an architecture for video servers based on the spreading of JPEG200 data in different RAIDs is presented, each individual part of the data structure goes to a specific RAID type depending on the effect that produces the data on the overall image quality, the method provide a redundancy correlated with the data rank. The global storage can be used in all the different tasks of the production workflow saving disk space, redundant files and transfers procedures.

Data Processing Modeling in Decision Support Systems.

Due to the advancement of both, information technology in general, and databases in particular; data storage devices are becoming cheaper and data processing speed is increasing. As result of this, organizations tend to store large volumes of data holding great potential information. Decision Support Systems, DSS try to use the stored data to obtain valuable information for organizations. In this paper, we use both data models and use cases to represent the functionality of data processing in DSS following Software Engineering processes. We propose a methodology to develop DSS in the Analysis phase, respective of data processing modeling. We have used, as a starting point, a data model adapted to the semantics involved in multidimensional databases or data warehouses, DW. Also, we have taken an algorithm that provides us with all the possible ways to automatically cross check multidimensional model data. Using the aforementioned, we propose diagrams and descriptions of use cases, which can be considered as patterns representing the DSS functionality, in regard to DW data processing, DW on which DSS are based. We highlight the reusability and automation benefits that this can be achieved, and we think this study can serve as a guide in the development of DSS.

Run-Time Scalable Hardware for Reconfigurable Systems

La optimización de parámetros tales como el consumo de potencia, la cantidad de recursos lógicos empleados o la ocupación de memoria ha sido siempre una de las preocupaciones principales a la hora de diseñar sistemas embebidos. Esto es debido a que se trata de sistemas dotados de una cantidad de recursos limitados, y que han sido tradicionalmente empleados para un propósito específico, que permanece invariable a lo largo de toda la vida útil del sistema. Sin embargo, el uso de sistemas embebidos se ha extendido a áreas de aplicación fuera de su ámbito tradicional, caracterizadas por una mayor demanda computacional. Así, por ejemplo, algunos de estos sistemas deben llevar a cabo un intenso procesado de señales multimedia o la transmisión de datos mediante sistemas de comunicaciones de alta capacidad. Por otra parte, las condiciones de operación del sistema pueden variar en tiempo real. Esto sucede, por ejemplo, si su funcionamiento depende de datos medidos por el propio sistema o recibidos a través de la red, de las demandas del usuario en cada momento, o de condiciones internas del propio dispositivo, tales como la duración de la batería. Como consecuencia de la existencia de requisitos de operación dinámicos es necesario ir hacia una gestión dinámica de los recursos del sistema. Si bien el software es inherentemente flexible, no ofrece una potencia computacional tan alta como el hardware. Por lo tanto, el hardware reconfigurable aparece como una solución adecuada para tratar con mayor flexibilidad los requisitos variables dinámicamente en sistemas con alta demanda computacional. La flexibilidad y adaptabilidad del hardware requieren de dispositivos reconfigurables que permitan la modificación de su funcionalidad bajo demanda. En esta tesis se han seleccionado las FPGAs (Field Programmable Gate Arrays) como los dispositivos más apropiados, hoy en día, para implementar sistemas basados en hardware reconfigurable De entre todas las posibilidades existentes para explotar la capacidad de reconfiguración de las FPGAs comerciales, se ha seleccionado la reconfiguración dinámica y parcial. Esta técnica consiste en substituir una parte de la lógica del dispositivo, mientras el resto continúa en funcionamiento. La capacidad de reconfiguración dinámica y parcial de las FPGAs es empleada en esta tesis para tratar con los requisitos de flexibilidad y de capacidad computacional que demandan los dispositivos embebidos. La propuesta principal de esta tesis doctoral es el uso de arquitecturas de procesamiento escalables espacialmente, que son capaces de adaptar su funcionalidad y rendimiento en tiempo real, estableciendo un compromiso entre dichos parámetros y la cantidad de lógica que ocupan en el dispositivo. A esto nos referimos con arquitecturas con huellas escalables. En particular, se propone el uso de arquitecturas altamente paralelas, modulares, regulares y con una alta localidad en sus comunicaciones, para este propósito. El tamaño de dichas arquitecturas puede ser modificado mediante la adición o eliminación de algunos de los módulos que las componen, tanto en una dimensión como en dos. Esta estrategia permite implementar soluciones escalables, sin tener que contar con una versión de las mismas para cada uno de los tamaños posibles de la arquitectura. De esta manera se reduce significativamente el tiempo necesario para modificar su tamaño, así como la cantidad de memoria necesaria para almacenar todos los archivos de configuración. En lugar de proponer arquitecturas para aplicaciones específicas, se ha optado por patrones de procesamiento genéricos, que pueden ser ajustados para solucionar distintos problemas en el estado del arte. A este respecto, se proponen patrones basados en esquemas sistólicos, así como de tipo wavefront. Con el objeto de poder ofrecer una solución integral, se han tratado otros aspectos relacionados con el diseño y el funcionamiento de las arquitecturas, tales como el control del proceso de reconfiguración de la FPGA, la integración de las arquitecturas en el resto del sistema, así como las técnicas necesarias para su implementación. Por lo que respecta a la implementación, se han tratado distintos aspectos de bajo nivel dependientes del dispositivo. Algunas de las propuestas realizadas a este respecto en la presente tesis doctoral son un router que es capaz de garantizar el correcto rutado de los módulos reconfigurables dentro del área destinada para ellos, así como una estrategia para la comunicación entre módulos que no introduce ningún retardo ni necesita emplear recursos configurables del dispositivo. El flujo de diseño propuesto se ha automatizado mediante una herramienta denominada DREAMS. La herramienta se encarga de la modificación de las netlists correspondientes a cada uno de los módulos reconfigurables del sistema, y que han sido generadas previamente mediante herramientas comerciales. Por lo tanto, el flujo propuesto se entiende como una etapa de post-procesamiento, que adapta esas netlists a los requisitos de la reconfiguración dinámica y parcial. Dicha modificación la lleva a cabo la herramienta de una forma completamente automática, por lo que la productividad del proceso de diseño aumenta de forma evidente. Para facilitar dicho proceso, se ha dotado a la herramienta de una interfaz gráfica. El flujo de diseño propuesto, y la herramienta que lo soporta, tienen características específicas para abordar el diseño de las arquitecturas dinámicamente escalables propuestas en esta tesis. Entre ellas está el soporte para el realojamiento de módulos reconfigurables en posiciones del dispositivo distintas a donde el módulo es originalmente implementado, así como la generación de estructuras de comunicación compatibles con la simetría de la arquitectura. El router has sido empleado también en esta tesis para obtener un rutado simétrico entre nets equivalentes. Dicha posibilidad ha sido explotada para aumentar la protección de circuitos con altos requisitos de seguridad, frente a ataques de canal lateral, mediante la implantación de lógica complementaria con rutado idéntico. Para controlar el proceso de reconfiguración de la FPGA, se propone en esta tesis un motor de reconfiguración especialmente adaptado a los requisitos de las arquitecturas dinámicamente escalables. Además de controlar el puerto de reconfiguración, el motor de reconfiguración ha sido dotado de la capacidad de realojar módulos reconfigurables en posiciones arbitrarias del dispositivo, en tiempo real. De esta forma, basta con generar un único bitstream por cada módulo reconfigurable del sistema, independientemente de la posición donde va a ser finalmente reconfigurado. La estrategia seguida para implementar el proceso de realojamiento de módulos es diferente de las propuestas existentes en el estado del arte, pues consiste en la composición de los archivos de configuración en tiempo real. De esta forma se consigue aumentar la velocidad del proceso, mientras que se reduce la longitud de los archivos de configuración parciales a almacenar en el sistema. El motor de reconfiguración soporta módulos reconfigurables con una altura menor que la altura de una región de reloj del dispositivo. Internamente, el motor se encarga de la combinación de los frames que describen el nuevo módulo, con la configuración existente en el dispositivo previamente. El escalado de las arquitecturas de procesamiento propuestas en esta tesis también se puede beneficiar de este mecanismo. Se ha incorporado también un acceso directo a una memoria externa donde se pueden almacenar bitstreams parciales. Para acelerar el proceso de reconfiguración se ha hecho funcionar el ICAP por encima de la máxima frecuencia de reloj aconsejada por el fabricante. Así, en el caso de Virtex-5, aunque la máxima frecuencia del reloj deberían ser 100 MHz, se ha conseguido hacer funcionar el puerto de reconfiguración a frecuencias de operación de hasta 250 MHz, incluyendo el proceso de realojamiento en tiempo real. Se ha previsto la posibilidad de portar el motor de reconfiguración a futuras familias de FPGAs. Por otro lado, el motor de reconfiguración se puede emplear para inyectar fallos en el propio dispositivo hardware, y así ser capaces de evaluar la tolerancia ante los mismos que ofrecen las arquitecturas reconfigurables. Los fallos son emulados mediante la generación de archivos de configuración a los que intencionadamente se les ha introducido un error, de forma que se modifica su funcionalidad. Con el objetivo de comprobar la validez y los beneficios de las arquitecturas propuestas en esta tesis, se han seguido dos líneas principales de aplicación. En primer lugar, se propone su uso como parte de una plataforma adaptativa basada en hardware evolutivo, con capacidad de escalabilidad, adaptabilidad y recuperación ante fallos. En segundo lugar, se ha desarrollado un deblocking filter escalable, adaptado a la codificación de vídeo escalable, como ejemplo de aplicación de las arquitecturas de tipo wavefront propuestas. El hardware evolutivo consiste en el uso de algoritmos evolutivos para diseñar hardware de forma autónoma, explotando la flexibilidad que ofrecen los dispositivos reconfigurables. En este caso, los elementos de procesamiento que componen la arquitectura son seleccionados de una biblioteca de elementos presintetizados, de acuerdo con las decisiones tomadas por el algoritmo evolutivo, en lugar de definir la configuración de las mismas en tiempo de diseño. De esta manera, la configuración del core puede cambiar cuando lo hacen las condiciones del entorno, en tiempo real, por lo que se consigue un control autónomo del proceso de reconfiguración dinámico. Así, el sistema es capaz de optimizar, de forma autónoma, su propia configuración. El hardware evolutivo tiene una capacidad inherente de auto-reparación. Se ha probado que las arquitecturas evolutivas propuestas en esta tesis son tolerantes ante fallos, tanto transitorios, como permanentes y acumulativos. La plataforma evolutiva se ha empleado para implementar filtros de eliminación de ruido. La escalabilidad también ha sido aprovechada en esta aplicación. Las arquitecturas evolutivas escalables permiten la adaptación autónoma de los cores de procesamiento ante fluctuaciones en la cantidad de recursos disponibles en el sistema. Por lo tanto, constituyen un ejemplo de escalabilidad dinámica para conseguir un determinado nivel de calidad, que puede variar en tiempo real. Se han propuesto dos variantes de sistemas escalables evolutivos. El primero consiste en un único core de procesamiento evolutivo, mientras que el segundo está formado por un número variable de arrays de procesamiento. La codificación de vídeo escalable, a diferencia de los codecs no escalables, permite la decodificación de secuencias de vídeo con diferentes niveles de calidad, de resolución temporal o de resolución espacial, descartando la información no deseada. Existen distintos algoritmos que soportan esta característica. En particular, se va a emplear el estándar Scalable Video Coding (SVC), que ha sido propuesto como una extensión de H.264/AVC, ya que este último es ampliamente utilizado tanto en la industria, como a nivel de investigación. Para poder explotar toda la flexibilidad que ofrece el estándar, hay que permitir la adaptación de las características del decodificador en tiempo real. El uso de las arquitecturas dinámicamente escalables es propuesto en esta tesis con este objetivo. El deblocking filter es un algoritmo que tiene como objetivo la mejora de la percepción visual de la imagen reconstruida, mediante el suavizado de los "artefactos" de bloque generados en el lazo del codificador. Se trata de una de las tareas más intensivas en procesamiento de datos de H.264/AVC y de SVC, y además, su carga computacional es altamente dependiente del nivel de escalabilidad seleccionado en el decodificador. Por lo tanto, el deblocking filter ha sido seleccionado como prueba de concepto de la aplicación de las arquitecturas dinámicamente escalables para la compresión de video. La arquitectura propuesta permite añadir o eliminar unidades de computación, siguiendo un esquema de tipo wavefront. La arquitectura ha sido propuesta conjuntamente con un esquema de procesamiento en paralelo del deblocking filter a nivel de macrobloque, de tal forma que cuando se varía del tamaño de la arquitectura, el orden de filtrado de los macrobloques varia de la misma manera. El patrón propuesto se basa en la división del procesamiento de cada macrobloque en dos etapas independientes, que se corresponden con el filtrado horizontal y vertical de los bloques dentro del macrobloque. Las principales contribuciones originales de esta tesis son las siguientes: - El uso de arquitecturas altamente regulares, modulares, paralelas y con una intensa localidad en sus comunicaciones, para implementar cores de procesamiento dinámicamente reconfigurables. - El uso de arquitecturas bidimensionales, en forma de malla, para construir arquitecturas dinámicamente escalables, con una huella escalable. De esta forma, las arquitecturas permiten establecer un compromiso entre el área que ocupan en el dispositivo, y las prestaciones que ofrecen en cada momento. Se proponen plantillas de procesamiento genéricas, de tipo sistólico o wavefront, que pueden ser adaptadas a distintos problemas de procesamiento. - Un flujo de diseño y una herramienta que lo soporta, para el diseño de sistemas reconfigurables dinámicamente, centradas en el diseño de las arquitecturas altamente paralelas, modulares y regulares propuestas en esta tesis. - Un esquema de comunicaciones entre módulos reconfigurables que no introduce ningún retardo ni requiere el uso de recursos lógicos propios. - Un router flexible, capaz de resolver los conflictos de rutado asociados con el diseño de sistemas reconfigurables dinámicamente. - Un algoritmo de optimización para sistemas formados por múltiples cores escalables que optimice, mediante un algoritmo genético, los parámetros de dicho sistema. Se basa en un modelo conocido como el problema de la mochila. - Un motor de reconfiguración adaptado a los requisitos de las arquitecturas altamente regulares y modulares. Combina una alta velocidad de reconfiguración, con la capacidad de realojar módulos en tiempo real, incluyendo el soporte para la reconfiguración de regiones que ocupan menos que una región de reloj, así como la réplica de un módulo reconfigurable en múltiples posiciones del dispositivo. - Un mecanismo de inyección de fallos que, empleando el motor de reconfiguración del sistema, permite evaluar los efectos de fallos permanentes y transitorios en arquitecturas reconfigurables. - La demostración de las posibilidades de las arquitecturas propuestas en esta tesis para la implementación de sistemas de hardware evolutivos, con una alta capacidad de procesamiento de datos. - La implementación de sistemas de hardware evolutivo escalables, que son capaces de tratar con la fluctuación de la cantidad de recursos disponibles en el sistema, de una forma autónoma. - Una estrategia de procesamiento en paralelo para el deblocking filter compatible con los estándares H.264/AVC y SVC que reduce el número de ciclos de macrobloque necesarios para procesar un frame de video. - Una arquitectura dinámicamente escalable que permite la implementación de un nuevo deblocking filter, totalmente compatible con los estándares H.264/AVC y SVC, que explota el paralelismo a nivel de macrobloque. El presente documento se organiza en siete capítulos. En el primero se ofrece una introducción al marco tecnológico de esta tesis, especialmente centrado en la reconfiguración dinámica y parcial de FPGAs. También se motiva la necesidad de las arquitecturas dinámicamente escalables propuestas en esta tesis. En el capítulo 2 se describen las arquitecturas dinámicamente escalables. Dicha descripción incluye la mayor parte de las aportaciones a nivel arquitectural realizadas en esta tesis. Por su parte, el flujo de diseño adaptado a dichas arquitecturas se propone en el capítulo 3. El motor de reconfiguración se propone en el 4, mientras que el uso de dichas arquitecturas para implementar sistemas de hardware evolutivo se aborda en el 5. El deblocking filter escalable se describe en el 6, mientras que las conclusiones finales de esta tesis, así como la descripción del trabajo futuro, son abordadas en el capítulo 7. ABSTRACT The optimization of system parameters, such as power dissipation, the amount of hardware resources and the memory footprint, has been always a main concern when dealing with the design of resource-constrained embedded systems. This situation is even more demanding nowadays. Embedded systems cannot anymore be considered only as specific-purpose computers, designed for a particular functionality that remains unchanged during their lifetime. Differently, embedded systems are now required to deal with more demanding and complex functions, such as multimedia data processing and high-throughput connectivity. In addition, system operation may depend on external data, the user requirements or internal variables of the system, such as the battery life-time. All these conditions may vary at run-time, leading to adaptive scenarios. As a consequence of both the growing computational complexity and the existence of dynamic requirements, dynamic resource management techniques for embedded systems are needed. Software is inherently flexible, but it cannot meet the computing power offered by hardware solutions. Therefore, reconfigurable hardware emerges as a suitable technology to deal with the run-time variable requirements of complex embedded systems. Adaptive hardware requires the use of reconfigurable devices, where its functionality can be modified on demand. In this thesis, Field Programmable Gate Arrays (FPGAs) have been selected as the most appropriate commercial technology existing nowadays to implement adaptive hardware systems. There are different ways of exploiting reconfigurability in reconfigurable devices. Among them is dynamic and partial reconfiguration. This is a technique which consists in substituting part of the FPGA logic on demand, while the rest of the device continues working. The strategy followed in this thesis is to exploit the dynamic and partial reconfiguration of commercial FPGAs to deal with the flexibility and complexity demands of state-of-the-art embedded systems. The proposal of this thesis to deal with run-time variable system conditions is the use of spatially scalable processing hardware IP cores, which are able to adapt their functionality or performance at run-time, trading them off with the amount of logic resources they occupy in the device. This is referred to as a scalable footprint in the context of this thesis. The distinguishing characteristic of the proposed cores is that they rely on highly parallel, modular and regular architectures, arranged in one or two dimensions. These architectures can be scaled by means of the addition or removal of the composing blocks. This strategy avoids implementing a full version of the core for each possible size, with the corresponding benefits in terms of scaling and adaptation time, as well as bitstream storage memory requirements. Instead of providing specific-purpose architectures, generic architectural templates, which can be tuned to solve different problems, are proposed in this thesis. Architectures following both systolic and wavefront templates have been selected. Together with the proposed scalable architectural templates, other issues needed to ensure the proper design and operation of the scalable cores, such as the device reconfiguration control, the run-time management of the architecture and the implementation techniques have been also addressed in this thesis. With regard to the implementation of dynamically reconfigurable architectures, device dependent low-level details are addressed. Some of the aspects covered in this thesis are the area constrained routing for reconfigurable modules, or an inter-module communication strategy which does not introduce either extra delay or logic overhead. The system implementation, from the hardware description to the device configuration bitstream, has been fully automated by modifying the netlists corresponding to each of the system modules, which are previously generated using the vendor tools. This modification is therefore envisaged as a post-processing step. Based on these implementation proposals, a design tool called DREAMS (Dynamically Reconfigurable Embedded and Modular Systems) has been created, including a graphic user interface. The tool has specific features to cope with modular and regular architectures, including the support for module relocation and the inter-module communications scheme based on the symmetry of the architecture. The core of the tool is a custom router, which has been also exploited in this thesis to obtain symmetric routed nets, with the aim of enhancing the protection of critical reconfigurable circuits against side channel attacks. This is achieved by duplicating the logic with an exactly equal routing. In order to control the reconfiguration process of the FPGA, a Reconfiguration Engine suited to the specific requirements set by the proposed architectures was also proposed. Therefore, in addition to controlling the reconfiguration port, the Reconfiguration Engine has been enhanced with the online relocation ability, which allows employing a unique configuration bitstream for all the positions where the module may be placed in the device. Differently to the existing relocating solutions, which are based on bitstream parsers, the proposed approach is based on the online composition of bitstreams. This strategy allows increasing the speed of the process, while the length of partial bitstreams is also reduced. The height of the reconfigurable modules can be lower than the height of a clock region. The Reconfiguration Engine manages the merging process of the new and the existing configuration frames within each clock region. The process of scaling up and down the hardware cores also benefits from this technique. A direct link to an external memory where partial bitstreams can be stored has been also implemented. In order to accelerate the reconfiguration process, the ICAP has been overclocked over the speed reported by the manufacturer. In the case of Virtex-5, even though the maximum frequency of the ICAP is reported to be 100 MHz, valid operations at 250 MHz have been achieved, including the online relocation process. Portability of the reconfiguration solution to today's and probably, future FPGAs, has been also considered. The reconfiguration engine can be also used to inject faults in real hardware devices, and this way being able to evaluate the fault tolerance offered by the reconfigurable architectures. Faults are emulated by introducing partial bitstreams intentionally modified to provide erroneous functionality. To prove the validity and the benefits offered by the proposed architectures, two demonstration application lines have been envisaged. First, scalable architectures have been employed to develop an evolvable hardware platform with adaptability, fault tolerance and scalability properties. Second, they have been used to implement a scalable deblocking filter suited to scalable video coding. Evolvable Hardware is the use of evolutionary algorithms to design hardware in an autonomous way, exploiting the flexibility offered by reconfigurable devices. In this case, processing elements composing the architecture are selected from a presynthesized library of processing elements, according to the decisions taken by the algorithm, instead of being decided at design time. This way, the configuration of the array may change as run-time environmental conditions do, achieving autonomous control of the dynamic reconfiguration process. Thus, the self-optimization property is added to the native self-configurability of the dynamically scalable architectures. In addition, evolvable hardware adaptability inherently offers self-healing features. The proposal has proved to be self-tolerant, since it is able to self-recover from both transient and cumulative permanent faults. The proposed evolvable architecture has been used to implement noise removal image filters. Scalability has been also exploited in this application. Scalable evolvable hardware architectures allow the autonomous adaptation of the processing cores to a fluctuating amount of resources available in the system. Thus, it constitutes an example of the dynamic quality scalability tackled in this thesis. Two variants have been proposed. The first one consists in a single dynamically scalable evolvable core, and the second one contains a variable number of processing cores. Scalable video is a flexible approach for video compression, which offers scalability at different levels. Differently to non-scalable codecs, a scalable video bitstream can be decoded with different levels of quality, spatial or temporal resolutions, by discarding the undesired information. The interest in this technology has been fostered by the development of the Scalable Video Coding (SVC) standard, as an extension of H.264/AVC. In order to exploit all the flexibility offered by the standard, it is necessary to adapt the characteristics of the decoder to the requirements of each client during run-time. The use of dynamically scalable architectures is proposed in this thesis with this aim. The deblocking filter algorithm is the responsible of improving the visual perception of a reconstructed image, by smoothing blocking artifacts generated in the encoding loop. This is one of the most computationally intensive tasks of the standard, and furthermore, it is highly dependent on the selected scalability level in the decoder. Therefore, the deblocking filter has been selected as a proof of concept of the implementation of dynamically scalable architectures for video compression. The proposed architecture allows the run-time addition or removal of computational units working in parallel to change its level of parallelism, following a wavefront computational pattern. Scalable architecture is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, the macroblock filtering order is modified accordingly. The proposed pattern is based on the division of the macroblock processing into two independent stages, corresponding to the horizontal and vertical filtering of the blocks within the macroblock. The main contributions of this thesis are: - The use of highly parallel, modular, regular and local architectures to implement dynamically reconfigurable processing IP cores, for data intensive applications with flexibility requirements. - The use of two-dimensional mesh-type arrays as architectural templates to build dynamically reconfigurable IP cores, with a scalable footprint. The proposal consists in generic architectural templates, which can be tuned to solve different computational problems. •A design flow and a tool targeting the design of DPR systems, focused on highly parallel, modular and local architectures. - An inter-module communication strategy, which does not introduce delay or area overhead, named Virtual Borders. - A custom and flexible router to solve the routing conflicts as well as the inter-module communication problems, appearing during the design of DPR systems. - An algorithm addressing the optimization of systems composed of multiple scalable cores, which size can be decided individually, to optimize the system parameters. It is based on a model known as the multi-dimensional multi-choice Knapsack problem. - A reconfiguration engine tailored to the requirements of highly regular and modular architectures. It combines a high reconfiguration throughput with run-time module relocation capabilities, including the support for sub-clock reconfigurable regions and the replication in multiple positions. - A fault injection mechanism which takes advantage of the system reconfiguration engine, as well as the modularity of the proposed reconfigurable architectures, to evaluate the effects of transient and permanent faults in these architectures. - The demonstration of the possibilities of the architectures proposed in this thesis to implement evolvable hardware systems, while keeping a high processing throughput. - The implementation of scalable evolvable hardware systems, which are able to adapt to the fluctuation of the amount of resources available in the system, in an autonomous way. - A parallelization strategy for the H.264/AVC and SVC deblocking filter, which reduces the number of macroblock cycles needed to process the whole frame. - A dynamically scalable architecture that permits the implementation of a novel deblocking filter module, fully compliant with the H.264/AVC and SVC standards, which exploits the macroblock level parallelism of the algorithm. This document is organized in seven chapters. In the first one, an introduction to the technology framework of this thesis, specially focused on dynamic and partial reconfiguration, is provided. The need for the dynamically scalable processing architectures proposed in this work is also motivated in this chapter. In chapter 2, dynamically scalable architectures are described. Description includes most of the architectural contributions of this work. The design flow tailored to the scalable architectures, together with the DREAMs tool provided to implement them, are described in chapter 3. The reconfiguration engine is described in chapter 4. The use of the proposed scalable archtieectures to implement evolvable hardware systems is described in chapter 5, while the scalable deblocking filter is described in chapter 6. Final conclusions of this thesis, and the description of future work, are addressed in chapter 7.

Domestic hot water consumption vs. solar thermal energy storage: the optimum size of the storage tank

Many efforts have been made in order to adequate the production of a solar thermal collector field to the consumption of domestic hot water of the inhabitants of a building. In that sense, much has been achieved in different domains: research agencies, government policies and manufacturers. However, most of the design rules of the solar plants are based on steady state models, whereas solar irradiance, consumption and thermal accumulation are inherently transient processes. As a result of this lack of physical accuracy, thermal storage tanks are sometimes left to be as large as the designer decides without any aforementioned precise recommendation. This can be a problem if solar thermal systems are meant to be implemented in nowadays buildings, where there is a shortage of space. In addition to that, an excessive storage volume could not result more efficient in many residential applications, but costly, extreme in space consumption and in some cases too heavy. A proprietary transient simulation program has been developed and validated with a detailed measurement campaign in an experimental facility. In situ environmental data have been obtained through a whole year of operation. They have been gathered at intervals of 10 min for a solar plant of 50 m2 with a storage tank of 3 m3, including the equipment for domestic hot water production of a typical apartment building. This program has been used to obtain the design and dimensioning criteria of DHW solar plants under daily transient conditions throughout a year and more specifically the size of the storage tank for a multi storey apartment building. Comparison of the simulation results with the current Spanish regulation applicable, “Código Técnico de la Edificación” (CTE 2006), offers fruitful details and establishes solar facilities dimensioning criteria.

Steady state analysis of a storage integrated solar thermophotovoltaic (SISTPV) system

This paper presents the theoretical analysis of a storage integrated solar thermophotovoltaic (SISTPV) system operating in steady state. These systems combine thermophotovoltaic (TPV) technology and high temperature thermal storage phase-change materials (PCM) in the same unit, providing a great potential in terms of efficiency, cost reduction and storage energy density. The main attraction in the proposed system is its simplicity and modularity compared to conventional Concentrated Solar Power (CSP) technologies. This is mainly due to the absence of moving parts. In this paper we analyze the use of Silicon as the phase change material (PCM). Silicon is an excellent candidate because of its high melting point (1680 K) and its very high latent heat of fusion of 1800 kJ/kg, which is about ten times greater than the conventional PCMs like molten salts. For a simple system configuration, we have demonstrated that overall conversion efficiencies up to ?35% are approachable. Although higher efficiencies are expected by incorporating more advanced devices like multijunction TPV cells, narrow band selective emitters or adopting near-field TPV configurations as well as by enhancing the convective/conductive heat transfer within the PCM. In this paper, we also discuss about the optimum system configurations and provide the general guidelines for designing these systems. Preliminary estimates of night time operations indicate it is possible to achieve over 10 h of operation with a relatively small quantity of Silicon.

Ammonia and Greenhouse Gases Emission from Slurry Storage with impermeable Cover and Landspreading of Cattle Slurry

Intensive farm systems handle large volume of livestock wastes, resulting in adverse environmental effects, such as gaseous losses into the atmosphere in form of ammonia (NH3) and greenhouse gases (GHG), i.e. methane (CH4), carbon dioxide (CO2) and nitrous oxide (N2O). In this study, the manure management continuum of slurry storage with impermeable cover and following cattle slurry band spreading and incorporation to soil was assessed for NH3 and GHG emissions. The experiment was conducted in an outdoor covered storage (flexible bag system) (study I), which collected the slurry produced in 7 dairy cattle farms (2,000 m3 slurry) during 12 days in the northern Spain.

Eventual election of multiple leaders for solving consensus in anonymous systems

In classical distributed systems, each process has a unique identity. Today, new distributed systems have emerged where a unique identity is not always possible to be assigned to each process. For example, in many sensor networks a unique identity is not possible to be included in each device due to its small storage capacity, reduced computational power, or the huge number of devices to be identified. In these cases, we have to work with anonymous distributed systems where processes cannot be identified. Consensus cannot be solved in classical and anonymous asynchronous distributed systems where processes can crash. To bypass this impossibility result, failure detectors are added to these systems. It is known that ? is the weakest failure detector class for solving consensus in classical asynchronous systems when amajority of processes never crashes. Although A? was introduced as an anonymous version of ?, to find the weakest failure detector in anonymous systems to solve consensus when amajority of processes never crashes is nowadays an open question. Furthermore, A? has the important drawback that it is not implementable. Very recently, A? has been introduced as a counterpart of ? for anonymous systems. In this paper, we show that the A? failure detector class is strictly weaker than A? (i.e., A? provides less information about process crashes than A?). We also present in this paper the first implementation of A? (hence, we also show that A? is implementable), and, finally, we include the first implementation of consensus in anonymous asynchronous systems augmented with A? and where a majority of processes does not crash.