37 resultados para feeder reconfiguration


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In order to achieve total selectivity at electrical distribution networks it is of great importance to analyze the defect currents at ungrounded power systems. This information will help to grant selectivity at electrical distribution networks ensuring that only the defect line or feeder is removed from service. In the present work a new selective and directional protection method for ungrounded power systems is evaluated. The new method measures only defect currents to detect earth faults and works with a directional criterion to determine the line under faulty conditions. The main contribution of this new technique is that it can detect earth faults in outgoing lines at any type of substation avoiding the possible mismatch of traditional directional earth fault relays. This detection technique is based on the comparison of the direction of a reference current to the direction of all earth fault capacitive currents at all the feeders connected to the same bus bars. This new method has been validated through computer simulations. The results for the different cases studied are remarkable, proving total validity and usefulness of the new method.

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In this work, the power management techniques implemented in a high-performance node for Wireless Sensor Networks (WSN) based on a RAM-based FPGA are presented. This new node custom architecture is intended for high-end WSN applications that include complex sensor management like video cameras, high compute demanding tasks such as image encoding or robust encryption, and/or higher data bandwidth needs. In the case of these complex processing tasks, yet maintaining low power design requirements, it can be shown that the combination of different techniques such as extensive HW algorithm mapping, smart management of power islands to selectively switch on and off components, smart and low-energy partial reconfiguration, an adequate set of save energy modes and wake up options, all combined, may yield energy results that may compete and improve energy usage of typical low power microcontrollers used in many WSN node architectures. Actually, results show that higher complexity tasks are in favor of HW based platforms, while the flexibility achieved by dynamic and partial reconfiguration techniques could be comparable to SW based solutions.

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La optimización de parámetros tales como el consumo de potencia, la cantidad de recursos lógicos empleados o la ocupación de memoria ha sido siempre una de las preocupaciones principales a la hora de diseñar sistemas embebidos. Esto es debido a que se trata de sistemas dotados de una cantidad de recursos limitados, y que han sido tradicionalmente empleados para un propósito específico, que permanece invariable a lo largo de toda la vida útil del sistema. Sin embargo, el uso de sistemas embebidos se ha extendido a áreas de aplicación fuera de su ámbito tradicional, caracterizadas por una mayor demanda computacional. Así, por ejemplo, algunos de estos sistemas deben llevar a cabo un intenso procesado de señales multimedia o la transmisión de datos mediante sistemas de comunicaciones de alta capacidad. Por otra parte, las condiciones de operación del sistema pueden variar en tiempo real. Esto sucede, por ejemplo, si su funcionamiento depende de datos medidos por el propio sistema o recibidos a través de la red, de las demandas del usuario en cada momento, o de condiciones internas del propio dispositivo, tales como la duración de la batería. Como consecuencia de la existencia de requisitos de operación dinámicos es necesario ir hacia una gestión dinámica de los recursos del sistema. Si bien el software es inherentemente flexible, no ofrece una potencia computacional tan alta como el hardware. Por lo tanto, el hardware reconfigurable aparece como una solución adecuada para tratar con mayor flexibilidad los requisitos variables dinámicamente en sistemas con alta demanda computacional. La flexibilidad y adaptabilidad del hardware requieren de dispositivos reconfigurables que permitan la modificación de su funcionalidad bajo demanda. En esta tesis se han seleccionado las FPGAs (Field Programmable Gate Arrays) como los dispositivos más apropiados, hoy en día, para implementar sistemas basados en hardware reconfigurable De entre todas las posibilidades existentes para explotar la capacidad de reconfiguración de las FPGAs comerciales, se ha seleccionado la reconfiguración dinámica y parcial. Esta técnica consiste en substituir una parte de la lógica del dispositivo, mientras el resto continúa en funcionamiento. La capacidad de reconfiguración dinámica y parcial de las FPGAs es empleada en esta tesis para tratar con los requisitos de flexibilidad y de capacidad computacional que demandan los dispositivos embebidos. La propuesta principal de esta tesis doctoral es el uso de arquitecturas de procesamiento escalables espacialmente, que son capaces de adaptar su funcionalidad y rendimiento en tiempo real, estableciendo un compromiso entre dichos parámetros y la cantidad de lógica que ocupan en el dispositivo. A esto nos referimos con arquitecturas con huellas escalables. En particular, se propone el uso de arquitecturas altamente paralelas, modulares, regulares y con una alta localidad en sus comunicaciones, para este propósito. El tamaño de dichas arquitecturas puede ser modificado mediante la adición o eliminación de algunos de los módulos que las componen, tanto en una dimensión como en dos. Esta estrategia permite implementar soluciones escalables, sin tener que contar con una versión de las mismas para cada uno de los tamaños posibles de la arquitectura. De esta manera se reduce significativamente el tiempo necesario para modificar su tamaño, así como la cantidad de memoria necesaria para almacenar todos los archivos de configuración. En lugar de proponer arquitecturas para aplicaciones específicas, se ha optado por patrones de procesamiento genéricos, que pueden ser ajustados para solucionar distintos problemas en el estado del arte. A este respecto, se proponen patrones basados en esquemas sistólicos, así como de tipo wavefront. Con el objeto de poder ofrecer una solución integral, se han tratado otros aspectos relacionados con el diseño y el funcionamiento de las arquitecturas, tales como el control del proceso de reconfiguración de la FPGA, la integración de las arquitecturas en el resto del sistema, así como las técnicas necesarias para su implementación. Por lo que respecta a la implementación, se han tratado distintos aspectos de bajo nivel dependientes del dispositivo. Algunas de las propuestas realizadas a este respecto en la presente tesis doctoral son un router que es capaz de garantizar el correcto rutado de los módulos reconfigurables dentro del área destinada para ellos, así como una estrategia para la comunicación entre módulos que no introduce ningún retardo ni necesita emplear recursos configurables del dispositivo. El flujo de diseño propuesto se ha automatizado mediante una herramienta denominada DREAMS. La herramienta se encarga de la modificación de las netlists correspondientes a cada uno de los módulos reconfigurables del sistema, y que han sido generadas previamente mediante herramientas comerciales. Por lo tanto, el flujo propuesto se entiende como una etapa de post-procesamiento, que adapta esas netlists a los requisitos de la reconfiguración dinámica y parcial. Dicha modificación la lleva a cabo la herramienta de una forma completamente automática, por lo que la productividad del proceso de diseño aumenta de forma evidente. Para facilitar dicho proceso, se ha dotado a la herramienta de una interfaz gráfica. El flujo de diseño propuesto, y la herramienta que lo soporta, tienen características específicas para abordar el diseño de las arquitecturas dinámicamente escalables propuestas en esta tesis. Entre ellas está el soporte para el realojamiento de módulos reconfigurables en posiciones del dispositivo distintas a donde el módulo es originalmente implementado, así como la generación de estructuras de comunicación compatibles con la simetría de la arquitectura. El router has sido empleado también en esta tesis para obtener un rutado simétrico entre nets equivalentes. Dicha posibilidad ha sido explotada para aumentar la protección de circuitos con altos requisitos de seguridad, frente a ataques de canal lateral, mediante la implantación de lógica complementaria con rutado idéntico. Para controlar el proceso de reconfiguración de la FPGA, se propone en esta tesis un motor de reconfiguración especialmente adaptado a los requisitos de las arquitecturas dinámicamente escalables. Además de controlar el puerto de reconfiguración, el motor de reconfiguración ha sido dotado de la capacidad de realojar módulos reconfigurables en posiciones arbitrarias del dispositivo, en tiempo real. De esta forma, basta con generar un único bitstream por cada módulo reconfigurable del sistema, independientemente de la posición donde va a ser finalmente reconfigurado. La estrategia seguida para implementar el proceso de realojamiento de módulos es diferente de las propuestas existentes en el estado del arte, pues consiste en la composición de los archivos de configuración en tiempo real. De esta forma se consigue aumentar la velocidad del proceso, mientras que se reduce la longitud de los archivos de configuración parciales a almacenar en el sistema. El motor de reconfiguración soporta módulos reconfigurables con una altura menor que la altura de una región de reloj del dispositivo. Internamente, el motor se encarga de la combinación de los frames que describen el nuevo módulo, con la configuración existente en el dispositivo previamente. El escalado de las arquitecturas de procesamiento propuestas en esta tesis también se puede beneficiar de este mecanismo. Se ha incorporado también un acceso directo a una memoria externa donde se pueden almacenar bitstreams parciales. Para acelerar el proceso de reconfiguración se ha hecho funcionar el ICAP por encima de la máxima frecuencia de reloj aconsejada por el fabricante. Así, en el caso de Virtex-5, aunque la máxima frecuencia del reloj deberían ser 100 MHz, se ha conseguido hacer funcionar el puerto de reconfiguración a frecuencias de operación de hasta 250 MHz, incluyendo el proceso de realojamiento en tiempo real. Se ha previsto la posibilidad de portar el motor de reconfiguración a futuras familias de FPGAs. Por otro lado, el motor de reconfiguración se puede emplear para inyectar fallos en el propio dispositivo hardware, y así ser capaces de evaluar la tolerancia ante los mismos que ofrecen las arquitecturas reconfigurables. Los fallos son emulados mediante la generación de archivos de configuración a los que intencionadamente se les ha introducido un error, de forma que se modifica su funcionalidad. Con el objetivo de comprobar la validez y los beneficios de las arquitecturas propuestas en esta tesis, se han seguido dos líneas principales de aplicación. En primer lugar, se propone su uso como parte de una plataforma adaptativa basada en hardware evolutivo, con capacidad de escalabilidad, adaptabilidad y recuperación ante fallos. En segundo lugar, se ha desarrollado un deblocking filter escalable, adaptado a la codificación de vídeo escalable, como ejemplo de aplicación de las arquitecturas de tipo wavefront propuestas. El hardware evolutivo consiste en el uso de algoritmos evolutivos para diseñar hardware de forma autónoma, explotando la flexibilidad que ofrecen los dispositivos reconfigurables. En este caso, los elementos de procesamiento que componen la arquitectura son seleccionados de una biblioteca de elementos presintetizados, de acuerdo con las decisiones tomadas por el algoritmo evolutivo, en lugar de definir la configuración de las mismas en tiempo de diseño. De esta manera, la configuración del core puede cambiar cuando lo hacen las condiciones del entorno, en tiempo real, por lo que se consigue un control autónomo del proceso de reconfiguración dinámico. Así, el sistema es capaz de optimizar, de forma autónoma, su propia configuración. El hardware evolutivo tiene una capacidad inherente de auto-reparación. Se ha probado que las arquitecturas evolutivas propuestas en esta tesis son tolerantes ante fallos, tanto transitorios, como permanentes y acumulativos. La plataforma evolutiva se ha empleado para implementar filtros de eliminación de ruido. La escalabilidad también ha sido aprovechada en esta aplicación. Las arquitecturas evolutivas escalables permiten la adaptación autónoma de los cores de procesamiento ante fluctuaciones en la cantidad de recursos disponibles en el sistema. Por lo tanto, constituyen un ejemplo de escalabilidad dinámica para conseguir un determinado nivel de calidad, que puede variar en tiempo real. Se han propuesto dos variantes de sistemas escalables evolutivos. El primero consiste en un único core de procesamiento evolutivo, mientras que el segundo está formado por un número variable de arrays de procesamiento. La codificación de vídeo escalable, a diferencia de los codecs no escalables, permite la decodificación de secuencias de vídeo con diferentes niveles de calidad, de resolución temporal o de resolución espacial, descartando la información no deseada. Existen distintos algoritmos que soportan esta característica. En particular, se va a emplear el estándar Scalable Video Coding (SVC), que ha sido propuesto como una extensión de H.264/AVC, ya que este último es ampliamente utilizado tanto en la industria, como a nivel de investigación. Para poder explotar toda la flexibilidad que ofrece el estándar, hay que permitir la adaptación de las características del decodificador en tiempo real. El uso de las arquitecturas dinámicamente escalables es propuesto en esta tesis con este objetivo. El deblocking filter es un algoritmo que tiene como objetivo la mejora de la percepción visual de la imagen reconstruida, mediante el suavizado de los "artefactos" de bloque generados en el lazo del codificador. Se trata de una de las tareas más intensivas en procesamiento de datos de H.264/AVC y de SVC, y además, su carga computacional es altamente dependiente del nivel de escalabilidad seleccionado en el decodificador. Por lo tanto, el deblocking filter ha sido seleccionado como prueba de concepto de la aplicación de las arquitecturas dinámicamente escalables para la compresión de video. La arquitectura propuesta permite añadir o eliminar unidades de computación, siguiendo un esquema de tipo wavefront. La arquitectura ha sido propuesta conjuntamente con un esquema de procesamiento en paralelo del deblocking filter a nivel de macrobloque, de tal forma que cuando se varía del tamaño de la arquitectura, el orden de filtrado de los macrobloques varia de la misma manera. El patrón propuesto se basa en la división del procesamiento de cada macrobloque en dos etapas independientes, que se corresponden con el filtrado horizontal y vertical de los bloques dentro del macrobloque. Las principales contribuciones originales de esta tesis son las siguientes: - El uso de arquitecturas altamente regulares, modulares, paralelas y con una intensa localidad en sus comunicaciones, para implementar cores de procesamiento dinámicamente reconfigurables. - El uso de arquitecturas bidimensionales, en forma de malla, para construir arquitecturas dinámicamente escalables, con una huella escalable. De esta forma, las arquitecturas permiten establecer un compromiso entre el área que ocupan en el dispositivo, y las prestaciones que ofrecen en cada momento. Se proponen plantillas de procesamiento genéricas, de tipo sistólico o wavefront, que pueden ser adaptadas a distintos problemas de procesamiento. - Un flujo de diseño y una herramienta que lo soporta, para el diseño de sistemas reconfigurables dinámicamente, centradas en el diseño de las arquitecturas altamente paralelas, modulares y regulares propuestas en esta tesis. - Un esquema de comunicaciones entre módulos reconfigurables que no introduce ningún retardo ni requiere el uso de recursos lógicos propios. - Un router flexible, capaz de resolver los conflictos de rutado asociados con el diseño de sistemas reconfigurables dinámicamente. - Un algoritmo de optimización para sistemas formados por múltiples cores escalables que optimice, mediante un algoritmo genético, los parámetros de dicho sistema. Se basa en un modelo conocido como el problema de la mochila. - Un motor de reconfiguración adaptado a los requisitos de las arquitecturas altamente regulares y modulares. Combina una alta velocidad de reconfiguración, con la capacidad de realojar módulos en tiempo real, incluyendo el soporte para la reconfiguración de regiones que ocupan menos que una región de reloj, así como la réplica de un módulo reconfigurable en múltiples posiciones del dispositivo. - Un mecanismo de inyección de fallos que, empleando el motor de reconfiguración del sistema, permite evaluar los efectos de fallos permanentes y transitorios en arquitecturas reconfigurables. - La demostración de las posibilidades de las arquitecturas propuestas en esta tesis para la implementación de sistemas de hardware evolutivos, con una alta capacidad de procesamiento de datos. - La implementación de sistemas de hardware evolutivo escalables, que son capaces de tratar con la fluctuación de la cantidad de recursos disponibles en el sistema, de una forma autónoma. - Una estrategia de procesamiento en paralelo para el deblocking filter compatible con los estándares H.264/AVC y SVC que reduce el número de ciclos de macrobloque necesarios para procesar un frame de video. - Una arquitectura dinámicamente escalable que permite la implementación de un nuevo deblocking filter, totalmente compatible con los estándares H.264/AVC y SVC, que explota el paralelismo a nivel de macrobloque. El presente documento se organiza en siete capítulos. En el primero se ofrece una introducción al marco tecnológico de esta tesis, especialmente centrado en la reconfiguración dinámica y parcial de FPGAs. También se motiva la necesidad de las arquitecturas dinámicamente escalables propuestas en esta tesis. En el capítulo 2 se describen las arquitecturas dinámicamente escalables. Dicha descripción incluye la mayor parte de las aportaciones a nivel arquitectural realizadas en esta tesis. Por su parte, el flujo de diseño adaptado a dichas arquitecturas se propone en el capítulo 3. El motor de reconfiguración se propone en el 4, mientras que el uso de dichas arquitecturas para implementar sistemas de hardware evolutivo se aborda en el 5. El deblocking filter escalable se describe en el 6, mientras que las conclusiones finales de esta tesis, así como la descripción del trabajo futuro, son abordadas en el capítulo 7. ABSTRACT The optimization of system parameters, such as power dissipation, the amount of hardware resources and the memory footprint, has been always a main concern when dealing with the design of resource-constrained embedded systems. This situation is even more demanding nowadays. Embedded systems cannot anymore be considered only as specific-purpose computers, designed for a particular functionality that remains unchanged during their lifetime. Differently, embedded systems are now required to deal with more demanding and complex functions, such as multimedia data processing and high-throughput connectivity. In addition, system operation may depend on external data, the user requirements or internal variables of the system, such as the battery life-time. All these conditions may vary at run-time, leading to adaptive scenarios. As a consequence of both the growing computational complexity and the existence of dynamic requirements, dynamic resource management techniques for embedded systems are needed. Software is inherently flexible, but it cannot meet the computing power offered by hardware solutions. Therefore, reconfigurable hardware emerges as a suitable technology to deal with the run-time variable requirements of complex embedded systems. Adaptive hardware requires the use of reconfigurable devices, where its functionality can be modified on demand. In this thesis, Field Programmable Gate Arrays (FPGAs) have been selected as the most appropriate commercial technology existing nowadays to implement adaptive hardware systems. There are different ways of exploiting reconfigurability in reconfigurable devices. Among them is dynamic and partial reconfiguration. This is a technique which consists in substituting part of the FPGA logic on demand, while the rest of the device continues working. The strategy followed in this thesis is to exploit the dynamic and partial reconfiguration of commercial FPGAs to deal with the flexibility and complexity demands of state-of-the-art embedded systems. The proposal of this thesis to deal with run-time variable system conditions is the use of spatially scalable processing hardware IP cores, which are able to adapt their functionality or performance at run-time, trading them off with the amount of logic resources they occupy in the device. This is referred to as a scalable footprint in the context of this thesis. The distinguishing characteristic of the proposed cores is that they rely on highly parallel, modular and regular architectures, arranged in one or two dimensions. These architectures can be scaled by means of the addition or removal of the composing blocks. This strategy avoids implementing a full version of the core for each possible size, with the corresponding benefits in terms of scaling and adaptation time, as well as bitstream storage memory requirements. Instead of providing specific-purpose architectures, generic architectural templates, which can be tuned to solve different problems, are proposed in this thesis. Architectures following both systolic and wavefront templates have been selected. Together with the proposed scalable architectural templates, other issues needed to ensure the proper design and operation of the scalable cores, such as the device reconfiguration control, the run-time management of the architecture and the implementation techniques have been also addressed in this thesis. With regard to the implementation of dynamically reconfigurable architectures, device dependent low-level details are addressed. Some of the aspects covered in this thesis are the area constrained routing for reconfigurable modules, or an inter-module communication strategy which does not introduce either extra delay or logic overhead. The system implementation, from the hardware description to the device configuration bitstream, has been fully automated by modifying the netlists corresponding to each of the system modules, which are previously generated using the vendor tools. This modification is therefore envisaged as a post-processing step. Based on these implementation proposals, a design tool called DREAMS (Dynamically Reconfigurable Embedded and Modular Systems) has been created, including a graphic user interface. The tool has specific features to cope with modular and regular architectures, including the support for module relocation and the inter-module communications scheme based on the symmetry of the architecture. The core of the tool is a custom router, which has been also exploited in this thesis to obtain symmetric routed nets, with the aim of enhancing the protection of critical reconfigurable circuits against side channel attacks. This is achieved by duplicating the logic with an exactly equal routing. In order to control the reconfiguration process of the FPGA, a Reconfiguration Engine suited to the specific requirements set by the proposed architectures was also proposed. Therefore, in addition to controlling the reconfiguration port, the Reconfiguration Engine has been enhanced with the online relocation ability, which allows employing a unique configuration bitstream for all the positions where the module may be placed in the device. Differently to the existing relocating solutions, which are based on bitstream parsers, the proposed approach is based on the online composition of bitstreams. This strategy allows increasing the speed of the process, while the length of partial bitstreams is also reduced. The height of the reconfigurable modules can be lower than the height of a clock region. The Reconfiguration Engine manages the merging process of the new and the existing configuration frames within each clock region. The process of scaling up and down the hardware cores also benefits from this technique. A direct link to an external memory where partial bitstreams can be stored has been also implemented. In order to accelerate the reconfiguration process, the ICAP has been overclocked over the speed reported by the manufacturer. In the case of Virtex-5, even though the maximum frequency of the ICAP is reported to be 100 MHz, valid operations at 250 MHz have been achieved, including the online relocation process. Portability of the reconfiguration solution to today's and probably, future FPGAs, has been also considered. The reconfiguration engine can be also used to inject faults in real hardware devices, and this way being able to evaluate the fault tolerance offered by the reconfigurable architectures. Faults are emulated by introducing partial bitstreams intentionally modified to provide erroneous functionality. To prove the validity and the benefits offered by the proposed architectures, two demonstration application lines have been envisaged. First, scalable architectures have been employed to develop an evolvable hardware platform with adaptability, fault tolerance and scalability properties. Second, they have been used to implement a scalable deblocking filter suited to scalable video coding. Evolvable Hardware is the use of evolutionary algorithms to design hardware in an autonomous way, exploiting the flexibility offered by reconfigurable devices. In this case, processing elements composing the architecture are selected from a presynthesized library of processing elements, according to the decisions taken by the algorithm, instead of being decided at design time. This way, the configuration of the array may change as run-time environmental conditions do, achieving autonomous control of the dynamic reconfiguration process. Thus, the self-optimization property is added to the native self-configurability of the dynamically scalable architectures. In addition, evolvable hardware adaptability inherently offers self-healing features. The proposal has proved to be self-tolerant, since it is able to self-recover from both transient and cumulative permanent faults. The proposed evolvable architecture has been used to implement noise removal image filters. Scalability has been also exploited in this application. Scalable evolvable hardware architectures allow the autonomous adaptation of the processing cores to a fluctuating amount of resources available in the system. Thus, it constitutes an example of the dynamic quality scalability tackled in this thesis. Two variants have been proposed. The first one consists in a single dynamically scalable evolvable core, and the second one contains a variable number of processing cores. Scalable video is a flexible approach for video compression, which offers scalability at different levels. Differently to non-scalable codecs, a scalable video bitstream can be decoded with different levels of quality, spatial or temporal resolutions, by discarding the undesired information. The interest in this technology has been fostered by the development of the Scalable Video Coding (SVC) standard, as an extension of H.264/AVC. In order to exploit all the flexibility offered by the standard, it is necessary to adapt the characteristics of the decoder to the requirements of each client during run-time. The use of dynamically scalable architectures is proposed in this thesis with this aim. The deblocking filter algorithm is the responsible of improving the visual perception of a reconstructed image, by smoothing blocking artifacts generated in the encoding loop. This is one of the most computationally intensive tasks of the standard, and furthermore, it is highly dependent on the selected scalability level in the decoder. Therefore, the deblocking filter has been selected as a proof of concept of the implementation of dynamically scalable architectures for video compression. The proposed architecture allows the run-time addition or removal of computational units working in parallel to change its level of parallelism, following a wavefront computational pattern. Scalable architecture is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, the macroblock filtering order is modified accordingly. The proposed pattern is based on the division of the macroblock processing into two independent stages, corresponding to the horizontal and vertical filtering of the blocks within the macroblock. The main contributions of this thesis are: - The use of highly parallel, modular, regular and local architectures to implement dynamically reconfigurable processing IP cores, for data intensive applications with flexibility requirements. - The use of two-dimensional mesh-type arrays as architectural templates to build dynamically reconfigurable IP cores, with a scalable footprint. The proposal consists in generic architectural templates, which can be tuned to solve different computational problems. •A design flow and a tool targeting the design of DPR systems, focused on highly parallel, modular and local architectures. - An inter-module communication strategy, which does not introduce delay or area overhead, named Virtual Borders. - A custom and flexible router to solve the routing conflicts as well as the inter-module communication problems, appearing during the design of DPR systems. - An algorithm addressing the optimization of systems composed of multiple scalable cores, which size can be decided individually, to optimize the system parameters. It is based on a model known as the multi-dimensional multi-choice Knapsack problem. - A reconfiguration engine tailored to the requirements of highly regular and modular architectures. It combines a high reconfiguration throughput with run-time module relocation capabilities, including the support for sub-clock reconfigurable regions and the replication in multiple positions. - A fault injection mechanism which takes advantage of the system reconfiguration engine, as well as the modularity of the proposed reconfigurable architectures, to evaluate the effects of transient and permanent faults in these architectures. - The demonstration of the possibilities of the architectures proposed in this thesis to implement evolvable hardware systems, while keeping a high processing throughput. - The implementation of scalable evolvable hardware systems, which are able to adapt to the fluctuation of the amount of resources available in the system, in an autonomous way. - A parallelization strategy for the H.264/AVC and SVC deblocking filter, which reduces the number of macroblock cycles needed to process the whole frame. - A dynamically scalable architecture that permits the implementation of a novel deblocking filter module, fully compliant with the H.264/AVC and SVC standards, which exploits the macroblock level parallelism of the algorithm. This document is organized in seven chapters. In the first one, an introduction to the technology framework of this thesis, specially focused on dynamic and partial reconfiguration, is provided. The need for the dynamically scalable processing architectures proposed in this work is also motivated in this chapter. In chapter 2, dynamically scalable architectures are described. Description includes most of the architectural contributions of this work. The design flow tailored to the scalable architectures, together with the DREAMs tool provided to implement them, are described in chapter 3. The reconfiguration engine is described in chapter 4. The use of the proposed scalable archtieectures to implement evolvable hardware systems is described in chapter 5, while the scalable deblocking filter is described in chapter 6. Final conclusions of this thesis, and the description of future work, are addressed in chapter 7.

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The objective of this study was to build up a data set including productive performance and production factors data of growing-finishing (GF) pigs in Spain in order to perform a representative and reliable description of the traits of Spanish growing-finishing pig industry. Data from 764 batches from 452 farms belonging to nine companies (1,157,212 pigs) were collected between 2008 and 2010 through a survey including five parts: general, facilities, feeding, health status and performance. Most studied farms had only GF pigs on their facilities (94.7%), produced ‘industrial’ pigs (86.7%), had entire male and female (59.5%) and Pietrain-sired pigs (70.0%), housed between 13-20 pigs per pen (87.2%), had  50% of slatted floor (70%), single-space dry feeder (54.0%), nipple drinker (88.7%) and automatic ventilation systems (71.2%). A 75.0% of the farms used three feeding phases using mainly pelleted diets (91.0%), 61.3% performed three or more antibiotic treatments and 36.5% obtained water from the public supply. Continuous variables studied had the following average values: number of pigs placed per batch, 1,515 pigs; initial and final body weight, 19.0 and 108 kg; length of GF period, 136 days; culling rate, 1.4%; barn occupation, 99.7%; feed intake per pig and fattening cycle, 244 kg; daily gain, 0.657 kg; feed conversion ratio, 2.77 kg kg-1 and mortality rate, 4.3%. Data reflecting the practical situation of the Spanish growing and finishing pig production and it may contribute to develop new strategies in order to improve the productive and economic efficiency of GF pig units.

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With the advent of cloud computing model, distributed caches have become the cornerstone for building scalable applications. Popular systems like Facebook [1] or Twitter use Memcached [5], a highly scalable distributed object cache, to speed up applications by avoiding database accesses. Distributed object caches assign objects to cache instances based on a hashing function, and objects are not moved from a cache instance to another unless more instances are added to the cache and objects are redistributed. This may lead to situations where some cache instances are overloaded when some of the objects they store are frequently accessed, while other cache instances are less frequently used. In this paper we propose a multi-resource load balancing algorithm for distributed cache systems. The algorithm aims at balancing both CPU and Memory resources among cache instances by redistributing stored data. Considering the possible conflict of balancing multiple resources at the same time, we give CPU and Memory resources weighted priorities based on the runtime load distributions. A scarcer resource is given a higher weight than a less scarce resource when load balancing. The system imbalance degree is evaluated based on monitoring information, and the utility load of a node, a unit for resource consumption. Besides, since continuous rebalance of the system may affect the QoS of applications utilizing the cache system, our data selection policy ensures that each data migration minimizes the system imbalance degree and hence, the total reconfiguration cost can be minimized. An extensive simulation is conducted to compare our policy with other policies. Our policy shows a significant improvement in time efficiency and decrease in reconfiguration cost.

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One of the main concerns of evolvable and adaptive systems is the need of a training mechanism, which is normally done by using a training reference and a test input. The fitness function to be optimized during the evolution (training) phase is obtained by comparing the output of the candidate systems against the reference. The adaptivity that this type of systems may provide by re-evolving during operation is especially important for applications with runtime variable conditions. However, fully automated self-adaptivity poses additional problems. For instance, in some cases, it is not possible to have such reference, because the changes in the environment conditions are unknown, so it becomes difficult to autonomously identify which problem requires to be solved, and hence, what conditions should be representative for an adequate re-evolution. In this paper, a solution to solve this dependency is presented and analyzed. The system consists of an image filter application mapped on an evolvable hardware platform, able to evolve using two consecutive frames from a camera as both test and reference images. The system is entirely mapped in an FPGA, and native dynamic and partial reconfiguration is used for evolution. It is also shown that using such images, both of them being noisy, as input and reference images in the evolution phase of the system is equivalent or even better than evolving the filter with offline images. The combination of both techniques results in the completely autonomous, noise type/level agnostic filtering system without reference image requirement described along the paper.

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Evolvable Hardware (EH) is a technique that consists of using reconfigurable hardware devices whose configuration is controlled by an Evolutionary Algorithm (EA). Our system consists of a fully-FPGA implemented scalable EH platform, where the Reconfigurable processing Core (RC) can adaptively increase or decrease in size. Figure 1 shows the architecture of the proposed System-on-Programmable-Chip (SoPC), consisting of a MicroBlaze processor responsible of controlling the whole system operation, a Reconfiguration Engine (RE), and a Reconfigurable processing Core which is able to change its size in both height and width. This system is used to implement image filters, which are generated autonomously thanks to the evolutionary process. The system is complemented with a camera that enables the usage of the platform for real time applications.

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In this paper, an architecture based on a scalable and flexible set of Evolvable Processing arrays is presented. FPGA-native Dynamic Partial Reconfiguration (DPR) is used for evolution, which is done intrinsically, letting the system to adapt autonomously to variable run-time conditions, including the presence of transient and permanent faults. The architecture supports different modes of operation, namely: independent, parallel, cascaded or bypass mode. These modes of operation can be used during evolution time or during normal operation. The evolvability of the architecture is combined with fault-tolerance techniques, to enhance the platform with self-healing features, making it suitable for applications which require both high adaptability and reliability. Experimental results show that such a system may benefit from accelerated evolution times, increased performance and improved dependability, mainly by increasing fault tolerance for transient and permanent faults, as well as providing some fault identification possibilities. The evolvable HW array shown is tailored for window-based image processing applications.

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While for years traditional wireless sensor nodes have been based on ultra-low power microcontrollers with sufficient but limited computing power, the complexity and number of tasks of today’s applications are constantly increasing. Increasing the node duty cycle is not feasible in all cases, so in many cases more computing power is required. This extra computing power may be achieved by either more powerful microcontrollers, though more power consumption or, in general, any solution capable of accelerating task execution. At this point, the use of hardware based, and in particular FPGA solutions, might appear as a candidate technology, since though power use is higher compared with lower power devices, execution time is reduced, so energy could be reduced overall. In order to demonstrate this, an innovative WSN node architecture is proposed. This architecture is based on a high performance high capacity state-of-the-art FPGA, which combines the advantages of the intrinsic acceleration provided by the parallelism of hardware devices, the use of partial reconfiguration capabilities, as well as a careful power-aware management system, to show that energy savings for certain higher-end applications can be achieved. Finally, comprehensive tests have been done to validate the platform in terms of performance and power consumption, to proof that better energy efficiency compared to processor based solutions can be achieved, for instance, when encryption is imposed by the application requirements.

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Evolvable hardware (EH) is an interesting alternative to conventional digital circuit design, since autonomous generation of solutions for a given task permits self-adaptivity of the system to changing environments, and they present inherent fault tolerance when evolution is intrinsically performed. Systems based on FPGAs that use Dynamic and Partial Reconfiguration (DPR) for evolving the circuit are an example. Also, thanks to DPR, these systems can be provided with scalability, a feature that allows a system to change the number of allocated resources at run-time in order to vary some feature, such as performance. The combination of both aspects leads to scalable evolvable hardware (SEH), which changes in size as an extra degree of freedom when trying to achieve the optimal solution by means of evolution. The main contributions of this paper are an architecture of a scalable and evolvable hardware processing array system, some preliminary evolution strategies which take scalability into consideration, and to show in the experimental results the benefits of combined evolution and scalability. A digital image filtering application is used as use case.

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El sistema portuario español movió en el año 2013 aproximadamente 458,54 millones de toneladas, 13,8 millones de TEUs, con un total de 131.128 buques que accedieron a puerto para el conjunto de las 28 Autoridades Portuarias. Con el 62% de las exportaciones y el 86% de las importaciones realizadas por vía marítima, una rentabilidad del 2,34 %, muy cerca del objetivo del 2,5 % de rentabilidad media annual establecida legalmente, y una cifra de negocios aproximada de 1.028 millones de euros equivalentes al 1,1 % del PIB que genera un empleo directo e indirecto vinculado de 145.000 personas, concluimos que estamos hablando de un sector estratégico para la economía del país. Desde hace décadas, en muchos puertos del mundo se han venido desarrollando terminales “hub” o de concentración y distribución de cargas. Las navieras concentran entre este tipo de terminales sus líneas transoceánicas con buques de enormes dimensiones y capacidad de carga para producir los tránsitos de contenedores desde estas líneas a otras líneas llamadas “feeder”, con buques de menor tamaño que enlazan el “hub” con los puertos de su área marítima de influencia. La excepcional ubicación geoestratégica de España, con aproximadamente ocho mil kilómetros de costa, ha originado que los puertos españoles de mayor dimensión aspiren a incorporarse a esta red marítima internacional de contenedores y determina que en nuestro sistema portuario los movimientos de contenedores de tránsito tengan gran importancia. Sin embargo, la crisis económica ha tenido un efecto decisivo en el sector marítimo, determinando una lucha feroz entre todos los puertos, nacionales e internacionales, por captar este tipo de tráficos, lo que origina una búsqueda de las compañías navieras de puertos cada vez más eficientes en términos calidad/coste del servicio. La entrada en vigor del Texto Refundido de la Ley de Puertos y la piedra angular de su reforma, la Ley 33/2010, plantea como objetivo principal la mejora de la competitividad del sistema portuario español y liderar su recuperación, ofreciendo unas condiciones de entorno favorables a los puertos españoles que acaben por incentivar la captación de tráficos e inversión privada a través de una oferta de servicios e infraestructura de calidad y a precios competitivos que consoliden su posición dentro del tráfico marítimo mundial. Surge, por tanto, la conveniencia de investigar la influencia de las medidas propuestas por dicha norma legal y las soluciones ofrecidas a las demandas de un sector considerado estratégico para la economía del país, y cuya resolución se considera imprescindible para consolidar su recuperación. Por eso, se han analizado los aspectos más importantes de la reforma mediante la realización de un resumen ejecutivo y se ha estudiado la influencia de las medidas que incorpora desde el punto de vista de tres factores, que previamente se han considerado como fundamentales para la recuperación del sistema portuario español, y que históricamente habían sido demandados por el mismo, como son, en primer lugar, un progresivo sistema de flexibilización tributaria que permitiera a los puertos españoles ganar en términos de competitividad respecto a otros modelos portuarios mucho más flexibles en materia tarifaria, en segundo lugar, una necesaria liberalización del régimen de prestación de los servicios portuarios que posibilite el libre acceso a cualquier interesado en su prestación y, en último lugar, el progresivo abaratamiento de los costes inherentes a dichos servicios, fundamentalmente la manipulación de mercancías. Con posterioridad se ha investigado el trámite parlamentario al que se ha sometido la ley, fruto del enorme consenso alcanzado entre las dos principales fuerzas políticas del país, que determinó que se presentaran más de 700 enmiendas al proyecto original, y en algunos casos, se ha prestado especial atención a determinadas enmiendas que se consideran, en opinión de este investigador, novedosas y aventuradas, razón por la cual quizás no fueron incorporadas definitivamente al texto legal. Y se han analizado las principales demandas y aportaciones extraídas de la Sesión Informativa sobre la tramitación del entonces proyecto de ley ofrecida por la Comisión de Fomento del Congreso de los Diputados a los principales representantes del sector, comunidad portuaria, universidad y sindicatos. Siendo conscientes de la incidencia que tiene el servicio portuario de manipulación de mercancías en el paso de la mercancía por el puerto, se ha hecho una referencia concreta al peculiar régimen jurídico y laboral del personal vinculado al servicio. Avanzamos que las características de la relación laboral especial, y su peculiar régimen jurídico, con una dualidad de relaciones laborales, tiene una influencia decisiva en la nómina del trabajador que se repercute en los usuarios del servicio, fundamentalmente el naviero y el operador de la terminal, que en definitiva, incide en la competitividad del puerto. Y se ha constatado el auge aperturista de numerosas legislaciones portuarias europeas, prestando especial atención al proyecto frustrado de liberalización de los servicios portuarios en la Unión Europea de la conocida como Directiva Loyola de Palacio del año 2003 y al Libro Blanco de Transportes del año 2011. Así como a las deficiencias advertidas por el Dictamen de la Comisión Europea de fecha 27/09/2012 en relación al régimen jurídico del servicio portuario de manipulación de mercancías, que lo considera disconforme y contrario con las normas de libertad de establecimiento en Europa y que amenaza con una previsible reforma unilateral de la legislación portuaria española, a instancias europeas. Bajo este planteamiento, se ha procedido a analizar el marco de prestación de dichos servicios desde el punto de vista de la propia comunidad portuaria. Inicialmente, a través de un estudio de fuerzas de la competitividad del sector de los servicios portuarios en el sistema portuario español que nos permitirá trazar un mapa estratégico del mismo a través del “Modelo de las Cinco Fuerzas de Porter” concluyendo, que el poder de los prestadores de servicios portuarios como proveedores de los mismos, fundamentalmente en la manipulación de mercancías, es máximo, con un único colectivo, los estibadores portuarios, que al amparo de la normativa legal vigente tienen la exclusividad de su prestación. Dichas circunstancias restan competitividad al sistema frente a alternativas portuarias más flexibles y desincentivan la inversión privada. Y, en segundo lugar, mediante un proceso participativo en distintas encuestas sobre el modelo legislativo y sobre el marco formativo del sector con los propios agentes afectados dentro de la comunidad portuaria, desde la triple perspectiva de la vertiente pública que representan las Autoridades Portuarias, como gestores de las infraestructuras, la vertiente privada que representan los usuarios y prestadores de servicios, como principal cliente del puerto y desde el punto de vista de la propia mano de obra portuaria materializada en la representación sindical de dichos trabajadores. Los resultados nos permitirán concluir, respectivamente, la incidencia del servicio portuario mercancía por el puerto, por representar más de la mitad de los costes. Así como la aspiración de los trabajadores adscritos a dicho servicio de consolidar un título formativo que unifique y potencie su capacitación profesional, circunstancia esta última, también demandada por toda comunidad portuaria. Analizadas las conclusiones extraídas en cada una de las líneas de investigación se han detectado una serie de ineficiencias dentro del mismo que dicho marco regulador no ha sabido resolver, por lo que se ha considerado la conveniencia de formular, como herramienta de ayuda a gestores del sistema portuario español, una relación de medidas que, en opinión de este investigador, se consideran necesarias para mejorar el régimen de prestación de los servicios portuarios y se ha propuesto un borrador de modificación del actual Texto Refundido que pueda servir de base para materializar una futura reforma legal. Las conclusiones obtenidas en la investigación deben sentar las bases de una profunda reflexión sobre la necesidad de encaminar, como alternativa a una previsible modificación a instancias europeas, una reforma legal que decididamente apueste por la competitividad del sistema portuario español desde el punto de vista de la liberalización de servicios, el abaratamiento de los costes de la estiba y la necesaria profesionalización de los trabajadores adscritos al servicio portuario de manipulación de mercancías. During 2013 the Spanish Port System moved nearly 458,54 million tons of freight, 13,8 million TEUs, involving a total of 131.128 ships for the 28 existing Port Authorities. With 62% of exports and 86% of imports made through sea transportation, a 2,34% profit, close to the 2,5% average annual profit goal legally established, revenues of 1.028 million € equivalent to a 1.1% of Spain’s GDP and a figure of 145.000 people a directly or indirectly employed we can conclude that maritime industry is undoubtedly one of the strategic and key sectors for the country’s economy. Since several decades many ports in the world have been increasingly developing “Hub” terminals, those which concentrate and distribute freight. Shipping companies place among these type of terminals their transoceanic sea liners along with huge dimension & capacity ships to make the container transit from these liners to other called “feeder” which are smaller freight ships that connect the “hub” with the ports within its maritime area of influence. Spain’s exceptional geostrategic location with over 8.000 km of coastline has originated that those big dimension Spanish ports aspire to become a part of a container international maritime network which also determines that transit container move is key within our port system. Nevertheless the economic crisis has had a decisive impact on the maritime sector originating a fierce battle between all ports, national and international ones, all of them fight against each other to catch this type of maritime traffic which triggers an ongoing shipping companies search in cost/service quality efficient ports. The cornerstone of the Restated Text of Port Law is Law 33/2010, which lays out as main goal the Spanish Port System competitiveness improvement and lead its recovery offering favorable environment conditions to Spanish ports which help encourage maritime traffic attraction and private investment through a wide offer of services, quality of infrastructure and competitive prices which can consolidate its positioning within the world’s maritime traffic. It is therefore key to investigate the influence of the measures proposed by the above mentioned law and also the solutions offered to the demands of a sector which is considered strategic for the country’s economy and which solution is essential to consolidate the recovery. It is because of this that the most important aspects of the reform have been analyzed through the making of an executive summary and it has also been studied the influence of the measures it includes from the point of view of three factors which have previously been considered as key for the Spanish port system recovery. The system has historically demanded a progressive tax flexibility, which would permit Spanish ports be more competitive compared to other port models much more flexible in rates, a necessary liberalization of the port service provision regime and last but not least, to cut the price of costs related to those services, mainly freight handling. Following this, the parliamentary process of the law has also been studied as a consequence of the vast consensus reached by the main political forces in the country which clearly determined that more than 700 amendments to the original project were presented. In some cases the focus has been on amendments which are adventurous and new, reason why they were finally not included to the final legal text. Being well aware of the importance that freight handling procedure has, I have made a specific reference to the legal and working framework of those employees related to this service. We conclude that the special working relationship, its different legal regime, along with the working relationship dualism has a big impact and decisive influence over the worker’s salary which also affects service users, mainly shipowners and terminal operators, having a bad effect on the port’s competitiveness. The above confirms the new opening trend of main European port laws with special attention to the frustrated European Union port services liberalization project, also known as Directive Loyola de Palacio (2003) and the White Paper on Transports (2011). It is important to highlight that the European Commission has also observed several deficiencies with regard to the freight handling port service Law Regime being in disagreement with it, considering it is against the free establishment rules in Europe. The Commission is likely to present a unilateral reform to the Spanish Port Law. Under this approach the service provision framework is being analyzed from the Port Community point of view. Initially the analysis will focus on the study of the competition forces within the port services industry in Spain, this will allow us to draw up an strategic map through “Porter’s Five Forces Model” concluding that the power of port services providers as freight handlers is maximum, with an only collective, stevedores, which has the exclusivity for their services. All these circumstances not only decrease the system’s competitiveness versus other more flexible but also restrain private investments. Secondly, through a participating procedure in different surveys about the legislative model and about the training framework with the affected agents within the port community, there is a triple perspective: Public point of view represented by Port Authorities as infrastructure managers, Private point of view represented by users and service suppliers as main Port’s customer and finally, port workforce, represented by union leaders. Results will let us conclude that freight handling service is the most critical port service and represents more than half of the costs. This service related workers aspire to obtain a training certificate that unifies and boosts their professional role which is also chased by the entire port community. Once conclusions have been analyzed for all research lines, several deficiencies have been found and the regulatory framework hasn’t yet been able to solve them, it has therefore been a series of necessary measures that help improve the port services provision regime. A new proposal to the Restated Law Text has been drafted as the first step to embrace a future legal reform. Conclusions obtained on the research should set the new basis of a deep reflection about the need to bent on a new legal reform which firmly bets on Spanish port system competitiveness from three key points of view, service liberalization, ship load cost reduction and professionalization of freight handling related workers.

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The aim of this study was to determine the effect of animal management and farm facilities on total feed intake (TFI), feed conversion ratio (FCR) and mortality rate (MORT) of grower-finishing pigs. In total, 310 batches from 244 grower-finishing farms, consisting of 454 855 Pietrain sired pigs in six Spanish pig companies were used. Data collection consisted of a survey on management practices (season of placement, split-sex by pens, number of pig origins, water source in the farm, initial or final BW) and facilities (floor, feeder, ventilation or number of animals placed) during 2008 and 2009. Results indicated that batches of pigs placed between January and March had higher TFI (P=0.006), FCR (P=0.005) and MORT (P=0.03) than those placed between July and September. Moreover, batches of pigs placed between April and June had lower MORT (P=0.003) than those placed between January and March. Batches which had split-sex pens had lower TFI (P=0.001) and better FCR (P<0.001) than those with mixed-sex in pens; pigs fed with a single-space feeder with incorporated drinker also had the lowest TFI (P<0.001) and best FCR (P<0.001) in comparison to single and multi-space feeders without a drinker. Pigs placed in pens with <50% slatted floors presented an improvement in FCR (P<0.05) than pens with 50% or more slatted floors. Batches filled with pigs from multiple origins had higher MORT (P<0.001) than those from a single origin. Pigs housed in barns that performed manual ventilation control presented higher MORT (P<0.001) in comparison to automatic ventilation. The regression analysis also indicated that pigs which entered to grower-finisher facilities with higher initial BW had lower MORT (P<0.05) and finally pigs which were sent to slaughterhouse with a higher final BW presented higher TFI (P<0.001). The variables selected for each dependent variable explained 61.9%, 24.8% and 20.4% of the total variability for TFI, FCR and MORT, respectively. This study indicates that farms can increase growth performance and reduce mortality by improving farm facilities and/or modifying management practices.

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Cyber-Physical Systems need to handle increasingly complex tasks, which additionally, may have variable operating conditions over time. Therefore, dynamic resource management to adapt the system to different needs is required. In this paper, a new bus-based architecture, called ARTICo3, which by means of Dynamic Partial Reconfiguration, allows the replication of hardware tasks to support module redundancy, multi-thread operation or dual-rail solutions for enhanced side-channel attack protection is presented. A configuration-aware data transaction unit permits data dispatching to more than one module in parallel, or provide coalesced data dispatching among different units to maximize the advantages of burst transactions. The selection of a given configuration is application independent but context-aware, which may be achieved by the combination of a multi-thread model similar to the CUDA kernel model specification, combined with a dynamic thread/task/kernel scheduler. A multi-kernel application for face recognition is used as an application example to show one scenario of the ARTICo3 architecture.

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Dynamic and Partial Reconfiguration allows systems to change some parts of their hardware at run time. This feature favours the inclusion of evolutionary strategies to provide optimised solutions to the same problem so that they can be mixed and compared in a way that only the best ones prevail. At the same time, distributed intelligence permits systems to work in a collaborative way to jointly improve their global capabilities. This work presents a combination of both approaches where hardware evolution is performed both at local and network level in order to improve an image filter application in terms of performance, robustness and providing the capacity of avoiding local minimums, which is the main drawback of some evolutionary approaches.

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Dynamic and Partial Reconfiguration (DPR) allows a system to be able to modify certain parts of itself during run-time. This feature gives rise to the capability of evolution: changing parts of the configuration according to the online evaluation of performance or other parameters. The evolution is achieved through a bio-inspired model in which the features of the system are identified as genes. The objective of the evolution may not be a single one; in this work, power consumption is taken into consideration, together with the quality of filtering, as the measure of performance, of a noisy image. Pareto optimality is applied to the evolutionary process, in order to find a representative set of optimal solutions as for performance and power consumption. The main contributions of this paper are: implementing an evolvable system on a low-power Spartan-6 FPGA included in a Wireless Sensor Network node and, by enabling the availability of a real measure of power consumption at run-time, achieving the capability of multi-objective evolution, that yields different optimal configurations, among which the selected one will depend on the relative “weights” of performance and power consumption.