The elliptic rendezvous problem in DROMO formulation

The extension of DROMO formulation to relative motion is evaluated. The orbit of the follower spacecraft can be constructed through differences on the elements defining the orbit of the leader spacecraft. Assuming that the differences are small, the problemis linearized. Typical linearized solutions to relativemotion determine the relative state of the follower spacecraft at a certain time step. Because of the form of DROMO formulation, the performance of a frozen-anomaly transformation is explored. In this case, the relative state is computed for a certain value of the anomaly, equal for leader and follower. Since the time for leader and follower do not coincide, the implicit time delay needs to be corrected to recover the physical sense of the solution. When determining the relative orbit, numerical testing shows significant error reductions compared to previous linearized solutions.

Metodología de Diseño y Análisis de Sistemas Teleoperados Considerando Dinámica No Lineal

Cuando la separación física entre el sistema local y remoto es relativamente corta, el retardo no es perceptible; sin embargo, cuando el manipulador local y el manipulador remoto se encuentran a una distancia lejana uno del otro, el retardo de tiempo ya no es insignificante e influye negativamente en la realización de la tarea. El retardo de tiempo en un sistema de control introduce un atraso de fase que a su vez degrada el rendimiento del sistema y puede causar inestabilidad. Los sistemas de teleoperación pueden sacar provecho de la posibilidad de estar presente en dos lugares simultáneamente, sin embargo, el uso de Internet y otras redes de conmutación de paquetes, tales como Internet2, impone retardos de tiempo variables, haciendo que los esquemas de control ya establecidos elaboren soluciones para hacer frente a inestabilidades causadas por estos retardos de tiempo variables. En este trabajo de tesis se presenta el modelado y análisis de un sistema de teloperación bilateral no lineal de n grados de libertad controlado por convergencia de estado. La comunicación entre el sitio local y remoto se realiza mediante un canal de comunicación con retardo de tiempo. El análisis presentado en este trabajo considera que el retardo puede ser constante o variable. Los principales objetivos de este trabajo son; 1) Desarrollar una arquitectura de control no lineal garantizando la estabilidad del sistema teleoperado, 2) Evaluar la estabilidad del sistema considerando el retardo en la comunicación, y 3) Implementación de los algoritmos desarrollados para probar el desempeño de los mismos en un sistema experimental de 3 grados de libertad. A través de la teoría de Estabilidad de Lyapunov y el funcional Lyapunov-Krasovskii, se demuestra que el sistema de lazo cerrado es asintóticamente estable. Estas conclusiones de estabilidad se han obtenido mediante la integración de la función de Lyapunov y aplicando el Lema de Barbalat. Se demuestra también que se logra sincronizar las posiciones del manipulador local y remoto cuando el operador humano no mueve el manipulador local y el manipulador remoto se mueve libremente. El esquema de control propuesto se ha validado mediante simulación y en forma experimental empleando un sistema de teleoperación real desarrollado en esta tesis doctoral y que consta de un un manipulador serie planar de tres grados de libertad, un manipulador local, PHANTOM Omni, el cual es un dispositivo haptico fabricado que consta de 3 grados de libertad (en fuerza) y que proporciona realimentación de fuerza en los ejes x,y,z. El control en tiempo real se ha diseñado usando el Sistema Operativo en Tiempo Real QuaRC de QUARC en el lado local y el Simulink Real-Time Windows TargetTM en el lado remoto. Para finalizar el resumen se destaca el impacto de esta tesis en el mundo científico a través de los resultados publicados: 2 artículos en revistas con índice de impacto , 1 artículo en una revista indexada en Sistemas, Cibernética e Informática, 7 artículos en congresos y ha obtenido un premio en la 9a. Conferencia Iberoamericana en Sistemas, Cibernética e Informática, 2010. ABSTRACT When the physical separation between the local and remote system is relatively short, the delay is not noticeable; however, when the local manipulator and the remote manipulator are at a far distance from each other, the time delay is no longer negligible and negatively influences the performance of the task. The time delay in a control system introduces a phase delay which in turn degrades the system performance and cause instability. Teleoperation systems can benefit from the ability to be in two places simultaneously, however, the use of Internet and other packet switched networks, such as Internet2, imposes varying time delays, making established control schemes to develop solutions to address these instabilities caused by different time delays. In this thesis work we present a modeling and analysis of a nonlinear bilateral teloperation system of n degrees of freedom controlled by state convergence strategy. Communication between the local and remote site is via a communication channel with time delay. The analysis presented in this work considers that the time-delay can be constant or variable. The main objectives of this work are; 1) Develop a nonlinear control schemes to ensure the stability of the teleoperated system, 2) Evaluate the system stability considering the delay in communication, and 3) Implementation of algorithms developed to test the performance of the teleoperation system in an experimental system of 3 degrees of freedom. Through the Theory of Stability of Lyapunov and the functional Lyapunov-Krasovskii, one demonstrates that the closed loop system is asymptotically stable.. The conclusions about stability were obtained by integration of the Lyapunov function and applying Barbalat Lemma. It further shows that the positions of the local and remote manipulator are synchronize when the human operator stops applying a constant force and the remote manipulator does not interact with the environment. The proposed control scheme has been validated by means of simulation and in experimental form using a developed system of real teleoperation in this doctoral thesis, which consists of a series planar manipulator of three degrees of freedom, a local manipulator, PHANTOM Omni, which is an haptic device that consists of 3 degrees of freedom (in force) and that provide feeback force in x-axis, and, z. The control in real time has been designed using the Operating system in Real time QuaRC of Quanser in the local side and the Simulink Real-Time Windows Target in the remote side. In order to finalize the summary, the highlights impact of this thesis in the scientific world are shows through the published results: 2 articles in Journals with impact factor, one article in a indexed Journal on Systemics, Cybernetics and Informatics, 7 articles in Conferences and has won an award in 9a. Conferencia Iberoamericana en Sistemas, Cibernética e Informática, 2010.

Sonic anemometry of planetary atmospheres

The application of a recently developed model of sonic anemometers measuring process has revealed that these sensors cannot be considered as absolute ones when measuring spectral characteristics of turbulent wind speed since it is demonstrated that the ratios of measured to real spectral density functions depend on the composition and temperature of the considered planetary atmosphere. The new model of the measuring process of sonic anemometers is applied to describe the measuring characteristics of these sensors as fluid/flow dependent (against the traditional hypothesis of fluid/flow independence) and hence dependent on the considered planetary atmosphere. The influence of fluid and flow characteristics (quantified via the Mach number of the flow) and the influence of the design parameters of sonic anemometers (mainly represented by time delay between pulses shots and geometry) on turbulence measurement are quantified for the atmospheres of Mars, Jupiter, and Earth. Important differences between the behavior of these sensors for the same averaged wind speed in the three considered atmospheres are detected in terms of characteristics of turbulence measurement as well as in terms of optimum values of anemometer design parameters for application on the different considered planetary atmospheres. These differences cannot be detected by traditional models of sonic anemometer measuring process based on line averaging along the sonic acoustic paths.

On multiple-path sonic anemometer measurement theory

In this paper, a model of the measuring process of sonic anemometers with more than one measuring path is presented. The main hypothesis of the work is that the time variation of the turbulent speed field during the sequence of pulses that produces a measure of the wind speed vector affects the measurement. Therefore, the previously considered frozen flow, or instantaneous averaging, condition is relaxed. This time variation, quantified by the mean Mach number of the flow and the time delay between consecutive pulses firings, in combination with both the full geometry of sensors (acoustic path location and orientation) and the incidence angles of the mean with speed vector, give rise to significant errors in the measurement of turbulence which are not considered by models based on the hypothesis of instantaneous line averaging. The additional corrections (relative to the ones proposed by instantaneous line-averaging models) are strongly dependent on the wave number component parallel to the mean wind speed, the time delay between consecutive pulses, the Mach number of the flow, the geometry of the sensor and the incidence angles of mean wind speed vector. Kaimal´s limit k W1=1/l (where k W1 is the wave number component parallel to mean wind speed and l is the path length) for the maximum wave numbers from which the sonic process affects the measurement of turbulence is here generalized as k W1=C l /l, where C l is usually lesser than unity and depends on all the new parameters taken into account by the present model.

On sonic anemometer measurement theory

In this paper a model for the measuring process of sonic anemometers (ultrasound pulse based) is presented. The differential equations that describe the travel of ultrasound pulses are solved in the general case of non-steady, non-uniform atmospheric flow field. The concepts of instantaneous line-average and travelling pulse-referenced average are established and employed to explain and calculate the differences between the measured turbulent speed (travelling pulse-referenced average) and the line-averaged one. The limit k1l=1 established by Kaimal in 1968, as the maximum value which permits the neglect of the influence of the sonic measuring process on the measurement of turbulent components is reviewed here. Three particular measurement cases are analysed: A non-steady, uniform flow speed field, a steady, non-uniform flow speed field and finally an atmospheric flow speed field. In the first case, for a harmonic time-dependent flow field, Mach number, M (flow speed to sound speed ratio) and time delay between pulses have revealed themselves to be important parameters in the behaviour of sonic anemometers, within the range of operation. The second case demonstrates how the spatial non-uniformity of the flow speed field leads to an influence of the finite transit time of the pulses (M≠0) even in the absence of non-steady behaviour of the wind speed. In the last case, a model of the influence of the sonic anemometer processes on the measurement of wind speed spectral characteristics is presented. The new solution is compared to the line-averaging models existing in the literature. Mach number and time delay significantly distort the measurement in the normal operational range. Classical line averaging solutions are recovered when Mach number and time delay between pulses go to zero in the new proposed model. The results obtained from the mathematical model have been applied to the calculation of errors in different configurations of practical interest, such as an anemometer located on a meteorological mast and the transfer function of a sensor in an atmospheric wind. The expressions obtained can be also applied to determine the quality requirements of the flow in a wind tunnel used for ultrasonic anemometer calibrations.

Influence of delay time on regularity estimation for voice pathology detection

The employment of nonlinear analysis techniques for automatic voice pathology detection systems has gained popularity due to the ability of such techniques for dealing with the underlying nonlinear phenomena. On this respect, characterization using nonlinear analysis typically employs the classical Correlation Dimension and the largest Lyapunov Exponent, as well as some regularity quantifiers computing the system predictability. Mostly, regularity features highly depend on a correct choosing of some parameters. One of those, the delay time �, is usually fixed to be 1. Nonetheless, it has been stated that a unity � can not avoid linear correlation of the time series and hence, may not correctly capture system nonlinearities. Therefore, present work studies the influence of the � parameter on the estimation of regularity features. Three � estimations are considered: the baseline value 1; a � based on the Average Automutual Information criterion; and � chosen from the embedding window. Testing results obtained for pathological voice suggest that an improved accuracy might be obtained by using a � value different from 1, as it accounts for the underlying nonlinearities of the voice signal.

Broadband Channel Long Delay Cluster Measurements and Analysis at 2.4GHz in Subway Tunnels

The delay caused by the reflected ray in broadband communication has a great influence on the communications in subway tunnel. This paper presents measurements taken in subway tunnels at 2.4 GHz, with 5 MHz bandwidth. According to propagation characteristics of tunnel, the measurements were carried out with a frequency domain channel sounding technique, in three typical scenarios: line of sight (LOS), Non-line-of-sight (NLOS) and far line of sight (FLOS), which lead to different delay distributions. Firstly IFFT was chosen to get channel impulse response (CIR) h(t) from measured three-dimensional transfer functions. Power delay profile (PDP) was investigated to give an overview of broadband channel model. Thereafter, a long delay caused by the obturation of tunnel is observed and investigated in all the scenarios. The measurements show that the reflection can be greatly remained by the tunnel, which leads to long delay cluster where the reflection, but direct ray, makes the main contribution for radio wave propagation. Four important parameters: distribution of whole PDP power, first peak arriving time, reflection cluster duration and PDP power distribution of reflection cluster were studied to give a detailed description of long delay characteristic in tunnel. This can be used to ensure high capacity communication in tunnels

Effect of a variable delay in delayed dynamical systems

We report numerical evidence of the effects of a periodic modulation in the delay time of a delayed dynamical system. By referring to a Mackey-Glass equation and by adding a modula- tion in the delay time, we describe how the solution of the system passes from being chaotic to shadow periodic states. We analyze this transition for both sinusoidal and sawtooth wave mod- ulations, and we give, in the latter case, the relationship between the period of the shadowed orbit and the amplitude of the modulation. Future goals and open questions are highlighted.

Optical Multistability and Oscillations in Hybrid Optical Bistable Systems with Short Delay Times

Optical instabilities in the output light from a bistable optical device (BOD) with a delayed feedback was predicted by Ikeda [1]. Gibbs et al. [2] gave the first experimental verification of this type of instabilities. From that time several groups have studied the instabilities of the BOD for different relations between the delay time tR and the time constant ح of the system. In a previous paper [3] an empirical and analytical study of instabilities in hybrid BOD was reported by us. The employed set up is shown in Fig. 1.

Run-Time Scalable Hardware for Reconfigurable Systems

La optimización de parámetros tales como el consumo de potencia, la cantidad de recursos lógicos empleados o la ocupación de memoria ha sido siempre una de las preocupaciones principales a la hora de diseñar sistemas embebidos. Esto es debido a que se trata de sistemas dotados de una cantidad de recursos limitados, y que han sido tradicionalmente empleados para un propósito específico, que permanece invariable a lo largo de toda la vida útil del sistema. Sin embargo, el uso de sistemas embebidos se ha extendido a áreas de aplicación fuera de su ámbito tradicional, caracterizadas por una mayor demanda computacional. Así, por ejemplo, algunos de estos sistemas deben llevar a cabo un intenso procesado de señales multimedia o la transmisión de datos mediante sistemas de comunicaciones de alta capacidad. Por otra parte, las condiciones de operación del sistema pueden variar en tiempo real. Esto sucede, por ejemplo, si su funcionamiento depende de datos medidos por el propio sistema o recibidos a través de la red, de las demandas del usuario en cada momento, o de condiciones internas del propio dispositivo, tales como la duración de la batería. Como consecuencia de la existencia de requisitos de operación dinámicos es necesario ir hacia una gestión dinámica de los recursos del sistema. Si bien el software es inherentemente flexible, no ofrece una potencia computacional tan alta como el hardware. Por lo tanto, el hardware reconfigurable aparece como una solución adecuada para tratar con mayor flexibilidad los requisitos variables dinámicamente en sistemas con alta demanda computacional. La flexibilidad y adaptabilidad del hardware requieren de dispositivos reconfigurables que permitan la modificación de su funcionalidad bajo demanda. En esta tesis se han seleccionado las FPGAs (Field Programmable Gate Arrays) como los dispositivos más apropiados, hoy en día, para implementar sistemas basados en hardware reconfigurable De entre todas las posibilidades existentes para explotar la capacidad de reconfiguración de las FPGAs comerciales, se ha seleccionado la reconfiguración dinámica y parcial. Esta técnica consiste en substituir una parte de la lógica del dispositivo, mientras el resto continúa en funcionamiento. La capacidad de reconfiguración dinámica y parcial de las FPGAs es empleada en esta tesis para tratar con los requisitos de flexibilidad y de capacidad computacional que demandan los dispositivos embebidos. La propuesta principal de esta tesis doctoral es el uso de arquitecturas de procesamiento escalables espacialmente, que son capaces de adaptar su funcionalidad y rendimiento en tiempo real, estableciendo un compromiso entre dichos parámetros y la cantidad de lógica que ocupan en el dispositivo. A esto nos referimos con arquitecturas con huellas escalables. En particular, se propone el uso de arquitecturas altamente paralelas, modulares, regulares y con una alta localidad en sus comunicaciones, para este propósito. El tamaño de dichas arquitecturas puede ser modificado mediante la adición o eliminación de algunos de los módulos que las componen, tanto en una dimensión como en dos. Esta estrategia permite implementar soluciones escalables, sin tener que contar con una versión de las mismas para cada uno de los tamaños posibles de la arquitectura. De esta manera se reduce significativamente el tiempo necesario para modificar su tamaño, así como la cantidad de memoria necesaria para almacenar todos los archivos de configuración. En lugar de proponer arquitecturas para aplicaciones específicas, se ha optado por patrones de procesamiento genéricos, que pueden ser ajustados para solucionar distintos problemas en el estado del arte. A este respecto, se proponen patrones basados en esquemas sistólicos, así como de tipo wavefront. Con el objeto de poder ofrecer una solución integral, se han tratado otros aspectos relacionados con el diseño y el funcionamiento de las arquitecturas, tales como el control del proceso de reconfiguración de la FPGA, la integración de las arquitecturas en el resto del sistema, así como las técnicas necesarias para su implementación. Por lo que respecta a la implementación, se han tratado distintos aspectos de bajo nivel dependientes del dispositivo. Algunas de las propuestas realizadas a este respecto en la presente tesis doctoral son un router que es capaz de garantizar el correcto rutado de los módulos reconfigurables dentro del área destinada para ellos, así como una estrategia para la comunicación entre módulos que no introduce ningún retardo ni necesita emplear recursos configurables del dispositivo. El flujo de diseño propuesto se ha automatizado mediante una herramienta denominada DREAMS. La herramienta se encarga de la modificación de las netlists correspondientes a cada uno de los módulos reconfigurables del sistema, y que han sido generadas previamente mediante herramientas comerciales. Por lo tanto, el flujo propuesto se entiende como una etapa de post-procesamiento, que adapta esas netlists a los requisitos de la reconfiguración dinámica y parcial. Dicha modificación la lleva a cabo la herramienta de una forma completamente automática, por lo que la productividad del proceso de diseño aumenta de forma evidente. Para facilitar dicho proceso, se ha dotado a la herramienta de una interfaz gráfica. El flujo de diseño propuesto, y la herramienta que lo soporta, tienen características específicas para abordar el diseño de las arquitecturas dinámicamente escalables propuestas en esta tesis. Entre ellas está el soporte para el realojamiento de módulos reconfigurables en posiciones del dispositivo distintas a donde el módulo es originalmente implementado, así como la generación de estructuras de comunicación compatibles con la simetría de la arquitectura. El router has sido empleado también en esta tesis para obtener un rutado simétrico entre nets equivalentes. Dicha posibilidad ha sido explotada para aumentar la protección de circuitos con altos requisitos de seguridad, frente a ataques de canal lateral, mediante la implantación de lógica complementaria con rutado idéntico. Para controlar el proceso de reconfiguración de la FPGA, se propone en esta tesis un motor de reconfiguración especialmente adaptado a los requisitos de las arquitecturas dinámicamente escalables. Además de controlar el puerto de reconfiguración, el motor de reconfiguración ha sido dotado de la capacidad de realojar módulos reconfigurables en posiciones arbitrarias del dispositivo, en tiempo real. De esta forma, basta con generar un único bitstream por cada módulo reconfigurable del sistema, independientemente de la posición donde va a ser finalmente reconfigurado. La estrategia seguida para implementar el proceso de realojamiento de módulos es diferente de las propuestas existentes en el estado del arte, pues consiste en la composición de los archivos de configuración en tiempo real. De esta forma se consigue aumentar la velocidad del proceso, mientras que se reduce la longitud de los archivos de configuración parciales a almacenar en el sistema. El motor de reconfiguración soporta módulos reconfigurables con una altura menor que la altura de una región de reloj del dispositivo. Internamente, el motor se encarga de la combinación de los frames que describen el nuevo módulo, con la configuración existente en el dispositivo previamente. El escalado de las arquitecturas de procesamiento propuestas en esta tesis también se puede beneficiar de este mecanismo. Se ha incorporado también un acceso directo a una memoria externa donde se pueden almacenar bitstreams parciales. Para acelerar el proceso de reconfiguración se ha hecho funcionar el ICAP por encima de la máxima frecuencia de reloj aconsejada por el fabricante. Así, en el caso de Virtex-5, aunque la máxima frecuencia del reloj deberían ser 100 MHz, se ha conseguido hacer funcionar el puerto de reconfiguración a frecuencias de operación de hasta 250 MHz, incluyendo el proceso de realojamiento en tiempo real. Se ha previsto la posibilidad de portar el motor de reconfiguración a futuras familias de FPGAs. Por otro lado, el motor de reconfiguración se puede emplear para inyectar fallos en el propio dispositivo hardware, y así ser capaces de evaluar la tolerancia ante los mismos que ofrecen las arquitecturas reconfigurables. Los fallos son emulados mediante la generación de archivos de configuración a los que intencionadamente se les ha introducido un error, de forma que se modifica su funcionalidad. Con el objetivo de comprobar la validez y los beneficios de las arquitecturas propuestas en esta tesis, se han seguido dos líneas principales de aplicación. En primer lugar, se propone su uso como parte de una plataforma adaptativa basada en hardware evolutivo, con capacidad de escalabilidad, adaptabilidad y recuperación ante fallos. En segundo lugar, se ha desarrollado un deblocking filter escalable, adaptado a la codificación de vídeo escalable, como ejemplo de aplicación de las arquitecturas de tipo wavefront propuestas. El hardware evolutivo consiste en el uso de algoritmos evolutivos para diseñar hardware de forma autónoma, explotando la flexibilidad que ofrecen los dispositivos reconfigurables. En este caso, los elementos de procesamiento que componen la arquitectura son seleccionados de una biblioteca de elementos presintetizados, de acuerdo con las decisiones tomadas por el algoritmo evolutivo, en lugar de definir la configuración de las mismas en tiempo de diseño. De esta manera, la configuración del core puede cambiar cuando lo hacen las condiciones del entorno, en tiempo real, por lo que se consigue un control autónomo del proceso de reconfiguración dinámico. Así, el sistema es capaz de optimizar, de forma autónoma, su propia configuración. El hardware evolutivo tiene una capacidad inherente de auto-reparación. Se ha probado que las arquitecturas evolutivas propuestas en esta tesis son tolerantes ante fallos, tanto transitorios, como permanentes y acumulativos. La plataforma evolutiva se ha empleado para implementar filtros de eliminación de ruido. La escalabilidad también ha sido aprovechada en esta aplicación. Las arquitecturas evolutivas escalables permiten la adaptación autónoma de los cores de procesamiento ante fluctuaciones en la cantidad de recursos disponibles en el sistema. Por lo tanto, constituyen un ejemplo de escalabilidad dinámica para conseguir un determinado nivel de calidad, que puede variar en tiempo real. Se han propuesto dos variantes de sistemas escalables evolutivos. El primero consiste en un único core de procesamiento evolutivo, mientras que el segundo está formado por un número variable de arrays de procesamiento. La codificación de vídeo escalable, a diferencia de los codecs no escalables, permite la decodificación de secuencias de vídeo con diferentes niveles de calidad, de resolución temporal o de resolución espacial, descartando la información no deseada. Existen distintos algoritmos que soportan esta característica. En particular, se va a emplear el estándar Scalable Video Coding (SVC), que ha sido propuesto como una extensión de H.264/AVC, ya que este último es ampliamente utilizado tanto en la industria, como a nivel de investigación. Para poder explotar toda la flexibilidad que ofrece el estándar, hay que permitir la adaptación de las características del decodificador en tiempo real. El uso de las arquitecturas dinámicamente escalables es propuesto en esta tesis con este objetivo. El deblocking filter es un algoritmo que tiene como objetivo la mejora de la percepción visual de la imagen reconstruida, mediante el suavizado de los "artefactos" de bloque generados en el lazo del codificador. Se trata de una de las tareas más intensivas en procesamiento de datos de H.264/AVC y de SVC, y además, su carga computacional es altamente dependiente del nivel de escalabilidad seleccionado en el decodificador. Por lo tanto, el deblocking filter ha sido seleccionado como prueba de concepto de la aplicación de las arquitecturas dinámicamente escalables para la compresión de video. La arquitectura propuesta permite añadir o eliminar unidades de computación, siguiendo un esquema de tipo wavefront. La arquitectura ha sido propuesta conjuntamente con un esquema de procesamiento en paralelo del deblocking filter a nivel de macrobloque, de tal forma que cuando se varía del tamaño de la arquitectura, el orden de filtrado de los macrobloques varia de la misma manera. El patrón propuesto se basa en la división del procesamiento de cada macrobloque en dos etapas independientes, que se corresponden con el filtrado horizontal y vertical de los bloques dentro del macrobloque. Las principales contribuciones originales de esta tesis son las siguientes: - El uso de arquitecturas altamente regulares, modulares, paralelas y con una intensa localidad en sus comunicaciones, para implementar cores de procesamiento dinámicamente reconfigurables. - El uso de arquitecturas bidimensionales, en forma de malla, para construir arquitecturas dinámicamente escalables, con una huella escalable. De esta forma, las arquitecturas permiten establecer un compromiso entre el área que ocupan en el dispositivo, y las prestaciones que ofrecen en cada momento. Se proponen plantillas de procesamiento genéricas, de tipo sistólico o wavefront, que pueden ser adaptadas a distintos problemas de procesamiento. - Un flujo de diseño y una herramienta que lo soporta, para el diseño de sistemas reconfigurables dinámicamente, centradas en el diseño de las arquitecturas altamente paralelas, modulares y regulares propuestas en esta tesis. - Un esquema de comunicaciones entre módulos reconfigurables que no introduce ningún retardo ni requiere el uso de recursos lógicos propios. - Un router flexible, capaz de resolver los conflictos de rutado asociados con el diseño de sistemas reconfigurables dinámicamente. - Un algoritmo de optimización para sistemas formados por múltiples cores escalables que optimice, mediante un algoritmo genético, los parámetros de dicho sistema. Se basa en un modelo conocido como el problema de la mochila. - Un motor de reconfiguración adaptado a los requisitos de las arquitecturas altamente regulares y modulares. Combina una alta velocidad de reconfiguración, con la capacidad de realojar módulos en tiempo real, incluyendo el soporte para la reconfiguración de regiones que ocupan menos que una región de reloj, así como la réplica de un módulo reconfigurable en múltiples posiciones del dispositivo. - Un mecanismo de inyección de fallos que, empleando el motor de reconfiguración del sistema, permite evaluar los efectos de fallos permanentes y transitorios en arquitecturas reconfigurables. - La demostración de las posibilidades de las arquitecturas propuestas en esta tesis para la implementación de sistemas de hardware evolutivos, con una alta capacidad de procesamiento de datos. - La implementación de sistemas de hardware evolutivo escalables, que son capaces de tratar con la fluctuación de la cantidad de recursos disponibles en el sistema, de una forma autónoma. - Una estrategia de procesamiento en paralelo para el deblocking filter compatible con los estándares H.264/AVC y SVC que reduce el número de ciclos de macrobloque necesarios para procesar un frame de video. - Una arquitectura dinámicamente escalable que permite la implementación de un nuevo deblocking filter, totalmente compatible con los estándares H.264/AVC y SVC, que explota el paralelismo a nivel de macrobloque. El presente documento se organiza en siete capítulos. En el primero se ofrece una introducción al marco tecnológico de esta tesis, especialmente centrado en la reconfiguración dinámica y parcial de FPGAs. También se motiva la necesidad de las arquitecturas dinámicamente escalables propuestas en esta tesis. En el capítulo 2 se describen las arquitecturas dinámicamente escalables. Dicha descripción incluye la mayor parte de las aportaciones a nivel arquitectural realizadas en esta tesis. Por su parte, el flujo de diseño adaptado a dichas arquitecturas se propone en el capítulo 3. El motor de reconfiguración se propone en el 4, mientras que el uso de dichas arquitecturas para implementar sistemas de hardware evolutivo se aborda en el 5. El deblocking filter escalable se describe en el 6, mientras que las conclusiones finales de esta tesis, así como la descripción del trabajo futuro, son abordadas en el capítulo 7. ABSTRACT The optimization of system parameters, such as power dissipation, the amount of hardware resources and the memory footprint, has been always a main concern when dealing with the design of resource-constrained embedded systems. This situation is even more demanding nowadays. Embedded systems cannot anymore be considered only as specific-purpose computers, designed for a particular functionality that remains unchanged during their lifetime. Differently, embedded systems are now required to deal with more demanding and complex functions, such as multimedia data processing and high-throughput connectivity. In addition, system operation may depend on external data, the user requirements or internal variables of the system, such as the battery life-time. All these conditions may vary at run-time, leading to adaptive scenarios. As a consequence of both the growing computational complexity and the existence of dynamic requirements, dynamic resource management techniques for embedded systems are needed. Software is inherently flexible, but it cannot meet the computing power offered by hardware solutions. Therefore, reconfigurable hardware emerges as a suitable technology to deal with the run-time variable requirements of complex embedded systems. Adaptive hardware requires the use of reconfigurable devices, where its functionality can be modified on demand. In this thesis, Field Programmable Gate Arrays (FPGAs) have been selected as the most appropriate commercial technology existing nowadays to implement adaptive hardware systems. There are different ways of exploiting reconfigurability in reconfigurable devices. Among them is dynamic and partial reconfiguration. This is a technique which consists in substituting part of the FPGA logic on demand, while the rest of the device continues working. The strategy followed in this thesis is to exploit the dynamic and partial reconfiguration of commercial FPGAs to deal with the flexibility and complexity demands of state-of-the-art embedded systems. The proposal of this thesis to deal with run-time variable system conditions is the use of spatially scalable processing hardware IP cores, which are able to adapt their functionality or performance at run-time, trading them off with the amount of logic resources they occupy in the device. This is referred to as a scalable footprint in the context of this thesis. The distinguishing characteristic of the proposed cores is that they rely on highly parallel, modular and regular architectures, arranged in one or two dimensions. These architectures can be scaled by means of the addition or removal of the composing blocks. This strategy avoids implementing a full version of the core for each possible size, with the corresponding benefits in terms of scaling and adaptation time, as well as bitstream storage memory requirements. Instead of providing specific-purpose architectures, generic architectural templates, which can be tuned to solve different problems, are proposed in this thesis. Architectures following both systolic and wavefront templates have been selected. Together with the proposed scalable architectural templates, other issues needed to ensure the proper design and operation of the scalable cores, such as the device reconfiguration control, the run-time management of the architecture and the implementation techniques have been also addressed in this thesis. With regard to the implementation of dynamically reconfigurable architectures, device dependent low-level details are addressed. Some of the aspects covered in this thesis are the area constrained routing for reconfigurable modules, or an inter-module communication strategy which does not introduce either extra delay or logic overhead. The system implementation, from the hardware description to the device configuration bitstream, has been fully automated by modifying the netlists corresponding to each of the system modules, which are previously generated using the vendor tools. This modification is therefore envisaged as a post-processing step. Based on these implementation proposals, a design tool called DREAMS (Dynamically Reconfigurable Embedded and Modular Systems) has been created, including a graphic user interface. The tool has specific features to cope with modular and regular architectures, including the support for module relocation and the inter-module communications scheme based on the symmetry of the architecture. The core of the tool is a custom router, which has been also exploited in this thesis to obtain symmetric routed nets, with the aim of enhancing the protection of critical reconfigurable circuits against side channel attacks. This is achieved by duplicating the logic with an exactly equal routing. In order to control the reconfiguration process of the FPGA, a Reconfiguration Engine suited to the specific requirements set by the proposed architectures was also proposed. Therefore, in addition to controlling the reconfiguration port, the Reconfiguration Engine has been enhanced with the online relocation ability, which allows employing a unique configuration bitstream for all the positions where the module may be placed in the device. Differently to the existing relocating solutions, which are based on bitstream parsers, the proposed approach is based on the online composition of bitstreams. This strategy allows increasing the speed of the process, while the length of partial bitstreams is also reduced. The height of the reconfigurable modules can be lower than the height of a clock region. The Reconfiguration Engine manages the merging process of the new and the existing configuration frames within each clock region. The process of scaling up and down the hardware cores also benefits from this technique. A direct link to an external memory where partial bitstreams can be stored has been also implemented. In order to accelerate the reconfiguration process, the ICAP has been overclocked over the speed reported by the manufacturer. In the case of Virtex-5, even though the maximum frequency of the ICAP is reported to be 100 MHz, valid operations at 250 MHz have been achieved, including the online relocation process. Portability of the reconfiguration solution to today's and probably, future FPGAs, has been also considered. The reconfiguration engine can be also used to inject faults in real hardware devices, and this way being able to evaluate the fault tolerance offered by the reconfigurable architectures. Faults are emulated by introducing partial bitstreams intentionally modified to provide erroneous functionality. To prove the validity and the benefits offered by the proposed architectures, two demonstration application lines have been envisaged. First, scalable architectures have been employed to develop an evolvable hardware platform with adaptability, fault tolerance and scalability properties. Second, they have been used to implement a scalable deblocking filter suited to scalable video coding. Evolvable Hardware is the use of evolutionary algorithms to design hardware in an autonomous way, exploiting the flexibility offered by reconfigurable devices. In this case, processing elements composing the architecture are selected from a presynthesized library of processing elements, according to the decisions taken by the algorithm, instead of being decided at design time. This way, the configuration of the array may change as run-time environmental conditions do, achieving autonomous control of the dynamic reconfiguration process. Thus, the self-optimization property is added to the native self-configurability of the dynamically scalable architectures. In addition, evolvable hardware adaptability inherently offers self-healing features. The proposal has proved to be self-tolerant, since it is able to self-recover from both transient and cumulative permanent faults. The proposed evolvable architecture has been used to implement noise removal image filters. Scalability has been also exploited in this application. Scalable evolvable hardware architectures allow the autonomous adaptation of the processing cores to a fluctuating amount of resources available in the system. Thus, it constitutes an example of the dynamic quality scalability tackled in this thesis. Two variants have been proposed. The first one consists in a single dynamically scalable evolvable core, and the second one contains a variable number of processing cores. Scalable video is a flexible approach for video compression, which offers scalability at different levels. Differently to non-scalable codecs, a scalable video bitstream can be decoded with different levels of quality, spatial or temporal resolutions, by discarding the undesired information. The interest in this technology has been fostered by the development of the Scalable Video Coding (SVC) standard, as an extension of H.264/AVC. In order to exploit all the flexibility offered by the standard, it is necessary to adapt the characteristics of the decoder to the requirements of each client during run-time. The use of dynamically scalable architectures is proposed in this thesis with this aim. The deblocking filter algorithm is the responsible of improving the visual perception of a reconstructed image, by smoothing blocking artifacts generated in the encoding loop. This is one of the most computationally intensive tasks of the standard, and furthermore, it is highly dependent on the selected scalability level in the decoder. Therefore, the deblocking filter has been selected as a proof of concept of the implementation of dynamically scalable architectures for video compression. The proposed architecture allows the run-time addition or removal of computational units working in parallel to change its level of parallelism, following a wavefront computational pattern. Scalable architecture is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, the macroblock filtering order is modified accordingly. The proposed pattern is based on the division of the macroblock processing into two independent stages, corresponding to the horizontal and vertical filtering of the blocks within the macroblock. The main contributions of this thesis are: - The use of highly parallel, modular, regular and local architectures to implement dynamically reconfigurable processing IP cores, for data intensive applications with flexibility requirements. - The use of two-dimensional mesh-type arrays as architectural templates to build dynamically reconfigurable IP cores, with a scalable footprint. The proposal consists in generic architectural templates, which can be tuned to solve different computational problems. •A design flow and a tool targeting the design of DPR systems, focused on highly parallel, modular and local architectures. - An inter-module communication strategy, which does not introduce delay or area overhead, named Virtual Borders. - A custom and flexible router to solve the routing conflicts as well as the inter-module communication problems, appearing during the design of DPR systems. - An algorithm addressing the optimization of systems composed of multiple scalable cores, which size can be decided individually, to optimize the system parameters. It is based on a model known as the multi-dimensional multi-choice Knapsack problem. - A reconfiguration engine tailored to the requirements of highly regular and modular architectures. It combines a high reconfiguration throughput with run-time module relocation capabilities, including the support for sub-clock reconfigurable regions and the replication in multiple positions. - A fault injection mechanism which takes advantage of the system reconfiguration engine, as well as the modularity of the proposed reconfigurable architectures, to evaluate the effects of transient and permanent faults in these architectures. - The demonstration of the possibilities of the architectures proposed in this thesis to implement evolvable hardware systems, while keeping a high processing throughput. - The implementation of scalable evolvable hardware systems, which are able to adapt to the fluctuation of the amount of resources available in the system, in an autonomous way. - A parallelization strategy for the H.264/AVC and SVC deblocking filter, which reduces the number of macroblock cycles needed to process the whole frame. - A dynamically scalable architecture that permits the implementation of a novel deblocking filter module, fully compliant with the H.264/AVC and SVC standards, which exploits the macroblock level parallelism of the algorithm. This document is organized in seven chapters. In the first one, an introduction to the technology framework of this thesis, specially focused on dynamic and partial reconfiguration, is provided. The need for the dynamically scalable processing architectures proposed in this work is also motivated in this chapter. In chapter 2, dynamically scalable architectures are described. Description includes most of the architectural contributions of this work. The design flow tailored to the scalable architectures, together with the DREAMs tool provided to implement them, are described in chapter 3. The reconfiguration engine is described in chapter 4. The use of the proposed scalable archtieectures to implement evolvable hardware systems is described in chapter 5, while the scalable deblocking filter is described in chapter 6. Final conclusions of this thesis, and the description of future work, are addressed in chapter 7.

Minimum time control for multiphase buck converter: analysis and application

The combination of minimum time control and multiphase converter is a favorable option for dc-dc converters in applications where output voltage variation is required, such as RF amplifiers and dynamic voltage scaling in microprocessors, due to their advantage of fast dynamic response. In this paper, an improved minimum time control approach for multiphase buck converter that is based on charge balance technique, aiming at fast output voltage transition is presented. Compared with the traditional method, the proposed control takes into account the phase delay and current ripple in each phase. Therefore, by investigating the behavior of multiphase converter during voltage transition, it resolves the problem of current unbalance after the transient, which can lead to long settling time of the output voltage. The restriction of this control is that the output voltage that the converter can provide is related to the number of the phases, because only the duty cycles at which the multiphase converter has total ripple cancellation are used in this approach. The model of the proposed control is introduced, and the design constraints of the buck converters filter for this control are discussed. In order to prove the concept, a four-phase buck converter is implemented and the experimental results that validate the proposed control method are presented. The application of this control to RF envelope tracking is also presented in this paper.

A self-timed multipurpose delay sensor for field programmable gate arrays (FPGAs)

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor’s measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of ±0.67 °C, over the range of 20–100 °C, employing 20 logic elements with a 2-point calibration.

Controlled time of arrival feasibility analysis

Previous research studies and operational trials have shown that using the airborne Required Time of Arrival (RTA) function, an aircraft can individually achieve an assigned time to a metering or merge point accurately. This study goes a step further and investigates the application of RTA to a real sequence of arriving aircraft into Melbourne Australia. Assuming that the actual arrival times were Controlled Time of Arrivals (CTAs) assigned to each aircraft, the study examines if the airborne RTA solution would work. Three scenarios were compared: a baseline scenario being the actual flown trajectories in a two hour time-span into Melbourne, a scenario in which the sequential landing slot times of the baseline scenario were assigned as CTAs and a third scenario in which the landing slots could be freely redistributed to the inbound traffic as CTAs. The research found that pressure on the terminal area would sometimes require aircraft to lose more time than possible through the RTA capability. Using linear holding as an additional measure to absorb extensive delays, up to 500NM (5%) of total track reduction and 1300kg (3%) of total fuel consumption could be saved in the scenario with landing slots freely distributed as CTAs, compared to the baseline scenario. Assigning CTAs in an arrival sequence requires the ground system to have an accurate trajectory predictor to propose additional delay measures (path stretching, linear holding) if necessary. Reducing the achievable time window of the aircraft to add control margin to the RTA function, had a negative impact and increased the amount of intervention other than speed control required to solve the sequence. It was concluded that the RTA capability is not a complete solution but merely a tool to assist in managing the increasing complexity of air traffic.

Large aperture antenna arrays with subband delay compensation for reception of wideband satellite signals

Con esta disertación se pretenden resolver algunos de los problemas encontrados actualmente en la recepción de señales de satélites bajo dos escenarios particularmente exigentes: comunicaciones de Espacio Profundo y en banda Ka. Las comunicaciones con sondas de Espacio Profundo necesitan grandes aperturas en tierra para poder incrementar la velocidad de datos. La opción de usar antennas con diámetro mayor de 35 metros tiene serios problemas, pues antenas tan grandes son caras de mantener, difíciles de apuntar, pueden tener largos tiempo de reparación y además tienen una efeciencia decreciente a medida que se utilizan bandas más altas. Soluciones basadas en agrupaciones de antenas de menor tamaño (12 ó 35 metros) son mas ecónomicas y factibles técnicamente. Las comunicaciones en banda Ka tambien pueden beneficiarse de la combinación de múltiples antennas. Las antenas de menor tamaño son más fáciles de apuntar y además tienen un campo de visión mayor. Además, las técnicas de diversidad espacial pueden ser reemplazadas por una combinación de antenas para así incrementar el margen del enlace. La combinación de antenas muy alejadas sobre grandes anchos de banda, bien por recibir una señal de banda ancha o múltiples de banda estrecha, es complicada técnicamente. En esta disertación se demostrará que el uso de conformador de haz en el dominio de la frecuencia puede ayudar a relajar los requisitos de calibración y, al mismo tiempo, proporcionar un mayor campo de visión y mayores capacidades de ecualización. Para llevar esto a cabo, el trabajo ha girado en torno a tres aspectos fundamentales. El primero es la investigación bibliográfica del trabajo existente en este campo. El segundo es el modelado matemático del proceso de combinación y el desarrollo de nuevos algoritmos de estimación de fase y retardo. Y el tercero es la propuesta de nuevas aplicaciones en las que usar estas técnicas. La investigación bibliográfica se centra principalmente en los capítulos 1, 2, 4 y 5. El capítulo 1 da una breve introducción a la teoría de combinación de antenas de gran apertura. En este capítulo, los principales campos de aplicación son descritos y además se establece la necesidad de compensar retardos en subbandas. La teoría de bancos de filtros se expone en el capítulo 2; se selecciona y simula un banco de filtros modulado uniformemente con fase lineal. Las propiedades de convergencia de varios filtros adaptativos se muestran en el capítulo 4. Y finalmente, las técnicas de estimación de retardo son estudiadas y resumidas en el capítulo 5. Desde el punto de vista matemático, las principales contribución de esta disertación han sido: • Sección 3.1.4. Cálculo de la desviación de haz de un conformador de haz con compensación de retardo en pasos discretos en frecuencia intermedia. • Sección 3.2. Modelo matemático de un conformador de haz en subbandas. • Sección 3.2.2. Cálculo de la desviación de haz de un conformador de haz en subbandas con un buffer de retardo grueso. • Sección 3.2.4. Análisis de la influencia de los alias internos en la compensación en subbandas de retardo y fase. • Sección 3.2.4.2. Cálculo de la desviación de haz de un conformador de haz con compensación de retardo en subbandas. • Sección 3.2.6. Cálculo de la ganancia de relación señal a ruido de la agrupación de antenas en cada una de las subbandas. • Sección 3.3.2. Modelado de la función de transferencia de la agrupación de antenas bajo errores de estimación de retardo. • Sección 3.3.3. Modelado de los efectos de derivas de fase y retardo entre actualizaciones de las estimaciones. • Sección 3.4. Cálculo de la directividad de la agrupación de antenas con y sin compensación de retardos en subbandas. • Sección 5.2.6. Desarrollo de un algorimo para estimar la fase y el retardo entre dos señales a partir de su descomposición de subbandas bajo entornos estacionarios. • Sección 5.5.1. Desarrollo de un algorimo para estimar la fase, el retardo y la deriva de retardo entre dos señales a partir de su descomposición de subbandas bajo entornos no estacionarios. Las aplicaciones que se pueden beneficiar de estas técnicas son descritas en el capítulo 7: • Sección 6.2. Agrupaciones de antenas para comunicaciones de Espacio Profundo con capacidad multihaz y sin requisitos de calibración geométrica o de retardo de grupo. • Sección 6.2.6. Combinación en banda ancha de antenas con separaciones de miles de kilómetros, para recepción de sondas de espacio profundo. • Secciones 6.4 and 6.3. Combinación de estaciones remotas en banda Ka en escenarios de diversidad espacial, para recepción de satélites LEO o GEO. • Sección 6.3. Recepción de satélites GEO colocados con arrays de antenas multihaz. Las publicaciones a las que ha dado lugar esta tesis son las siguientes • A. Torre. Wideband antenna arraying over long distances. Interplanetary Progress Report, 42-194:1–18, 2013. En esta pulicación se resumen los resultados de las secciones 3.2, 3.2.2, 3.3.2, los algoritmos en las secciones 5.2.6, 5.5.1 y la aplicación destacada en 6.2.6. • A. Torre. Reception of wideband signals from geostationary collocated satellites with antenna arrays. IET Communications, Vol. 8, Issue 13:2229–2237, September, 2014. En esta segunda se muestran los resultados de la sección 3.2.4, el algoritmo en la sección 5.2.6.1 , y la aplicación mostrada en 6.3. ABSTRACT This dissertation is an attempt to solve some of the problems found nowadays in the reception of satellite signals under two particular challenging scenarios: Deep Space and Ka-band communications. Deep Space communications require from larger apertures on ground in order to increase the data rate. The option of using single dishes with diameters larger than 35 meters has severe drawbacks. Such antennas are expensive to maintain, prone to long downtimes, difficult to point and have a degraded performance in high frequency bands. The array solution, either with 12 meter or 35 meter antennas is deemed to be the most economically and technically feasible solution. Ka-band communications can also benefit from antenna arraying technology. The smaller aperture antennas that make up the array are easier to point and have a wider field of view allowing multiple simultaneous beams. Besides, site diversity techniques can be replaced by pure combination in order to increase link margin. Combination of far away antennas over a large bandwidth, either because a wideband signal or multiple narrowband signals are received, is a demanding task. This dissertation will show that the use of frequency domain beamformers with subband delay compensation can help to ease calibration requirements and, at the same time, provide with a wider field of view and enhanced equalization capabilities. In order to do so, the work has been focused on three main aspects. The first one is the bibliographic research of previous work on this subject. The second one is the mathematical modeling of the array combination process and the development of new phase/delay estimation algorithms. And the third one is the proposal of new applications in which these techniques can be used. Bibliographic research is mainly done in chapters 1, 2, 4 and 5. Chapter 1 gives a brief introduction to previous work in the field of large aperture antenna arraying. In this chapter, the main fields of application are described and the need for subband delay compensation is established. Filter bank theory is shown in chapter 2; a linear phase uniform modulated filter bank is selected and simulated under diverse conditions. The convergence properties of several adaptive filters are shown in chapter 4. Finally, delay estimation techniques are studied and summarized in chapter 5. From a mathematical point of view, the main contributions of this dissertation have been: • Section 3.1.4. Calculation of beam squint of an IF beamformer with delay compensation at discrete time steps. • Section 3.2. Establishment of a mathematical model of a subband beamformer. • Section 3.2.2. Calculation of beam squint in a subband beamformer with a coarse delay buffer. • Section 3.2.4. Analysis of the influence of internal aliasing on phase and delay subband compensation. • Section 3.2.4.2. Calculation of beam squint of a beamformer with subband delay compensation. • Section 3.2.6. Calculation of the array SNR gain at each of the subbands. • Section 3.3.2. Modeling of the transfer function of an array subject to delay estimation errors. • Section 3.3.3. Modeling of the effects of phase and delay drifts between estimation updates. • Section 3.4. Calculation of array directivity with and without subband delay compensation. • Section 5.2.6. Development of an algorithm to estimate relative delay and phase between two signals from their subband decomposition in stationary environments. • Section 5.5.1. Development of an algorithm to estimate relative delay rate, delay and phase between two signals from their subband decomposition in non stationary environments. The applications that can benefit from these techniques are described in chapter 7: • Section 6.2. Arrays of antennas for Deep Space communications with multibeam capacity and without geometric or group delay calibration requirement. • Section 6.2.6. Wideband antenna arraying over long distances, in the range of thousands of kilometers, for reception of Deep Space probes. • Sections 6.4 y 6.3. Combination of remote stations in Ka-band site diversity scenarios for reception of LEO or GEO satellites. • Section 6.3. Reception of GEO collocated satellites with multibeam antenna arrays. The publications that have been made from the work in this dissertation are • A. Torre. Wideband antenna arraying over long distances. Interplanetary Progress Report, 42-194:1–18, 2013. This article shows the results in sections 3.2, 3.2.2, 3.3.2, the algorithms in sections 5.2.6, 5.5.1 and the application in section 6.2.6. • A. Torre. Reception of wideband signals from geostationary collocated satellites with antenna arrays. IET Communications, Vol. 8, Issue 13:2229–2237, September, 2014. This second article shows among others the results in section 3.2.4, the algorithm in section 5.2.6.1 , and the application in section 6.3.

An Implemented of a Real-Time Experimental Setup for Robotic Teleoperation System

The development of this work presents the implementation of an experimental platform, which will permit to investigate on a methodology for the design and analysis of a teleoperated system, considering the delay in the communication channel. The project has been developed in partnership with the laboratory of Automatic and Robotics of the Universidad Politécnica de Madrid and the Laboratory at the Centro de Tecnologías Avanzadas de Manufactura at the Pontificia Universidad Católica del Perú. The mechanical structure of the arm that is located in the remote side has been built and the electric servomechanism has been mounted to control their movement. The experimental test of the Teleoperation system has been developed. The PC104 card commands the power interface and sensors of the DC motor of each articulation of the arm. Has developed the drives for the management of the operations of the master and the slave: send/reception of position, speed, acceleration and current data through a CAN network. The programs for the interconnection through a LAN network, between the Windows Operating System and the Real-time Operating System (QNX), has been developed. The utility of the developed platform (hardware and software) has been demonstrated.