An improved bit parallel exact maximum clique algorithm

This paper describes new improvements for BB-MaxClique (San Segundo et al. in Comput Oper Resour 38(2):571–581, 2011 ), a leading maximum clique algorithm which uses bit strings to efficiently compute basic operations during search by bit masking. Improvements include a recently described recoloring strategy in Tomita et al. (Proceedings of the 4th International Workshop on Algorithms and Computation. Lecture Notes in Computer Science, vol 5942. Springer, Berlin, pp 191–203, 2010 ), which is now integrated in the bit string framework, as well as different optimization strategies for fast bit scanning. Reported results over DIMACS and random graphs show that the new variants improve over previous BB-MaxClique for a vast majority of cases. It is also established that recoloring is mainly useful for graphs with high densities.

SLBN: A Scalable Max-min Fair Algorithm for Rate-Based Explicit Congestion Control

The growth of the Internet has increased the need for scalable congestion control mechanisms in high speed networks. In this context, we propose a rate-based explicit congestion control mechanism with which the sources are provided with the rate at which they can transmit. These rates are computed with a distributed max-min fair algorithm, SLBN. The novelty of SLBN is that it combines two interesting features not simultaneously present in existing proposals: scalability and fast convergence to the max-min fair rates, even under high session churn. SLBN is scalable because routers only maintain a constant amount of state information (only three integer variables per link) and only incur a constant amount of computation per protocol packet, independently of the number of sessions that cross the router. Additionally, SLBN does not require processing any data packet, and it converges independently of sessions' RTT. Finally, by design, the protocol is conservative when assigning rates, even in the presence of high churn, which helps preventing link overshoots in transient periods. We claim that, with all these features, our mechanism is a good candidate to be used in real deployments.

Advanced Control Strategies for a 6 DoF Hydraulic Parallel Robot Based on the Dynamic Model

Nowadays robots have made their way into real applications that were prohibitive and unthinkable thirty years ago. This is mainly due to the increase in power computations and the evolution in the theoretical field of robotics and control. Even though there is plenty of information in the current literature on this topics, it is not easy to find clear concepts of how to proceed in order to design and implement a controller for a robot. In general, the design of a controller requires of a complete understanding and knowledge of the system to be controlled. Therefore, for advanced control techniques the systems must be first identified. Once again this particular objective is cumbersome and is never straight forward requiring of great expertise and some criteria must be adopted. On the other hand, the particular problem of designing a controller is even more complex when dealing with Parallel Manipulators (PM), since their closed-loop structures give rise to a highly nonlinear system. Under this basis the current work is developed, which intends to resume and gather all the concepts and experiences involve for the control of an Hydraulic Parallel Manipulator. The main objective of this thesis is to provide a guide remarking all the steps involve in the designing of advanced control technique for PMs. The analysis of the PM under study is minced up to the core of the mechanism: the hydraulic actuators. The actuators are modeled and experimental identified. Additionally, some consideration regarding traditional PID controllers are presented and an adaptive controller is finally implemented. From a macro perspective the kinematic and dynamic model of the PM are presented. Based on the model of the system and extending the adaptive controller of the actuator, a control strategy for the PM is developed and its performance is analyzed with simulation.

Multiphase Design and Control Techniques Applied to a Forward Micro-Inverter

En la última década la potencia instalada de energía solar fotovoltaica ha crecido una media de un 49% anual y se espera que alcance el 16%del consumo energético mundial en el año 2050. La mayor parte de estas instalaciones se corresponden con sistemas conectados a la red eléctrica y un amplio porcentaje de ellas son instalaciones domésticas o en edificios. En el mercado ya existen diferentes arquitecturas para este tipo de instalaciones, entre las que se encuentras los módulos AC. Un módulo AC consiste en un inversor, también conocido como micro-inversor, que se monta en la parte trasera de un panel o módulo fotovoltaico. Esta tecnología ofrece modularidad, redundancia y la extracción de la máxima potencia de cada panel solar de la instalación. Además, la expansión de esta tecnología posibilitará una reducción de costes asociados a las economías de escala y a la posibilidad de que el propio usuario pueda componer su propio sistema. Sin embargo, el micro-inversor debe ser capaz de proporcionar una ganancia de tensión adecuada para conectar el panel solar directamente a la red, mientras mantiene un rendimiento aceptable en un amplio rango de potencias. Asimismo, los estándares de conexión a red deber ser satisfechos y el tamaño y el tiempo de vida del micro-inversor son factores que han de tenerse siempre en cuenta. En esta tesis se propone un micro-inversor derivado de la topología “forward” controlado en el límite entre los modos de conducción continuo y discontinuo (BCM por sus siglas en inglés). El transformador de la topología propuesta mantiene la misma estructura que en el convertidor “forward” clásico y la utilización de interruptores bidireccionales en el secundario permite la conexión directa del inversor a la red. Asimismo el método de control elegido permite obtener factor de potencia cercano a la unidad con una implementación sencilla. En la tesis se presenta el principio de funcionamiento y los principales aspectos del diseño del micro-inversor propuesto. Con la idea de mantener una solución sencilla y de bajo coste, se ha seleccionado un controlador analógico que está originalmente pensado para controlar un corrector del factor de potencia en el mismo modo de conducción que el micro-inversor “forward”. La tesis presenta las principales modificaciones necesarias, con especial atención a la detección del cruce por cero de la corriente (ZCD por sus siglas en inglés) y la compatibilidad del controlador con la inclusión de un algoritmo de búsqueda del punto de máxima potencia (MPPT por sus siglas en inglés). Los resultados experimentales muestran las limitaciones de la implementación elegida e identifican al transformador como el principal contribuyente a las pérdidas del micro-inversor. El principal objetivo de esta tesis es contribuir a la aplicación de técnicas de control y diseño de sistemas multifase en micro-inversores fotovoltaicos. En esta tesis se van a considerar dos configuraciones multifase diferentes aplicadas al micro-inversor “forward” propuesto. La primera consiste en una variación con conexión paralelo-serie que permite la utilización de transformadores con una relación de vueltas baja, y por tanto bien acoplados, para conseguir una ganancia de tensión adecuada con un mejor rendimiento. Esta configuración emplea el mismo control BCM cuando la potencia extraída del panel solar es máxima. Este método de control implica que la frecuencia de conmutación se incrementa considerablemente cuando la potencia decrece, lo que compromete el rendimiento. Por lo tanto y con la intención de mantener unos bueno niveles de rendimiento ponderado, el micro-inversor funciona en modo de conducción discontinuo (DCM, por sus siglas en inglés) cuando la potencia extraía del panel solar es menor que la máxima. La segunda configuración multifase considerada en esta tesis es la aplicación de la técnica de paralelo con entrelazado. Además se han considerado dos técnicas diferentes para decidir el número de fases activas: dependiendo de la potencia continua extraída del panel solar y dependiendo de la potencia instantánea demandada por el micro-inversor. La aplicación de estas técnicas es interesante en los sistemas fotovoltaicos conectados a la red eléctrica por la posibilidad que brindan de obtener un rendimiento prácticamente plano en un amplio rango de potencia. Las configuraciones con entrelazado se controlan en DCM para evitar la necesidad de un control de corriente, lo que es importante cuando el número de fases es alto. Los núcleos adecuados para todas las configuraciones multifase consideradas se seleccionan usando el producto de áreas. Una vez seleccionados los núcleos se ha realizado un diseño detallado de cada uno de los transformadores. Con la información obtenida de los diseños y los resultados de simulación, se puede analizar el impacto que el número de transformadores utilizados tiene en el tamaño y el rendimiento de las distintas configuraciones. Los resultados de este análisis, presentado en esta tesis, se utilizan posteriormente para comparar las distintas configuraciones. Muchas otras topologías se han presentado en la literatura para abordar los diferentes aspectos a considerar en los micro-inversores, que han sido presentados anteriormente. La mayoría de estas topologías utilizan un transformador de alta frecuencia para solventar el salto de tensión y evitar problemas de seguridad y de puesta a tierra. En cualquier caso, es interesante evaluar si topologías sin aislamiento galvánico son aptas para su utilización como micro-inversores. En esta tesis se presenta una revisión de inversores con capacidad de elevar tensión, que se comparan bajo las mismas especificaciones. El objetivo es proporcionar la información necesaria para valorar si estas topologías son aplicables en los módulos AC. Las principales contribuciones de esta tesis son: • La aplicación del control BCM a un convertidor “forward” para obtener un micro-inversor de una etapa sencillo y de bajo coste. • La modificación de dicho micro-inversor con conexión paralelo-series de transformadores que permite reducir la corriente de los semiconductores y una ganancia de tensión adecuada con transformadores altamente acoplados. • La aplicación de técnicas de entrelazado y decisión de apagado de fases en la puesta en paralelo del micro-inversor “forward”. • El análisis y la comparación del efecto en el tamaño y el rendimiento del incremento del número de transformadores en las diferentes configuraciones multifase. • La eliminación de las medidas y los lazos de control de corriente en las topologías multifase con la utilización del modo de conducción discontinuo y un algoritmo MPPT sin necesidad de medida de corriente. • La recopilación y comparación bajo las mismas especificaciones de topologías inversoras con capacidad de elevar tensión, que pueden ser adecuadas para la utilización como micro-inversores. Esta tesis está estructurada en seis capítulos. El capítulo 1 presenta el marco en que se desarrolla la tesis así como el alcance de la misma. En el capítulo 2 se recopilan las topologías existentes de micro-invesores con aislamiento y aquellas sin aislamiento cuya implementación en un módulo AC es factible. Asimismo se presenta la comparación entre estas topologías bajo las mismas especificaciones. El capítulo 3 se centra en el micro-inversor “forward” que se propone originalmente en esta tesis. La aplicación de las técnicas multifase se aborda en los capítulos 4 y 5, en los que se presentan los análisis en función del número de transformadores. El capítulo está orientado a la propuesta paralelo-serie mientras que la configuración con entrelazado se analiza en el capítulo 5. Por último, en el capítulo 6 se presentan las contribuciones de esta tesis y los trabajos futuros. ABSTRACT In the last decade the photovoltaic (PV) installed power increased with an average growth of 49% per year and it is expected to cover the 16% of the global electricity consumption by 2050. Most of the installed PV power corresponds to grid-connected systems, with a significant percentage of residential installations. In these PV systems, the inverter is essential since it is the responsible of transferring into the grid the extracted power from the PV modules. Several architectures have been proposed for grid-connected residential PV systems, including the AC-module technology. An AC-module consists of an inverter, also known as micro-inverter, which is attached to a PV module. The AC-module technology offers modularity, redundancy and individual MPPT of each module. In addition, the expansion of this technology will enable the possibility of economies of scale of mass market and “plug and play” for the user, thus reducing the overall cost of the installation. However, the micro-inverter must be able to provide the required voltage boost to interface a low voltage PV module to the grid while keeping an acceptable efficiency in a wide power range. Furthermore, the quality standards must be satisfied and size and lifetime of the solutions must be always considered. In this thesis a single-stage forward micro-inverter with boundary mode operation is proposed to address the micro-inverter requirements. The transformer in the proposed topology remains as in the classic forward converter and bidirectional switches in the secondary side allows direct connection to the grid. In addition the selected control strategy allows high power factor current with a simple implementation. The operation of the topology is presented and the main design issues are introduced. With the intention to propose a simple and low-cost solution, an analog controller for a PFC operated in boundary mode is utilized. The main necessary modifications are discussed, with the focus on the zero current detection (ZCD) and the compatibility of the controller with a MPPT algorithm. The experimental results show the limitations of the selected analog controller implementation and the transformer is identified as a main losses contributor. The main objective of this thesis is to contribute in the application of control and design multiphase techniques to the PV micro-inverters. Two different multiphase configurations have been applied to the forward micro-inverter proposed in this thesis. The first one consists of a parallel-series connected variation which enables the use of low turns ratio, i.e. well coupled, transformers to achieve a proper voltage boost with an improved performance. This multiphase configuration implements BCM control at maximum load however. With this control method the switching frequency increases significantly for light load operation, thus jeopardizing the efficiency. Therefore, in order to keep acceptable weighted efficiency levels, DCM operation is selected for low power conditions. The second multiphase variation considered in this thesis is the interleaved configuration with two different phase shedding techniques: depending on the DC power extracted from the PV panel, and depending on the demanded instantaneous power. The application of interleaving techniques is interesting in PV grid-connected inverters for the possibility of flat efficiency behavior in a wide power range. The interleaved variations of the proposed forward micro-inverter are operated in DCM to avoid the current loop, which is important when the number of phases is large. The adequate transformer cores for all the multiphase configurations are selected according to the area product parameter and a detailed design of each required transformer is developed. With this information and simulation results, the impact in size and efficiency of the number of transformer used can be assessed. The considered multiphase topologies are compared in this thesis according to the results of the introduced analysis. Several other topological solutions have been proposed to solve the mentioned concerns in AC-module application. The most of these solutions use a high frequency transformer to boost the voltage and avoid grounding and safety issues. However, it is of interest to assess if the non-isolated topologies are suitable for AC-module application. In this thesis a review of transformerless step-up inverters is presented. The compiled topologies are compared using a set benchmark to provide the necessary information to assess whether non-isolated topologies are suitable for AC-module application. The main contributions of this thesis are: • The application of the boundary mode control with constant off-time to a forward converter, to obtain a simple and low-cost single-stage forward micro-inverter. • A modification of the forward micro-inverter with primary-parallel secondary-series connected transformers to reduce the current stress and improve the voltage gain with highly coupled transformers. •The application of the interleaved configuration with different phase shedding strategies to the proposed forward micro-inverter. • An analysis and comparison of the influence in size and efficiency of increasing the number of transformers in the parallel-series and interleaved multiphase configurations. • Elimination of the current loop and current measurements in the multiphase topologies by adopting DCM operation and a current sensorless MPPT. • A compilation and comparison with the same specifications of suitable non-isolated step-up inverters. This thesis is organized in six chapters. In Chapter 1 the background of single-phase PV-connected systems is discussed and the scope of the thesis is defined. Chapter 2 compiles the existing solutions for isolated micro-inverters and transformerless step-up inverters suitable for AC-module application. In addition, the most convenient non-isolated inverters are compared using a defined benchmark. Chapter 3 focuses on the originally proposed single-stage forward micro-inverter. The application of multiphase techniques is addressed in Chapter 4 and Chapter 5, and the impact in different parameters of increasing the number of phases is analyzed. In Chapter 4 an original primary-parallel secondary-series variation of the forward micro-inverter is presented, while Chapter 5 focuses on the application of the interleaved configuration. Finally, Chapter 6 discusses the contributions of the thesis and the future work.

B-Neck: A Distributed and Quiescent Max-Min Fair Algorithm

The problem of fairly distributing the capacity of a network among a set of sessions has been widely studied. In this problem, each session connects via a single path a source and a destination, and its goal is to maximize its assigned transmission rate (i.e., its throughput). Since the links of the network have limited bandwidths, some criterion has to be defined to fairly distribute their capacity among the sessions. A popular criterion is max-min fairness that, in short, guarantees that each session i gets a rate λi such that no session s can increase λs without causing another session s' to end up with a rate λs/ <; λs. Many max-min fair algorithms have been proposed, both centralized and distributed. However, to our knowledge, all proposed distributed algorithms require control data being continuously transmitted to recompute the max-min fair rates when needed (because none of them has mechanisms to detect convergence to the max-min fair rates). In this paper we propose B-Neck, a distributed max-min fair algorithm that is also quiescent. This means that, in absence of changes (i.e., session arrivals or departures), once the max min rates have been computed, B-Neck stops generating network traffic. Quiescence is a key design concept of B-Neck, because B-Neck routers are capable of detecting and notifying changes in the convergence conditions of max-min fair rates. As far as we know, B-Neck is the first distributed max-min fair algorithm that does not require a continuous injection of control traffic to compute the rates. The correctness of B-Neck is formally proved, and extensive simulations are conducted. In them, it is shown that B-Neck converges relatively fast and behaves nicely in presence of sessions arriving and departing.

New methods for the estimation of Takagi-Sugeno model based extended Kalman filter and its applications to optimal control for nonlinear systems

This paper describes new approaches to improve the local and global approximation (matching) and modeling capability of Takagi–Sugeno (T-S) fuzzy model. The main aim is obtaining high function approximation accuracy and fast convergence. The main problem encountered is that T-S identification method cannot be applied when the membership functions are overlapped by pairs. This restricts the application of the T-S method because this type of membership function has been widely used during the last 2 decades in the stability, controller design of fuzzy systems and is popular in industrial control applications. The approach developed here can be considered as a generalized version of T-S identification method with optimized performance in approximating nonlinear functions. We propose a noniterative method through weighting of parameters approach and an iterative algorithm by applying the extended Kalman filter, based on the same idea of parameters’ weighting. We show that the Kalman filter is an effective tool in the identification of T-S fuzzy model. A fuzzy controller based linear quadratic regulator is proposed in order to show the effectiveness of the estimation method developed here in control applications. An illustrative example of an inverted pendulum is chosen to evaluate the robustness and remarkable performance of the proposed method locally and globally in comparison with the original T-S model. Simulation results indicate the potential, simplicity, and generality of the algorithm. An illustrative example is chosen to evaluate the robustness. In this paper, we prove that these algorithms converge very fast, thereby making them very practical to use.

A parallel implementation of 3D Zernike moment analysis

Zernike polynomials are a well known set of functions that find many applications in image or pattern characterization because they allow to construct shape descriptors that are invariant against translations, rotations or scale changes. The concepts behind them can be extended to higher dimension spaces, making them also fit to describe volumetric data. They have been less used than their properties might suggest due to their high computational cost. We present a parallel implementation of 3D Zernike moments analysis, written in C with CUDA extensions, which makes it practical to employ Zernike descriptors in interactive applications, yielding a performance of several frames per second in voxel datasets about 2003 in size. In our contribution, we describe the challenges of implementing 3D Zernike analysis in a general-purpose GPU. These include how to deal with numerical inaccuracies, due to the high precision demands of the algorithm, or how to deal with the high volume of input data so that it does not become a bottleneck for the system.

Particle methods parallel implementations by GP-GPU strategies

This paper outlines the problems found in the parallelization of SPH (Smoothed Particle Hydrodynamics) algorithms using Graphics Processing Units. Different results of some parallel GPU implementations in terms of the speed-up and the scalability compared to the CPU sequential codes are shown. The most problematic stage in the GPU-SPH algorithms is the one responsible for locating neighboring particles and building the vectors where this information is stored, since these specific algorithms raise many dificulties for a data-level parallelization. Because of the fact that the neighbor location using linked lists does not show enough data-level parallelism, two new approaches have been pro- posed to minimize bank conflicts in the writing and subsequent reading of the neighbor lists. The first strategy proposes an efficient coordination between CPU-GPU, using GPU algorithms for those stages that allow a straight forward parallelization, and sequential CPU algorithms for those instructions that involve some kind of vector reduction. This coordination provides a relatively orderly reading of the neighbor lists in the interactions stage, achieving a speed-up factor of x47 in this stage. However, since the construction of the neighbor lists is quite expensive, it is achieved an overall speed-up of x41. The second strategy seeks to maximize the use of the GPU in the neighbor's location process by executing a specific vector sorting algorithm that allows some data-level parallelism. Al- though this strategy has succeeded in improving the speed-up on the stage of neighboring location, the global speed-up on the interactions stage falls, due to inefficient reading of the neighbor vectors. Some changes to these strategies are proposed, aimed at maximizing the computational load of the GPU and using the GPU texture-units, in order to reach the maximum speed-up for such codes. Different practical applications have been added to the mentioned GPU codes. First, the classical dam-break problem is studied. Second, the wave impact of the sloshing fluid contained in LNG vessel tanks is also simulated as a practical example of particle methods

Visual Servoing for the Robotenis System: a Strategy for a 3 DOF Parallel Robot to Hit a Ping-Pong Ball

This article describes a new visual servo control and strategies that are used to carry out dynamic tasks by the Robotenis platform. This platform is basically a parallel robot that is equipped with an acquisition and processing system of visual information, its main feature is that it has a completely open architecture control, and planned in order to design, implement, test and compare control strategies and algorithms (visual and actuated joint controllers). Following sections describe a new visual control strategy specially designed to track and intercept objects in 3D space. The results are compared with a controller shown in previous woks, where the end effector of the robot keeps a constant distance from the tracked object. In this work, the controller is specially designed in order to allow changes in the tracking reference. Changes in the tracking reference can be used to grip an object that is under movement, or as in this case, hitting a hanging Ping-Pong ball. Lyapunov stability is taken into account in the controller design.

Non-linear Control of an Autonomous Ground Vehicle

In this paper, in order to select a speed controller for a specific non-linear autonomous ground vehicle, proportional-integral-derivative (PID), Fuzzy, and linear quadratic regulator (LQR) controllers were designed. Here, in order to carry out the tuning of the above controllers, a multicomputer genetic algorithm (MGA) was designed. Then, the results of the MGA were used to parameterize the PID, Fuzzy and LQR controllers and to test them under laboratory conditions. Finally, a comparative analysis of the performance of the three controllers was conducted.

A methodology for granularity-based control of parallelism in logic programs

Several types of parallelism can be exploited in logic programs while preserving correctness and efficiency, i.e. ensuring that the parallel execution obtains the same results as the sequential one and the amount of work performed is not greater. However, such results do not take into account a number of overheads which appear in practice, such as process creation and scheduling, which can induce a slow-down, or, at least, limit speedup, if they are not controlled in some way. This paper describes a methodology whereby the granularity of parallel tasks, i.e. the work available under them, is efficiently estimated and used to limit parallelism so that the effect of such overheads is controlled. The run-time overhead associated with the approach is usually quite small, since as much work is done at compile time as possible. Also,a number of run-time optimizations are proposed. Moreover, a static analysis of the overhead associated with the granularity control process is performed in order to decide its convenience. The performance improvements resulting from the incorporation of grain size control are shown to be quite good, specially for systems with medium to large parallel execution overheads.

Energy and power aware scheduling algorithm modeling for battery powered embedded systems

Energy management has always been recognized as a challenge in mobile systems, especially in modern OS-based mobile systems where multi-functioning are widely supported. Nowadays, it is common for a mobile system user to run multiple applications simultaneously while having a target battery lifetime in mind for a specific application. Traditional OS-level power management (PM) policies make their best effort to save energy under performance constraint, but fail to guarantee a target lifetime, leaving the painful trading off between the total performance of applications and the target lifetime to the user itself. This thesis provides a new way to deal with the problem. It is advocated that a strong energy-aware PM scheme should first guarantee a user-specified battery lifetime to a target application by restricting the average power of those less important applications, and in addition to that, maximize the total performance of applications without harming the lifetime guarantee. As a support, energy, instead of CPU or transmission bandwidth, should be globally managed as the first-class resource by the OS. As the first-stage work of a complete PM scheme, this thesis presents the energy-based fair queuing scheduling, a novel class of energy-aware scheduling algorithms which, in combination with a mechanism of battery discharge rate restricting, systematically manage energy as the first-class resource with the objective of guaranteeing a user-specified battery lifetime for a target application in OS-based mobile systems. Energy-based fair queuing is a cross-application of the traditional fair queuing in the energy management domain. It assigns a power share to each task, and manages energy by proportionally serving energy to tasks according to their assigned power shares. The proportional energy use establishes proportional share of the system power among tasks, which guarantees a minimum power for each task and thus, avoids energy starvation on any task. Energy-based fair queuing treats all tasks equally as one type and supports periodical time-sensitive tasks by allocating each of them a share of system power that is adequate to meet the highest energy demand in all periods. However, an overly conservative power share is usually required to guarantee the meeting of all time constraints. To provide more effective and flexible support for various types of time-sensitive tasks in general purpose operating systems, an extra real-time friendly mechanism is introduced to combine priority-based scheduling into the energy-based fair queuing. Since a method is available to control the maximum time one time-sensitive task can run with priority, the power control and time-constraint meeting can be flexibly traded off. A SystemC-based test-bench is designed to assess the algorithms. Simulation results show the success of the energy-based fair queuing in achieving proportional energy use, time-constraint meeting, and a proper trading off between them. La gestión de energía en los sistema móviles está considerada hoy en día como un reto fundamental, notándose, especialmente, en aquellos terminales que utilizando un sistema operativo implementan múltiples funciones. Es común en los sistemas móviles actuales ejecutar simultaneamente diferentes aplicaciones y tener, para una de ellas, un objetivo de tiempo de uso de la batería. Tradicionalmente, las políticas de gestión de consumo de potencia de los sistemas operativos hacen lo que está en sus manos para ahorrar energía y satisfacer sus requisitos de prestaciones, pero no son capaces de proporcionar un objetivo de tiempo de utilización del sistema, dejando al usuario la difícil tarea de buscar un compromiso entre prestaciones y tiempo de utilización del sistema. Esta tesis, como contribución, proporciona una nueva manera de afrontar el problema. En ella se establece que un esquema de gestión de consumo de energía debería, en primer lugar, garantizar, para una aplicación dada, un tiempo mínimo de utilización de la batería que estuviera especificado por el usuario, restringiendo la potencia media consumida por las aplicaciones que se puedan considerar menos importantes y, en segundo lugar, maximizar las prestaciones globales sin comprometer la garantía de utilización de la batería. Como soporte de lo anterior, la energía, en lugar del tiempo de CPU o el ancho de banda, debería gestionarse globalmente por el sistema operativo como recurso de primera clase. Como primera fase en el desarrollo completo de un esquema de gestión de consumo, esta tesis presenta un algoritmo de planificación de encolado equitativo (fair queueing) basado en el consumo de energía, es decir, una nueva clase de algoritmos de planificación que, en combinación con mecanismos que restrinjan la tasa de descarga de una batería, gestionen de forma sistemática la energía como recurso de primera clase, con el objetivo de garantizar, para una aplicación dada, un tiempo de uso de la batería, definido por el usuario, en sistemas móviles empotrados. El encolado equitativo de energía es una extensión al dominio de la energía del encolado equitativo tradicional. Esta clase de algoritmos asigna una reserva de potencia a cada tarea y gestiona la energía sirviéndola de manera proporcional a su reserva. Este uso proporcional de la energía garantiza que cada tarea reciba una porción de potencia y evita que haya tareas que se vean privadas de recibir energía por otras con un comportamiento más ambicioso. Esta clase de algoritmos trata a todas las tareas por igual y puede planificar tareas periódicas en tiempo real asignando a cada una de ellas una reserva de potencia que es adecuada para proporcionar la mayor de las cantidades de energía demandadas por período. Sin embargo, es posible demostrar que sólo se consigue cumplir con los requisitos impuestos por todos los plazos temporales con reservas de potencia extremadamente conservadoras. En esta tesis, para proporcionar un soporte más flexible y eficiente para diferentes tipos de tareas de tiempo real junto con el resto de tareas, se combina un mecanismo de planificación basado en prioridades con el encolado equitativo basado en energía. En esta clase de algoritmos, gracias al método introducido, que controla el tiempo que se ejecuta con prioridad una tarea de tiempo real, se puede establecer un compromiso entre el cumplimiento de los requisitos de tiempo real y el consumo de potencia. Para evaluar los algoritmos, se ha diseñado en SystemC un banco de pruebas. Los resultados muestran que el algoritmo de encolado equitativo basado en el consumo de energía consigue el balance entre el uso proporcional a la energía reservada y el cumplimiento de los requisitos de tiempo real.

Towards granularity based control of parallelism in logic programs

Several types of parallelism can be exploited in logic programs while preserving correctness and efficiency, i.e. ensuring that the parallel execution obtains the same results as the sequential one and the amount of work performed is not greater. However, such results do not take into account a number of overheads which appear in practice, such as process creation and scheduling, which can induce a slow-down, or, at least, limit speedup, if they are not controlled in some way. This paper describes a methodology whereby the granularity of parallel tasks, i.e. the work available under them, is efficiently estimated and used to limit parallelism so that the effect of such overheads is controlled. The run-time overhead associated with the approach is usually quite small, since as much work is done at compile time as possible. Also, a number of run-time optimizations are proposed. Moreover, a static analysis of the overhead associated with the granularity control process is performed in order to decide its convenience. The performance improvements resulting from the incorporation of grain size control are shown to be quite good, specially for systems with médium to large parallel execution overheads.

Relating goal scheduling, precedence, and memory management in and-parallel execution of logic programs

The interactions among three important issues involved in the implementation of logic programs in parallel (goal scheduling, precedence, and memory management) are discussed. A simplified, parallel memory management model and an efficient, load-balancing goal scheduling strategy are presented. It is shown how, for systems which support "don't know" non-determinism, special care has to be taken during goal scheduling if the space recovery characteristics of sequential systems are to be preserved. A solution based on selecting only "newer" goals for execution is described, and an algorithm is proposed for efficiently maintaining and determining precedence relationships and variable ages across parallel goals. It is argued that the proposed schemes and algorithms make it possible to extend the storage performance of sequential systems to parallel execution without the considerable overhead previously associated with it. The results are applicable to a wide class of parallel and coroutining systems, and they represent an efficient alternative to "all heap" or "spaghetti stack" allocation models.

An abstract machine based execution model for computer architecture design and efficient implementation of logic programs in parallel.

The term "Logic Programming" refers to a variety of computer languages and execution models which are based on the traditional concept of Symbolic Logic. The expressive power of these languages offers promise to be of great assistance in facing the programming challenges of present and future symbolic processing applications in Artificial Intelligence, Knowledge-based systems, and many other areas of computing. The sequential execution speed of logic programs has been greatly improved since the advent of the first interpreters. However, higher inference speeds are still required in order to meet the demands of applications such as those contemplated for next generation computer systems. The execution of logic programs in parallel is currently considered a promising strategy for attaining such inference speeds. Logic Programming in turn appears as a suitable programming paradigm for parallel architectures because of the many opportunities for parallel execution present in the implementation of logic programs. This dissertation presents an efficient parallel execution model for logic programs. The model is described from the source language level down to an "Abstract Machine" level suitable for direct implementation on existing parallel systems or for the design of special purpose parallel architectures. Few assumptions are made at the source language level and therefore the techniques developed and the general Abstract Machine design are applicable to a variety of logic (and also functional) languages. These techniques offer efficient solutions to several areas of parallel Logic Programming implementation previously considered problematic or a source of considerable overhead, such as the detection and handling of variable binding conflicts in AND-Parallelism, the specification of control and management of the execution tree, the treatment of distributed backtracking, and goal scheduling and memory management issues, etc. A parallel Abstract Machine design is offered, specifying data areas, operation, and a suitable instruction set. This design is based on extending to a parallel environment the techniques introduced by the Warren Abstract Machine, which have already made very fast and space efficient sequential systems a reality. Therefore, the model herein presented is capable of retaining sequential execution speed similar to that of high performance sequential systems, while extracting additional gains in speed by efficiently implementing parallel execution. These claims are supported by simulations of the Abstract Machine on sample programs.