Improvement of the Dynamic Performance of a Buck Converter using Controlled Current Source as an Additional Energy Path

This work is related to the improvement of the dynamic performance of the Buck converter by means of introducing an additional power path that virtually increase s the output capacitance during transients, thus improving the output impedance of the converter. It is well known that in VRM applications, with wide load steps, voltage overshoots and undershoots ma y lead to undesired performance of the load. To solve this problem, high-bandwidth high-switching frequency power converter s can be applied to reduce the transient time or a big output capacitor can be applied to reduce the output impedance. The first solution can degrade the efficiency by increasing switching losses of the MOSFETS, and the second solution is penalizing the cost and size of the output filter. The additional energy path, as presented here, is introduced with the Output Impedance Correction Circuit (OICC) based on the Controlled Current Source (CCS). The OICC is using CCS to inject or extract a current n - 1 times larger than the output capacitor current, thus virtually increasing n times the value of the output capacitance during the transients. This feature allows the usage of a low frequency Buck converter with smaller capacitor but satisfying the dynamic requirements.

Hybrid behavioral-analytical loss model for a high frequency and low load DC/DC buck converter

This work presents a behavioral-analytical hybrid loss model for a buck converter. The model has been designed for a wide operating frequency range up to 4MHz and a low power range (below 20W). It is focused on the switching losses obtained in the power MOSFETs. Main advantages of the model are the fast calculation time (below 8.5 seconds) and a good accuracy, which makes this model suitable for the optimization process of the losses in the design of a converter. It has been validated by simulation and experimentally with one GaN power transistor and three Si MOSFETs. Results show good agreement between measurements and the model

Envelope Amplifier Based on a Hybrid Series Converter With The Slow-envelope Technique

High frequency dc-dc switching converters are used as envelope amplifiers in RF transmitters. The dc-dc converter should operate at very high frequency to track an envelope in the MHz range to supply the power amplifier. One of the circuits suitable for this application is a hybrid topology composed of a switched converter and a linear regulator in series that work together to adjust the output voltage to track the envelope with accuracy. This topology can take advantage of the reduced slew-rate technique where switching dc-dc converter provides the RF envelope with limited slew rate in order to avoid high switching frequency and high power losses, while the linear regulator performs fine adjustment in order to obtain the exact replica of the RF envelope. The combination of this control technique with this topology is proposed in this paper. Envelopes with different bandwidth will be considered to optimize the efficiency of the dc-dc converter. The calculations and experiments have been done to track a 2MHz envelope in the range 0-12V for an EER RF transmitter.

Adaptive Control for ZVS Three Phase Full Active Bridge Converter with ARCN

This paper presents an adaptive control for the auxiliary circuit, called ARCN (Auxiliary Resonant Commutating Network), used to achieve ZVS in full active bridge converters under a wide load range. Depending on the load conditions, the proposed control adapts the timing of the ARCN to minimize the losses. The principle of operation and implementation considerations are presented for a three phase full active bridge converter, proposing different methods to implement the control according to the specifications. The experimental results shown verify the proposed methodology.

Multiple Input-Output Bidirectional Solid State Transformer Based on a Series Resonant Converter

Las fuentes de alimentación de modo conmutado (SMPS en sus siglas en inglés) se utilizan ampliamente en una gran variedad de aplicaciones. La tarea más difícil para los diseñadores de SMPS consiste en lograr simultáneamente la operación del convertidor con alto rendimiento y alta densidad de energía. El tamaño y el peso de un convertidor de potencia está dominado por los componentes pasivos, ya que estos elementos son normalmente más grandes y más pesados que otros elementos en el circuito. Para una potencia de salida dada, la cantidad de energía almacenada en el convertidor que ha de ser entregada a la carga en cada ciclo de conmutación, es inversamente proporcional a la frecuencia de conmutación del convertidor. Por lo tanto, el aumento de la frecuencia de conmutación se considera un medio para lograr soluciones más compactas con los niveles de densidad de potencia más altos. La importancia de investigar en el rango de alta frecuencia de conmutación radica en todos los beneficios que se pueden lograr: además de la reducción en el tamaño de los componentes pasivos, el aumento de la frecuencia de conmutación puede mejorar significativamente prestaciones dinámicas de convertidores de potencia. Almacenamiento de energía pequeña y el período de conmutación corto conducen a una respuesta transitoria del convertidor más rápida en presencia de las variaciones de la tensión de entrada o de la carga. Las limitaciones más importantes del incremento de la frecuencia de conmutación se relacionan con mayores pérdidas del núcleo magnético convencional, así como las pérdidas de los devanados debido a los efectos pelicular y proximidad. También, un problema potencial es el aumento de los efectos de los elementos parásitos de los componentes magnéticos - inductancia de dispersión y la capacidad entre los devanados - que causan pérdidas adicionales debido a las corrientes no deseadas. Otro factor limitante supone el incremento de las pérdidas de conmutación y el aumento de la influencia de los elementos parásitos (pistas de circuitos impresos, interconexiones y empaquetado) en el comportamiento del circuito. El uso de topologías resonantes puede abordar estos problemas mediante el uso de las técnicas de conmutaciones suaves para reducir las pérdidas de conmutación incorporando los parásitos en los elementos del circuito. Sin embargo, las mejoras de rendimiento se reducen significativamente debido a las corrientes circulantes cuando el convertidor opera fuera de las condiciones de funcionamiento nominales. A medida que la tensión de entrada o la carga cambian las corrientes circulantes incrementan en comparación con aquellos en condiciones de funcionamiento nominales. Se pueden obtener muchos beneficios potenciales de la operación de convertidores resonantes a más alta frecuencia si se emplean en aplicaciones con condiciones de tensión de entrada favorables como las que se encuentran en las arquitecturas de potencia distribuidas. La regulación de la carga y en particular la regulación de la tensión de entrada reducen tanto la densidad de potencia del convertidor como el rendimiento. Debido a la relativamente constante tensión de bus que se encuentra en arquitecturas de potencia distribuidas los convertidores resonantes son adecuados para el uso en convertidores de tipo bus (transformadores cc/cc de estado sólido). En el mercado ya están disponibles productos comerciales de transformadores cc/cc de dos puertos que tienen muy alta densidad de potencia y alto rendimiento se basan en convertidor resonante serie que opera justo en la frecuencia de resonancia y en el orden de los megahercios. Sin embargo, las mejoras futuras en el rendimiento de las arquitecturas de potencia se esperan que vengan del uso de dos o más buses de distribución de baja tensión en vez de una sola. Teniendo eso en cuenta, el objetivo principal de esta tesis es aplicar el concepto del convertidor resonante serie que funciona en su punto óptimo en un nuevo transformador cc/cc bidireccional de puertos múltiples para atender las necesidades futuras de las arquitecturas de potencia. El nuevo transformador cc/cc bidireccional de puertos múltiples se basa en la topología de convertidor resonante serie y reduce a sólo uno el número de componentes magnéticos. Conmutaciones suaves de los interruptores hacen que sea posible la operación en las altas frecuencias de conmutación para alcanzar altas densidades de potencia. Los problemas posibles con respecto a inductancias parásitas se eliminan, ya que se absorben en los Resumen elementos del circuito. El convertidor se caracteriza con una muy buena regulación de la carga propia y cruzada debido a sus pequeñas impedancias de salida intrínsecas. El transformador cc/cc de puertos múltiples opera a una frecuencia de conmutación fija y sin regulación de la tensión de entrada. En esta tesis se analiza de forma teórica y en profundidad el funcionamiento y el diseño de la topología y del transformador, modelándolos en detalle para poder optimizar su diseño. Los resultados experimentales obtenidos se corresponden con gran exactitud a aquellos proporcionados por los modelos. El efecto de los elementos parásitos son críticos y afectan a diferentes aspectos del convertidor, regulación de la tensión de salida, pérdidas de conducción, regulación cruzada, etc. También se obtienen los criterios de diseño para seleccionar los valores de los condensadores de resonancia para lograr diferentes objetivos de diseño, tales como pérdidas de conducción mínimas, la eliminación de la regulación cruzada o conmutación en apagado con corriente cero en plena carga de todos los puentes secundarios. Las conmutaciones en encendido con tensión cero en todos los interruptores se consiguen ajustando el entrehierro para obtener una inductancia magnetizante finita en el transformador. Se propone, además, un cambio en los señales de disparo para conseguir que la operación con conmutaciones en apagado con corriente cero de todos los puentes secundarios sea independiente de la variación de la carga y de las tolerancias de los condensadores resonantes. La viabilidad de la topología propuesta se verifica a través una extensa tarea de simulación y el trabajo experimental. La optimización del diseño del transformador de alta frecuencia también se aborda en este trabajo, ya que es el componente más voluminoso en el convertidor. El impacto de de la duración del tiempo muerto y el tamaño del entrehierro en el rendimiento del convertidor se analizan en un ejemplo de diseño de transformador cc/cc de tres puertos y cientos de vatios de potencia. En la parte final de esta investigación se considera la implementación y el análisis de las prestaciones de un transformador cc/cc de cuatro puertos para una aplicación de muy baja tensión y de decenas de vatios de potencia, y sin requisitos de aislamiento. Abstract Recently, switch mode power supplies (SMPS) have been used in a great variety of applications. The most challenging issue for designers of SMPS is to achieve simultaneously high efficiency operation at high power density. The size and weight of a power converter is dominated by the passive components since these elements are normally larger and heavier than other elements in the circuit. If the output power is constant, the stored amount of energy in the converter which is to be delivered to the load in each switching cycle is inversely proportional to the converter’s switching frequency. Therefore, increasing the switching frequency is considered a mean to achieve more compact solutions at higher power density levels. The importance of investigation in high switching frequency range comes from all the benefits that can be achieved. Besides the reduction in size of passive components, increasing switching frequency can significantly improve dynamic performances of power converters. Small energy storage and short switching period lead to faster transient response of the converter against the input voltage and load variations. The most important limitations for pushing up the switching frequency are related to increased conventional magnetic core loss as well as the winding loss due to the skin and proximity effect. A potential problem is also increased magnetic parasitics – leakage inductance and capacitance between the windings – that cause additional loss due to unwanted currents. Higher switching loss and the increased influence of printed circuit boards, interconnections and packaging on circuit behavior is another limiting factor. Resonant power conversion can address these problems by using soft switching techniques to reduce switching loss incorporating the parasitics into the circuit elements. However the performance gains are significantly reduced due to the circulating currents when the converter operates out of the nominal operating conditions. As the input voltage or the load change the circulating currents become higher comparing to those ones at nominal operating conditions. Multiple Input-Output Many potential gains from operating resonant converters at higher switching frequency can be obtained if they are employed in applications with favorable input voltage conditions such as those found in distributed power architectures. Load and particularly input voltage regulation reduce a converter’s power density and efficiency. Due to a relatively constant bus voltage in distributed power architectures the resonant converters are suitable for bus voltage conversion (dc/dc or solid state transformation). Unregulated two port dc/dc transformer products achieving very high power density and efficiency figures are based on series resonant converter operating just at the resonant frequency and operating in the megahertz range are already available in the market. However, further efficiency improvements of power architectures are expected to come from using two or more separate low voltage distribution buses instead of a single one. The principal objective of this dissertation is to implement the concept of the series resonant converter operating at its optimum point into a novel bidirectional multiple port dc/dc transformer to address the future needs of power architectures. The new multiple port dc/dc transformer is based on a series resonant converter topology and reduces to only one the number of magnetic components. Soft switching commutations make possible high switching frequencies to be adopted and high power densities to be achieved. Possible problems regarding stray inductances are eliminated since they are absorbed into the circuit elements. The converter features very good inherent load and cross regulation due to the small output impedances. The proposed multiple port dc/dc transformer operates at fixed switching frequency without line regulation. Extensive theoretical analysis of the topology and modeling in details are provided in order to compare with the experimental results. The relationships that show how the output voltage regulation and conduction losses are affected by the circuit parasitics are derived. The methods to select the resonant capacitor values to achieve different design goals such as minimum conduction losses, elimination of cross regulation or ZCS operation at full load of all the secondary side bridges are discussed. ZVS turn-on of all the switches is achieved by relying on the finite magnetizing inductance of the Abstract transformer. A change of the driving pattern is proposed to achieve ZCS operation of all the secondary side bridges independent on load variations or resonant capacitor tolerances. The feasibility of the proposed topology is verified through extensive simulation and experimental work. The optimization of the high frequency transformer design is also addressed in this work since it is the most bulky component in the converter. The impact of dead time interval and the gap size on the overall converter efficiency is analyzed on the design example of the three port dc/dc transformer of several hundreds of watts of the output power for high voltage applications. The final part of this research considers the implementation and performance analysis of the four port dc/dc transformer in a low voltage application of tens of watts of the output power and without isolation requirements.

Minimum time control for multiphase buck converter: analysis and application

The combination of minimum time control and multiphase converter is a favorable option for dc-dc converters in applications where output voltage variation is required, such as RF amplifiers and dynamic voltage scaling in microprocessors, due to their advantage of fast dynamic response. In this paper, an improved minimum time control approach for multiphase buck converter that is based on charge balance technique, aiming at fast output voltage transition is presented. Compared with the traditional method, the proposed control takes into account the phase delay and current ripple in each phase. Therefore, by investigating the behavior of multiphase converter during voltage transition, it resolves the problem of current unbalance after the transient, which can lead to long settling time of the output voltage. The restriction of this control is that the output voltage that the converter can provide is related to the number of the phases, because only the duty cycles at which the multiphase converter has total ripple cancellation are used in this approach. The model of the proposed control is introduced, and the design constraints of the buck converters filter for this control are discussed. In order to prove the concept, a four-phase buck converter is implemented and the experimental results that validate the proposed control method are presented. The application of this control to RF envelope tracking is also presented in this paper.

Space-state robust control of a Buck converter with amorphous core coil and variable load

Pulse-width modulation is widely used to control electronic converters. One of the most frequently used topologies for high DC voltage/low DC voltage conversion is the Buck converter. These converters are described by a second order system with an LC filter between the switching subsystem and the load. The use of a coil with an amorphous magnetic material core rather than an air core permits the design of smaller converters. If high switching frequencies are used to obtain high quality voltage output, then the value of the auto inductance L is reduced over time. Robust controllers are thus needed if the accuracy of the converter response must be preserved under auto inductance and payload variations. This paper presents a robust controller for a Buck converter based on a state space feedback control system combined with an additional virtual space variable which minimizes the effects of the inductance and load variations when a switching frequency that is not too high is applied. The system exhibits a null steady-state average error response for the entire range of parameter variations. Simulation results and a comparison with a standard PID controller are also presented.

Transformer-coupled converter for voltage modulation techniques

In high performance digital systems as well as in RF systems, voltage scaling and modulation techniques have been adopted to achieve a more efficient processing of the energy. The implementation of such techniques relies on a power supply that is capable of rapidly adjusting the system supply voltage. In this paper, a pulsewidth modulation multiphase topology with magnetic coupling is proposed for its use in voltage modulation techniques. Since the magnetic coupling in this topology is done with transformers instead of coupled inductors, the energy storage is reduced and very fast voltage changes are achieved. Advantages and drawbacks of this topology have been previously presented in the literature and in this paper, the design criteria for implementing a power supply for the envelope elimination and restoration technique in an RF system are presented along with an implementation of the power supply.

Effect of control method on impedance-based interactions in a buck converter

All the interconnected regulated systems are prone to impedance-based interactions making them sensitive to instability and transient-performance degradation. The applied control method affects significantly the characteristics of the converter in terms of sensitivity to different impedance interactions. This paper provides for the first time the whole set of impedance-type internal parameters and the formulas according to which the interaction sensitivity can be fully explained and analyzed. The formulation given in this paper can be utilized equally either based on measured frequency responses or on predicted analytic transfer functions. Usually, the distributed dc-dc systems are constructed by using ready-made power modules without having thorough knowledge on the actual power-stage and control-system designs. As a consequence, the interaction characterization has to be based on the frequency responses measureable via the input and output terminals. A buck converter with four different control methods is experimentally characterized in frequency domain to demonstrate the effect of control method on the interaction sensitivity. The presented analytical models are used to explain the phenomena behind the changes in the interaction sensitivity.

Improvement of the Dynamic Performance of a Multiphase Current Controlled Buck Converter using an Auxiliary Synchronous Buck Converter as an Additional Energy Path

This work is related to the output impedance improvement of a Multiphase Buck converter with Peak Current Mode Control (PCMC) by means of introducing an additional power path that virtually increases the output capacitance during transients. Various solutions that can be employed to improve the dynamic behavior of the converter system exist, but nearly all solutions are developed for a Single Phase Buck converter with Voltage Mode Control (VMC), while in the VRM applications, due to the high currents, the system is usually implemented as a Multiphase Buck Converter with Current Mode Control. The additional energy path, as presented here, is introduced with the Output Impedance Correction Circuit (OICC) based on the Controlled Current Source (CCS). The OICC is used to inject or extract a current n-1 times larger than the output capacitor current, thus virtually increasing n times the value of the output capacitance during the transients. Furthermore, this work extends the OICC concept to a Multiphase Buck Converter system while comparing proposed solution with the system that has n times bigger output capacitor. In addition, the OICC is implemented as a Synchronous Buck Converter with PCMC, thus reducing its influence on the system efficiency.

Bidirectional multiple port dc/dc transformer based on a series resonant converter

In this paper a novel bidirectional multiple port dc/dc transformer topology is presented. The novel concept for dc/dc transformer is based on the Series Resonant Converter (SRC)topology operated at its resonant frequency point. This allows for higher switching frequency to be adopted and enables high efficiency/high power density operation. The feasibility of the proposed concept is verified on a 300W, 700 kHz three port prototype with 390V input voltage and 48V and 12V output voltages. A peak overall efficiency of 93% is measured at full load. A very good load and cross regulation characteristic of the converter is observed in the whole load range, from full load to open circuit. The sensitivity analysis of the resonant capacitance is also performed showing very slight deterioration in the converter performances when a resonant capacitor is changed ±30% of its nominal value.

Analysis and validation of a multiple output series resonant converter

In this paper a novel bidirectional multiple port dc/dc transformer topology is presented. The novel concept for dc/dc transformer is based on the Series Resonant Converter (SRC) topology operated at its resonant frequency point. This allows for higher switching frequency to be adopted and enables high efficiency/high power density operation. The feasibility of the proposed concept is verified on a 300W, 700 kHz three port prototype with 390V input voltage and 48V and 12V output voltages. A peak overall efficiency of 93% is measured at full load. A very good load and cross regulation characteristic of the converter is observed in the whole load range, from full load to open circuit. The sensitivity analysis of the resonant capacitance is also performed showing very slight deterioration in the converter performances when a resonant capacitor is changed ±30% of its nominal value.

Ripple cancellation technique applied to a synchronous buck converter to achieve very high bandwidth and very high efficiency envelope amplifier

This work presents a single stage converter for a high bandwidth and a high efficiency envelope amplifier. The current ripple cancellation technique is applied to a synchronous buck converter to cancel the output current ripple and to decrease the switching frequency without a reduction in the large signal bandwidth. The converter is modeled and the new design with ripple cancellation circuit is detailed. The advantages of the proposed design are presented and validated experimentally. The transfer function of the output filter of the buck converter with ripple cancellation circuit has been modeled and compared to measurements, showing a good correspondence. Experimental validation is provided at 4MHz of switching frequency for DC and variable output voltage for a sinusoidal and a 64QAM signal. Additional experimental validation of the efficiency improvement is provided, compared to the equivalent design (same bandwidth and output voltage ripple) of the conventional buck converter.

Multiphase Current Controlled Buck Converter with energy recycling Output Impedance Correction Circuit (OICC)

This work is related to the output impedance improvement of a Multiphase Buck converter with Peak Current Mode Control (PCMC) by means of introducing an additional power path that virtually increases the output capacitance during transients. Various solutions that can be employed to improve the dynamic behavior of the converter system exist, but nearly all solutions are developed for a Single Phase Buck converter with Voltage Mode Control (VMC), while in the VRM applications, due to the high currents, the system is usually implemented as a Multiphase Buck Converter with Current Mode Control. The Output Impedance Correction Circuit (OICC) is used to inject or extract a current n-1 times larger than the output capacitor current, thus virtually increasing n times the value of the output capacitance during the transients. Furthermore, this work extends the OICC concept to a Multiphase Buck Converter system while comparing proposed solution with the system that has n times bigger output capacitor. In addition, the OICC is implemented as a Synchronous Buck Converter with PCMC, thus reducing its influence on the system efficiency

Wide bandwidth envelope trackers with reduced switching frequency for RF power amplifier

El requerimiento de proveer alta frecuencia de datos en los modernos sistema de comunicación inalámbricos resulta en complejas señales moduladas de radio-frequencia (RF) con un gran ancho de banda y alto ratio pico-promedio (PAPR). Para garantizar la linealidad del comportamiento, los amplificadores lineales de potencia comunes funcionan típicamente entre 4 y 10 dB de back-o_ desde la máxima potencia de salida, ocasionando una baja eficiencia del sistema. La eliminación y restauración de la evolvente (EER) y el seguimiento de la evolvente (ET) son dos prometedoras técnicas para resolver el problema de la eficiencia. Tanto en EER como en ET, es complicado diseñar un amplificador de potencia que sea eficiente para señales de RF de alto ancho de banda y alto PAPR. Una propuesta común para los amplificadores de potencia es incluir un convertidor de potencia de muy alta eficiencia operando a frecuencias más altas que el ancho de banda de la señal RF. En este caso, la potencia perdida del convertidor ocasionado por la alta frecuencia desaconseja su práctica cuando el ancho de banda es muy alto. La solución a este problema es el enfoque de esta disertación que presenta dos arquitecturas de amplificador evolvente: convertidor híbrido-serie con una técnica de evolvente lenta y un convertidor multinivel basado en un convertidor reductor multifase con control de tiempo mínimo. En la primera arquitectura, una topología híbrida está compuesta de una convertidor reductor conmutado y un regulador lineal en serie que trabajan juntos para ajustar la tensión de salida para seguir a la evolvente con precisión. Un algoritmo de generación de una evolvente lenta crea una forma de onda con una pendiente limitada que es menor que la pendiente máxima de la evolvente original. La salida del convertidor reductor sigue esa forma de onda en vez de la evolvente original usando una menor frecuencia de conmutación, porque la forma de onda no sólo tiene una pendiente reducida sino también un menor ancho de banda. De esta forma, el regulador lineal se usa para filtrar la forma de onda tiene una pérdida de potencia adicional. Dependiendo de cuánto se puede reducir la pendiente de la evolvente para producir la forma de onda, existe un trade-off entre la pérdida de potencia del convertidor reductor relacionada con la frecuencia de conmutación y el regulador lineal. El punto óptimo referido a la menor pérdida de potencia total del amplificador de evolvente es capaz de identificarse con la ayuda de modelo preciso de pérdidas que es una combinación de modelos comportamentales y analíticos de pérdidas. Además, se analiza el efecto en la respuesta del filtro de salida del convertidor reductor. Un filtro de dampeo paralelo extra es necesario para eliminar la oscilación resonante del filtro de salida porque el convertidor reductor opera en lazo abierto. La segunda arquitectura es un amplificador de evolvente de seguimiento de tensión multinivel. Al contrario que los convertidores que usan multi-fuentes, un convertidor reductor multifase se emplea para generar la tensión multinivel. En régimen permanente, el convertidor reductor opera en puntos del ciclo de trabajo con cancelación completa del rizado. El número de niveles de tensión es igual al número de fases de acuerdo a las características del entrelazamiento del convertidor reductor. En la transición, un control de tiempo mínimo (MTC) para convertidores multifase es novedosamente propuesto y desarrollado para cambiar la tensión de salida del convertidor reductor entre diferentes niveles. A diferencia de controles convencionales de tiempo mínimo para convertidores multifase con inductancia equivalente, el propuesto MTC considera el rizado de corriente por cada fase basado en un desfase fijo que resulta en diferentes esquemas de control entre las fases. La ventaja de este control es que todas las corrientes vuelven a su fase en régimen permanente después de la transición para que la siguiente transición pueda empezar muy pronto, lo que es muy favorable para la aplicación de seguimiento de tensión multinivel. Además, el control es independiente de la carga y no es afectado por corrientes de fase desbalanceadas. Al igual que en la primera arquitectura, hay una etapa lineal con la misma función, conectada en serie con el convertidor reductor multifase. Dado que tanto el régimen permanente como el estado de transición del convertidor no están fuertemente relacionados con la frecuencia de conmutación, la frecuencia de conmutación puede ser reducida para el alto ancho de banda de la evolvente, la cual es la principal consideración de esta arquitectura. La optimización de la segunda arquitectura para más alto anchos de banda de la evolvente es presentada incluyendo el diseño del filtro de salida, la frecuencia de conmutación y el número de fases. El área de diseño del filtro está restringido por la transición rápida y el mínimo pulso del hardware. La rápida transición necesita un filtro pequeño pero la limitación del pulso mínimo del hardware lleva el diseño en el sentido contrario. La frecuencia de conmutación del convertidor afecta principalmente a la limitación del mínimo pulso y a las pérdidas de potencia. Con una menor frecuencia de conmutación, el ancho de pulso en la transición es más pequeño. El número de fases relativo a la aplicación específica puede ser optimizado en términos de la eficiencia global. Otro aspecto de la optimización es mejorar la estrategia de control. La transición permite seguir algunas partes de la evolvente que son más rápidas de lo que el hardware puede soportar al precio de complejidad. El nuevo método de sincronización de la transición incrementa la frecuencia de la transición, permitiendo que la tensión multinivel esté más cerca de la evolvente. Ambas estrategias permiten que el convertidor pueda seguir una evolvente con un ancho de banda más alto que la limitación de la etapa de potencia. El modelo de pérdidas del amplificador de evolvente se ha detallado y validado mediante medidas. El mecanismo de pérdidas de potencia del convertidor reductor tiene que incluir las transiciones en tiempo real, lo cual es diferente del clásico modelos de pérdidas de un convertidor reductor síncrono. Este modelo estima la eficiencia del sistema y juega un papel muy importante en el proceso de optimización. Finalmente, la segunda arquitectura del amplificador de evolvente se integra con el amplificador de clase F. La medida del sistema EER prueba el ahorro de energía con el amplificador de evolvente propuesto sin perjudicar la linealidad del sistema. ABSTRACT The requirement of delivering high data rates in modern wireless communication systems results in complex modulated RF signals with wide bandwidth and high peak-to-average ratio (PAPR). In order to guarantee the linearity performance, the conventional linear power amplifiers typically work at 4 to 10 dB back-off from the maximum output power, leading to low system efficiency. The envelope elimination and restoration (EER) and envelope tracking (ET) are two promising techniques to overcome the efficiency problem. In both EER and ET, it is challenging to design efficient envelope amplifier for wide bandwidth and high PAPR RF signals. An usual approach for envelope amplifier includes a high-efficiency switching power converter operating at a frequency higher than the RF signal's bandwidth. In this case, the power loss of converter caused by high switching operation becomes unbearable for system efficiency when signal bandwidth is very wide. The solution of this problem is the focus of this dissertation that presents two architectures of envelope amplifier: a hybrid series converter with slow-envelope technique and a multilevel converter based on a multiphase buck converter with the minimum time control. In the first architecture, a hybrid topology is composed of a switched buck converter and a linear regulator in series that work together to adjust the output voltage to track the envelope with accuracy. A slow envelope generation algorithm yields a waveform with limited slew rate that is lower than the maximum slew rate of the original envelope. The buck converter's output follows this waveform instead of the original envelope using lower switching frequency, because the waveform has not only reduced slew rate but also reduced bandwidth. In this way, the linear regulator used to filter the waveform has additional power loss. Depending on how much reduction of the slew rate of envelope in order to obtain that waveform, there is a trade-off between the power loss of buck converter related to the switching frequency and the power loss of linear regulator. The optimal point referring to the lowest total power loss of this envelope amplifier is identified with the help of a precise power loss model that is a combination of behavioral and analytic loss model. In addition, the output filter's effect on the response is analyzed. An extra parallel damping filter is needed to eliminate the resonant oscillation of output filter L and C, because the buck converter operates in open loop. The second architecture is a multilevel voltage tracking envelope amplifier. Unlike the converters using multi-sources, a multiphase buck converter is employed to generate the multilevel voltage. In the steady state, the buck converter operates at complete ripple cancellation points of duty cycle. The number of the voltage levels is equal to the number of phases according the characteristics of interleaved buck converter. In the transition, a minimum time control (MTC) for multiphase converter is originally proposed and developed for changing the output voltage of buck converter between different levels. As opposed to conventional minimum time control for multiphase converter with equivalent inductance, the proposed MTC considers the current ripple of each phase based on the fixed phase shift resulting in different control schemes among the phases. The advantage of this control is that all the phase current return to the steady state after the transition so that the next transition can be triggered very soon, which is very favorable for the application of multilevel voltage tracking. Besides, the control is independent on the load condition and not affected by the unbalance of phase current. Like the first architecture, there is also a linear stage with the same function, connected in series with the multiphase buck converter. Since both steady state and transition state of the converter are not strongly related to the switching frequency, it can be reduced for wide bandwidth envelope which is the main consideration of this architecture. The optimization of the second architecture for wider bandwidth envelope is presented including the output filter design, switching frequency and the number of phases. The filter design area is restrained by fast transition and the minimum pulse of hardware. The fast transition needs small filter but the minimum pulse of hardware limitation pushes the filter in opposite way. The converter switching frequency mainly affects the minimum pulse limitation and the power loss. With lower switching frequency, the pulse width in the transition is smaller. The number of phases related to specific application can be optimized in terms of overall efficiency. Another aspect of optimization is improving control strategy. Transition shift allows tracking some parts of envelope that are faster than the hardware can support at the price of complexity. The new transition synchronization method increases the frequency of transition, allowing the multilevel voltage to be closer to the envelope. Both control strategies push the converter to track wider bandwidth envelope than the limitation of power stage. The power loss model of envelope amplifier is detailed and validated by measurements. The power loss mechanism of buck converter has to include the transitions in real time operation, which is different from classical power loss model of synchronous buck converter. This model estimates the system efficiency and play a very important role in optimization process. Finally, the second envelope amplifier architecture is integrated with a Class F amplifier. EER system measurement proves the power saving with the proposed envelope amplifier without disrupting the linearity performance.